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Commit 90df0360 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'samsung-dt-5.6' of... 

Merge tag 'samsung-dt-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt

Samsung DTS ARM changes for v5.6

1. Couple ARM and wcore bus regulators on Exynos542x so higher
   frequencies could be used with dynamic voltage and frequency scaling.
   Enable this higher frequencies.
2. Correct the polarity of USB3503 hub GPIOs.
3. Adjust the bus frequencies (scaled with devfreq framework) on
   Exynos5422 Odroid boards to match values possible to obtain from root
   PLLs.
4. Add display to Tiny4412 board.
5. Cleanups and minor improvements.

* tag 'samsung-dt-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: dts: exynos: Enable FIMD node and add proper panel node to Tiny4412
  ARM: dts: samsung: Rename Samsung and Exynos to lowercase
  ARM: dts: exynos: Adjust bus related OPPs to the values correct for Exynos5422 Odroids
  ARM: dts: exynos: Move Exynos5420 bus related OPPs to the Odroid boards DTS
  ARM: dts: exynos: Correct USB3503 GPIOs polarity
  ARM: dts: exynos: Add missing CPU frequencies for Exynos5422/5800
  ARM: dts: exynos: Add initial data for coupled regulators for Exynos5422/5800
  ARM: dts: exynos: Remove syscon compatible from chipid node on Exynos5

Link: https://lore.kernel.org/r/20200110172334.4767-3-krzk@kernel.orgSigned-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 76c1f415 dc48a3a7
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arch/arm/boot/dts/exynos4412-odroid-common.dtsi
View file @ 90df0360
......@@ -267,7 +267,7 @@ usb3503: usb3503@8 {
intn-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>;
connect-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
initial-mode = <1>;
};
......
arch/arm/boot/dts/exynos4412-tiny4412.dts
View file @ 90df0360
......@@ -66,6 +66,31 @@ xusbxti {
clock-frequency = <24000000>;
};
};
panel {
compatible = "innolux,at070tn92";
port {
panel_input: endpoint {
remote-endpoint = <&lcdc_output>;
};
};
};
};
&fimd {
pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port@3 {
reg = <3>;
lcdc_output: endpoint {
remote-endpoint = <&panel_input>;
};
};
};
&rtc {
......
arch/arm/boot/dts/exynos5.dtsi
View file @ 90df0360
......@@ -36,7 +36,7 @@ soc: soc {
ranges;
chipid: chipid@10000000 {
compatible = "samsung,exynos4210-chipid", "syscon";
compatible = "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
};
......
arch/arm/boot/dts/exynos5250-arndale.dts
View file @ 90df0360
......@@ -15,7 +15,7 @@
#include "exynos5250.dtsi"
/ {
model = "Insignal Arndale evaluation board based on EXYNOS5250";
model = "Insignal Arndale evaluation board based on Exynos5250";
compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5";
memory@40000000 {
......@@ -154,7 +154,7 @@ usb_hub: usb-hub {
compatible = "smsc,usb3503a";
reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
connect-gpios = <&gpd1 7 GPIO_ACTIVE_LOW>;
connect-gpios = <&gpd1 7 GPIO_ACTIVE_HIGH>;
};
};
......
arch/arm/boot/dts/exynos5250-smdk5250.dts
View file @ 90df0360
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG SMDK5250 board device tree source
* Samsung SMDK5250 board device tree source
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
......@@ -12,7 +12,7 @@
#include "exynos5250.dtsi"
/ {
model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
model = "Samsung SMDK5250 board based on Exynos5250";
compatible = "samsung,smdk5250", "samsung,exynos5250", "samsung,exynos5";
aliases {
......
arch/arm/boot/dts/exynos5250.dtsi
View file @ 90df0360
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG EXYNOS5250 SoC device tree source
* Samsung Exynos5250 SoC device tree source
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
* EXYNOS5250 based board files can include this file and provide
* Samsung Exynos5250 SoC device nodes are listed in this file.
* Exynos5250 based board files can include this file and provide
* values for board specfic bindings.
*
* Note: This file does not include device nodes for all the controllers in
* EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
* Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
* additional nodes can be added to this file.
*/
......
arch/arm/boot/dts/exynos5260-xyref5260.dts
View file @ 90df0360
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG XYREF5260 board device tree source
* Samsung XYREF5260 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
......@@ -10,7 +10,7 @@
#include "exynos5260.dtsi"
/ {
model = "SAMSUNG XYREF5260 board based on EXYNOS5260";
model = "Samsung XYREF5260 board based on Exynos5260";
compatible = "samsung,xyref5260", "samsung,exynos5260", "samsung,exynos5";
memory@20000000 {
......
arch/arm/boot/dts/exynos5260.dtsi
View file @ 90df0360
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG EXYNOS5260 SoC device tree source
* Samsung Exynos5260 SoC device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
......
arch/arm/boot/dts/exynos5410-odroidxu.dts
View file @ 90df0360
......@@ -170,7 +170,7 @@ usb3503: usb-hub@8 {
intn-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
connect-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpx1 4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpx1 4 GPIO_ACTIVE_LOW>;
initial-mode = <1>;
clock-names = "refclk";
......
arch/arm/boot/dts/exynos5410-smdk5410.dts
View file @ 90df0360
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG SMDK5410 board device tree source
* Samsung SMDK5410 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
......@@ -10,7 +10,7 @@
#include "exynos5410.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Samsung SMDK5410 board based on EXYNOS5410";
model = "Samsung SMDK5410 board based on Exynos5410";
compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5";
memory@40000000 {
......
arch/arm/boot/dts/exynos5410.dtsi
View file @ 90df0360
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG EXYNOS5410 SoC device tree source
* Samsung Exynos5410 SoC device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
* EXYNOS5410 based board files can include this file and provide
* Samsung Exynos5410 SoC device nodes are listed in this file.
* Exynos5410 based board files can include this file and provide
* values for board specfic bindings.
*/
......
arch/arm/boot/dts/exynos5420-arndale-octa.dts
View file @ 90df0360
......@@ -15,7 +15,7 @@
#include <dt-bindings/clock/samsung,s2mps11.h>
/ {
model = "Insignal Arndale Octa evaluation board based on EXYNOS5420";
model = "Insignal Arndale Octa evaluation board based on Exynos5420";
compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5";
memory@20000000 {
......
arch/arm/boot/dts/exynos5420-cpus.dtsi
View file @ 90df0360
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG EXYNOS5420 SoC cpu device tree source
* Samsung Exynos5420 SoC cpu device tree source
*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
......
arch/arm/boot/dts/exynos5420-smdk5420.dts
View file @ 90df0360
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG SMDK5420 board device tree source
* Samsung SMDK5420 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
......@@ -12,7 +12,7 @@
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Samsung SMDK5420 board based on EXYNOS5420";
model = "Samsung SMDK5420 board based on Exynos5420";
compatible = "samsung,smdk5420", "samsung,exynos5420", "samsung,exynos5";
memory@20000000 {
......
arch/arm/boot/dts/exynos5420.dtsi
View file @ 90df0360
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG EXYNOS5420 SoC device tree source
* Samsung Exynos5420 SoC device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* SAMSUNG EXYNOS5420 SoC device nodes are listed in this file.
* EXYNOS5420 based board files can include this file and provide
* Samsung Exynos5420 SoC device nodes are listed in this file.
* Exynos5420 based board files can include this file and provide
* values for board specfic bindings.
*/
......@@ -48,62 +48,62 @@ cluster_a15_opp_table: opp_table0 {
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1250000>;
opp-microvolt = <1250000 1250000 1500000>;
clock-latency-ns = <140000>;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <1212500>;
opp-microvolt = <1212500 1212500 1500000>;
clock-latency-ns = <140000>;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <1175000>;
opp-microvolt = <1175000 1175000 1500000>;
clock-latency-ns = <140000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <1137500>;
opp-microvolt = <1137500 1137500 1500000>;
clock-latency-ns = <140000>;
};
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-microvolt = <1112500>;
opp-microvolt = <1112500 1112500 1500000>;
clock-latency-ns = <140000>;
};
opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1062500>;
opp-microvolt = <1062500 1062500 1500000>;
clock-latency-ns = <140000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1037500>;
opp-microvolt = <1037500 1037500 1500000>;
clock-latency-ns = <140000>;
};
opp-1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <1012500>;
opp-microvolt = <1012500 1012500 1500000>;
clock-latency-ns = <140000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = < 987500>;
opp-microvolt = < 987500 987500 1500000>;
clock-latency-ns = <140000>;
};
opp-900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = < 962500>;
opp-microvolt = < 962500 962500 1500000>;
clock-latency-ns = <140000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = < 937500>;
opp-microvolt = < 937500 937500 1500000>;
clock-latency-ns = <140000>;
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = < 912500>;
opp-microvolt = < 912500 912500 1500000>;
clock-latency-ns = <140000>;
};
};
......@@ -1092,7 +1092,6 @@ bus_wcore: bus_wcore {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
clock-names = "bus";
operating-points-v2 = <&bus_wcore_opp_table>;
status = "disabled";
};
......@@ -1100,7 +1099,6 @@ bus_noc: bus_noc {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK100_NOC>;
clock-names = "bus";
operating-points-v2 = <&bus_noc_opp_table>;
status = "disabled";
};
......@@ -1108,7 +1106,6 @@ bus_fsys_apb: bus_fsys_apb {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
clock-names = "bus";
operating-points-v2 = <&bus_fsys_apb_opp_table>;
status = "disabled";
};
......@@ -1116,7 +1113,6 @@ bus_fsys: bus_fsys {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
clock-names = "bus";
operating-points-v2 = <&bus_fsys_apb_opp_table>;
status = "disabled";
};
......@@ -1124,7 +1120,6 @@ bus_fsys2: bus_fsys2 {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
clock-names = "bus";
operating-points-v2 = <&bus_fsys2_opp_table>;
status = "disabled";
};
......@@ -1132,7 +1127,6 @@ bus_mfc: bus_mfc {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK333>;
clock-names = "bus";
operating-points-v2 = <&bus_mfc_opp_table>;
status = "disabled";
};
......@@ -1140,7 +1134,6 @@ bus_gen: bus_gen {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK266>;
clock-names = "bus";
operating-points-v2 = <&bus_gen_opp_table>;
status = "disabled";
};
......@@ -1148,7 +1141,6 @@ bus_peri: bus_peri {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK66>;
clock-names = "bus";
operating-points-v2 = <&bus_peri_opp_table>;
status = "disabled";
};
......@@ -1156,7 +1148,6 @@ bus_g2d: bus_g2d {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK333_G2D>;
clock-names = "bus";
operating-points-v2 = <&bus_g2d_opp_table>;
status = "disabled";
};
......@@ -1164,7 +1155,6 @@ bus_g2d_acp: bus_g2d_acp {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK266_G2D>;
clock-names = "bus";
operating-points-v2 = <&bus_g2d_acp_opp_table>;
status = "disabled";
};
......@@ -1172,7 +1162,6 @@ bus_jpeg: bus_jpeg {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
clock-names = "bus";
operating-points-v2 = <&bus_jpeg_opp_table>;
status = "disabled";
};
......@@ -1180,7 +1169,6 @@ bus_jpeg_apb: bus_jpeg_apb {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK166>;
clock-names = "bus";
operating-points-v2 = <&bus_jpeg_apb_opp_table>;
status = "disabled";
};
......@@ -1188,7 +1176,6 @@ bus_disp1_fimd: bus_disp1_fimd {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
clock-names = "bus";
operating-points-v2 = <&bus_disp1_fimd_opp_table>;
status = "disabled";
};
......@@ -1196,7 +1183,6 @@ bus_disp1: bus_disp1 {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
clock-names = "bus";
operating-points-v2 = <&bus_disp1_opp_table>;
status = "disabled";
};
......@@ -1204,7 +1190,6 @@ bus_gscl_scaler: bus_gscl_scaler {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
clock-names = "bus";
operating-points-v2 = <&bus_gscl_opp_table>;
status = "disabled";
};
......@@ -1212,252 +1197,8 @@ bus_mscl: bus_mscl {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
clock-names = "bus";
operating-points-v2 = <&bus_mscl_opp_table>;
status = "disabled";
};
bus_wcore_opp_table: opp_table2 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <84000000>;
opp-microvolt = <925000>;
};
opp01 {
opp-hz = /bits/ 64 <111000000>;
opp-microvolt = <950000>;
};
opp02 {
opp-hz = /bits/ 64 <222000000>;
opp-microvolt = <950000>;
};
opp03 {
opp-hz = /bits/ 64 <333000000>;
opp-microvolt = <950000>;
};
opp04 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <987500>;
};
};
bus_noc_opp_table: opp_table3 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <67000000>;
};
opp01 {
opp-hz = /bits/ 64 <75000000>;
};
opp02 {
opp-hz = /bits/ 64 <86000000>;
};
opp03 {
opp-hz = /bits/ 64 <100000000>;
};
};
bus_fsys_apb_opp_table: opp_table4 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <100000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
};
};
bus_fsys2_opp_table: opp_table5 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <75000000>;
};
opp01 {
opp-hz = /bits/ 64 <100000000>;
};
opp02 {
opp-hz = /bits/ 64 <150000000>;
};
};
bus_mfc_opp_table: opp_table6 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <96000000>;
};
opp01 {
opp-hz = /bits/ 64 <111000000>;
};
opp02 {
opp-hz = /bits/ 64 <167000000>;
};
opp03 {
opp-hz = /bits/ 64 <222000000>;
};
opp04 {
opp-hz = /bits/ 64 <333000000>;
};
};
bus_gen_opp_table: opp_table7 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <89000000>;
};
opp01 {
opp-hz = /bits/ 64 <133000000>;
};
opp02 {
opp-hz = /bits/ 64 <178000000>;
};
opp03 {
opp-hz = /bits/ 64 <267000000>;
};
};
bus_peri_opp_table: opp_table8 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <67000000>;
};
};
bus_g2d_opp_table: opp_table9 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <84000000>;
};
opp01 {
opp-hz = /bits/ 64 <167000000>;
};
opp02 {
opp-hz = /bits/ 64 <222000000>;
};
opp03 {
opp-hz = /bits/ 64 <300000000>;
};
opp04 {
opp-hz = /bits/ 64 <333000000>;
};
};
bus_g2d_acp_opp_table: opp_table10 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <67000000>;
};
opp01 {
opp-hz = /bits/ 64 <133000000>;
};
opp02 {
opp-hz = /bits/ 64 <178000000>;
};
opp03 {
opp-hz = /bits/ 64 <267000000>;
};
};
bus_jpeg_opp_table: opp_table11 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <75000000>;
};
opp01 {
opp-hz = /bits/ 64 <150000000>;
};
opp02 {
opp-hz = /bits/ 64 <200000000>;
};
opp03 {
opp-hz = /bits/ 64 <300000000>;
};
};
bus_jpeg_apb_opp_table: opp_table12 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <84000000>;
};
opp01 {
opp-hz = /bits/ 64 <111000000>;
};
opp02 {
opp-hz = /bits/ 64 <134000000>;
};
opp03 {
opp-hz = /bits/ 64 <167000000>;
};
};
bus_disp1_fimd_opp_table: opp_table13 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <120000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
};
};
bus_disp1_opp_table: opp_table14 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <120000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
};
opp02 {
opp-hz = /bits/ 64 <300000000>;
};
};
bus_gscl_opp_table: opp_table15 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <150000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
};
opp02 {
opp-hz = /bits/ 64 <300000000>;
};
};
bus_mscl_opp_table: opp_table16 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <84000000>;
};
opp01 {
opp-hz = /bits/ 64 <167000000>;
};
opp02 {
opp-hz = /bits/ 64 <222000000>;
};
opp03 {
opp-hz = /bits/ 64 <333000000>;
};
opp04 {
opp-hz = /bits/ 64 <400000000>;
};
};
};
thermal-zones {
......
arch/arm/boot/dts/exynos5422-cpus.dtsi
View file @ 90df0360
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG EXYNOS5422 SoC cpu device tree source
* Samsung Exynos5422 SoC cpu device tree source
*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
......
arch/arm/boot/dts/exynos5422-odroid-core.dtsi
View file @ 90df0360
......@@ -35,7 +35,264 @@ oscclk {
};
};
dmc_opp_table: opp_table2 {
bus_wcore_opp_table: opp_table2 {
compatible = "operating-points-v2";
/* derived from 532MHz MPLL */
opp00 {
opp-hz = /bits/ 64 <88700000>;
opp-microvolt = <925000 925000 1400000>;
};
opp01 {
opp-hz = /bits/ 64 <133000000>;
opp-microvolt = <950000 950000 1400000>;
};
opp02 {
opp-hz = /bits/ 64 <177400000>;
opp-microvolt = <950000 950000 1400000>;
};
opp03 {
opp-hz = /bits/ 64 <266000000>;
opp-microvolt = <950000 950000 1400000>;
};
opp04 {
opp-hz = /bits/ 64 <532000000>;
opp-microvolt = <1000000 1000000 1400000>;
};
};
bus_noc_opp_table: opp_table3 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
opp00 {
opp-hz = /bits/ 64 <66600000>;
};
opp01 {
opp-hz = /bits/ 64 <74000000>;
};
opp02 {
opp-hz = /bits/ 64 <83250000>;
};
opp03 {
opp-hz = /bits/ 64 <111000000>;
};
};
bus_fsys_apb_opp_table: opp_table4 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
opp00 {
opp-hz = /bits/ 64 <111000000>;
};
opp01 {
opp-hz = /bits/ 64 <222000000>;
};
};
bus_fsys2_opp_table: opp_table5 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
opp00 {
opp-hz = /bits/ 64 <75000000>;
};
opp01 {
opp-hz = /bits/ 64 <120000000>;
};
opp02 {
opp-hz = /bits/ 64 <200000000>;
};
};
bus_mfc_opp_table: opp_table6 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
opp00 {
opp-hz = /bits/ 64 <83250000>;
};
opp01 {
opp-hz = /bits/ 64 <111000000>;
};
opp02 {
opp-hz = /bits/ 64 <166500000>;
};
opp03 {
opp-hz = /bits/ 64 <222000000>;
};
opp04 {
opp-hz = /bits/ 64 <333000000>;
};
};
bus_gen_opp_table: opp_table7 {
compatible = "operating-points-v2";
/* derived from 532MHz MPLL */
opp00 {
opp-hz = /bits/ 64 <88700000>;
};
opp01 {
opp-hz = /bits/ 64 <133000000>;
};
opp02 {
opp-hz = /bits/ 64 <178000000>;
};
opp03 {
opp-hz = /bits/ 64 <266000000>;
};
};
bus_peri_opp_table: opp_table8 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
opp00 {
opp-hz = /bits/ 64 <66600000>;
};
};
bus_g2d_opp_table: opp_table9 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
opp00 {
opp-hz = /bits/ 64 <83250000>;
};
opp01 {
opp-hz = /bits/ 64 <111000000>;
};
opp02 {
opp-hz = /bits/ 64 <166500000>;
};
opp03 {
opp-hz = /bits/ 64 <222000000>;
};
opp04 {
opp-hz = /bits/ 64 <333000000>;
};
};
bus_g2d_acp_opp_table: opp_table10 {
compatible = "operating-points-v2";
/* derived from 532MHz MPLL */
opp00 {
opp-hz = /bits/ 64 <66500000>;
};
opp01 {
opp-hz = /bits/ 64 <133000000>;
};
opp02 {
opp-hz = /bits/ 64 <178000000>;
};
opp03 {
opp-hz = /bits/ 64 <266000000>;
};
};
bus_jpeg_opp_table: opp_table11 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
opp00 {
opp-hz = /bits/ 64 <75000000>;
};
opp01 {
opp-hz = /bits/ 64 <150000000>;
};
opp02 {
opp-hz = /bits/ 64 <200000000>;
};
opp03 {
opp-hz = /bits/ 64 <300000000>;
};
};
bus_jpeg_apb_opp_table: opp_table12 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
opp00 {
opp-hz = /bits/ 64 <83250000>;
};
opp01 {
opp-hz = /bits/ 64 <111000000>;
};
opp02 {
opp-hz = /bits/ 64 <133000000>;
};
opp03 {
opp-hz = /bits/ 64 <166500000>;
};
};
bus_disp1_fimd_opp_table: opp_table13 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
opp00 {
opp-hz = /bits/ 64 <120000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
};
};
bus_disp1_opp_table: opp_table14 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
opp00 {
opp-hz = /bits/ 64 <120000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
};
opp02 {
opp-hz = /bits/ 64 <300000000>;
};
};
bus_gscl_opp_table: opp_table15 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
opp00 {
opp-hz = /bits/ 64 <150000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
};
opp02 {
opp-hz = /bits/ 64 <300000000>;
};
};
bus_mscl_opp_table: opp_table16 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
opp00 {
opp-hz = /bits/ 64 <84000000>;
};
opp01 {
opp-hz = /bits/ 64 <167000000>;
};
opp02 {
opp-hz = /bits/ 64 <222000000>;
};
opp03 {
opp-hz = /bits/ 64 <333000000>;
};
opp04 {
opp-hz = /bits/ 64 <666000000>;
};
};
dmc_opp_table: opp_table17 {
compatible = "operating-points-v2";
opp00 {
......@@ -134,6 +391,7 @@ &adc {
};
&bus_wcore {
operating-points-v2 = <&bus_wcore_opp_table>;
devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
<&nocp_mem1_0>, <&nocp_mem1_1>;
vdd-supply = <&buck3_reg>;
......@@ -142,76 +400,91 @@ &bus_wcore {
};
&bus_noc {
operating-points-v2 = <&bus_noc_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_fsys_apb {
operating-points-v2 = <&bus_fsys_apb_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_fsys {
operating-points-v2 = <&bus_fsys2_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_fsys2 {
operating-points-v2 = <&bus_fsys2_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_mfc {
operating-points-v2 = <&bus_mfc_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_gen {
operating-points-v2 = <&bus_gen_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_peri {
operating-points-v2 = <&bus_peri_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_g2d {
operating-points-v2 = <&bus_g2d_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_g2d_acp {
operating-points-v2 = <&bus_g2d_acp_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_jpeg {
operating-points-v2 = <&bus_jpeg_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_jpeg_apb {
operating-points-v2 = <&bus_jpeg_apb_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_disp1_fimd {
operating-points-v2 = <&bus_disp1_fimd_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_disp1 {
operating-points-v2 = <&bus_disp1_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_gscl_scaler {
operating-points-v2 = <&bus_gscl_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_mscl {
operating-points-v2 = <&bus_mscl_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
......@@ -601,6 +874,8 @@ buck2_reg: BUCK2 {
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
regulator-coupled-with = <&buck3_reg>;
regulator-coupled-max-spread = <300000>;
regulator-state-mem {
regulator-off-in-suspend;
......@@ -613,6 +888,8 @@ buck3_reg: BUCK3 {
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
regulator-coupled-with = <&buck2_reg>;
regulator-coupled-max-spread = <300000>;
regulator-state-mem {
regulator-off-in-suspend;
......
arch/arm/boot/dts/exynos5422-odroidhc1.dts
View file @ 90df0360
......@@ -72,14 +72,14 @@ map0 {
*/
map1 {
trip = <&cpu0_alert1>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
......@@ -116,14 +116,14 @@ map0 {
};
map1 {
trip = <&cpu1_alert1>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
......@@ -160,14 +160,14 @@ map0 {
};
map1 {
trip = <&cpu2_alert1>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
......@@ -204,14 +204,14 @@ map0 {
};
map1 {
trip = <&cpu3_alert1>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
......
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
View file @ 90df0360
......@@ -107,7 +107,7 @@ map2 {
/*
* When reaching cpu0_alert3, reduce CPU
* by 2 steps. On Exynos5422/5800 that would
* be: 1600 MHz and 1100 MHz.
* (usually) be: 1800 MHz and 1200 MHz.
*/
map3 {
trip = <&cpu0_alert3>;
......@@ -122,19 +122,19 @@ map3 {
};
/*
* When reaching cpu0_alert4, reduce CPU
* further, down to 600 MHz (12 steps for big,
* 7 steps for LITTLE).
* further, down to 600 MHz (14 steps for big,
* 8 steps for LITTLE).
*/
map4 {
cpu0_cooling_map4: map4 {
trip = <&cpu0_alert4>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
......@@ -198,16 +198,16 @@ map3 {
<&cpu6 0 2>,
<&cpu7 0 2>;
};
map4 {
cpu1_cooling_map4: map4 {
trip = <&cpu1_alert4>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
......@@ -271,16 +271,16 @@ map3 {
<&cpu6 0 2>,
<&cpu7 0 2>;
};
map4 {
cpu2_cooling_map4: map4 {
trip = <&cpu2_alert4>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
......@@ -344,16 +344,16 @@ map3 {
<&cpu6 0 2>,
<&cpu7 0 2>;
};
map4 {
cpu3_cooling_map4: map4 {
trip = <&cpu3_alert4>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
......
arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
View file @ 90df0360
......@@ -30,6 +30,64 @@ &chipid {
samsung,asv-bin = <2>;
};
/*
* Odroid XU3-Lite board uses SoC revision with lower maximum frequencies
* than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores.
* Therefore we need to update OPPs tables and thermal maps accordingly.
*/
&cluster_a15_opp_table {
/delete-node/opp-2000000000;
/delete-node/opp-1900000000;
};
&cluster_a7_opp_table {
/delete-node/opp-1400000000;
};
&cpu0_cooling_map4 {
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
};
&cpu1_cooling_map4 {
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
};
&cpu2_cooling_map4 {
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
};
&cpu3_cooling_map4 {
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
};
&pwm {
/*
* PWM 0 -- fan
......
arch/arm/boot/dts/exynos5800-peach-pi.dts
View file @ 90df0360
......@@ -156,6 +156,15 @@ &clock_audss {
assigned-clock-parents = <&clock CLK_MAU_EPLL>;
};
/*
* Peach Pi board uses SoC revision with lower maximum frequency for A7 cores
* (1.3 GHz instead of 1.4 GHz) than Odroid XU3/XU4 boards. Thus we need to
* update A7 OPPs table accordingly.
*/
&cluster_a7_opp_table {
/delete-node/opp-1400000000;
};
&cpu0 {
cpu-supply = <&buck2_reg>;
};
......@@ -257,6 +266,8 @@ buck2_reg: BUCK2 {
regulator-always-on;
regulator-boot-on;
regulator-ramp-delay = <12500>;
regulator-coupled-with = <&buck3_reg>;
regulator-coupled-max-spread = <300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
......@@ -269,6 +280,8 @@ buck3_reg: BUCK3 {
regulator-always-on;
regulator-boot-on;
regulator-ramp-delay = <12500>;
regulator-coupled-with = <&buck2_reg>;
regulator-coupled-max-spread = <300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
......
arch/arm/boot/dts/exynos5800.dtsi
View file @ 90df0360
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG EXYNOS5800 SoC device tree source
* Samsung Exynos5800 SoC device tree source
*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* SAMSUNG EXYNOS5800 SoC device nodes are listed in this file.
* EXYNOS5800 based board files can include this file and provide
* Samsung Exynos5800 SoC device nodes are listed in this file.
* Exynos5800 based board files can include this file and provide
* values for board specfic bindings.
*/
......@@ -21,67 +21,87 @@ &clock {
};
&cluster_a15_opp_table {
opp-2000000000 {
opp-hz = /bits/ 64 <2000000000>;
opp-microvolt = <1312500>;
clock-latency-ns = <140000>;
};
opp-1900000000 {
opp-hz = /bits/ 64 <1900000000>;
opp-microvolt = <1262500>;
clock-latency-ns = <140000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1237500>;
clock-latency-ns = <140000>;
};
opp-1700000000 {
opp-microvolt = <1250000>;
opp-microvolt = <1250000 1250000 1500000>;
};
opp-1600000000 {
opp-microvolt = <1250000>;
opp-microvolt = <1250000 1250000 1500000>;
};
opp-1500000000 {
opp-microvolt = <1100000>;
opp-microvolt = <1100000 1100000 1500000>;
};
opp-1400000000 {
opp-microvolt = <1100000>;
opp-microvolt = <1100000 1100000 1500000>;
};
opp-1300000000 {
opp-microvolt = <1100000>;
opp-microvolt = <1100000 1100000 1500000>;
};
opp-1200000000 {
opp-microvolt = <1000000>;
opp-microvolt = <1000000 1000000 1500000>;
};
opp-1100000000 {
opp-microvolt = <1000000>;
opp-microvolt = <1000000 1000000 1500000>;
};
opp-1000000000 {
opp-microvolt = <1000000>;
opp-microvolt = <1000000 1000000 1500000>;
};
opp-900000000 {
opp-microvolt = <1000000>;
opp-microvolt = <1000000 1000000 1500000>;
};
opp-800000000 {
opp-microvolt = <900000>;
opp-microvolt = <900000 900000 1500000>;
};
opp-700000000 {
opp-microvolt = <900000>;
opp-microvolt = <900000 900000 1500000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <900000>;
opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <900000>;
opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <900000>;
opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <900000>;
opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <900000>;
opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
};
&cluster_a7_opp_table {
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-microvolt = <1275000>;
clock-latency-ns = <140000>;
};
opp-1300000000 {
opp-microvolt = <1250000>;
};
......
arch/arm/boot/dts/s3c2416-smdk2416.dts
View file @ 90df0360
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG SMDK2416 board device tree source
* Samsung SMDK2416 board device tree source
*
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
*/
......
arch/arm/boot/dts/s3c6410-smdk6410.dts
View file @ 90df0360
......@@ -4,7 +4,7 @@
*
* Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
*
* Device tree source file for SAMSUNG SMDK6410 board which is based on
* Device tree source file for Samsung SMDK6410 board which is based on
* Samsung's S3C6410 SoC.
*/
......@@ -16,7 +16,7 @@
#include "s3c6410.dtsi"
/ {
model = "SAMSUNG SMDK6410 board based on S3C6410";
model = "Samsung SMDK6410 board based on S3C6410";
compatible = "samsung,mini6410", "samsung,s3c6410";
memory@50000000 {
......
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