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Commit 93d3668c authored by Ido Schimmel's avatar Ido Schimmel Committed by David S. Miller
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mlxsw: spectrum_buffers: Use defines for pool indices 

The pool indices are currently hard coded throughout the code, which
makes the code hard to follow and extend.

Overcome this by using defines for the pool indices.
Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
Reviewed-by: default avatarPetr Machata <petrm@mellanox.com>
Acked-by: default avatarJiri Pirko <jiri@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 8f686206
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Showing with 104 additions and 78 deletions
drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c
View file @ 93d3668c
...@@ -49,6 +49,11 @@ struct mlxsw_sp_sb_pool_des { ...@@ -49,6 +49,11 @@ struct mlxsw_sp_sb_pool_des {
u8 pool; u8 pool;
}; };
#define MLXSW_SP_SB_POOL_ING 0
#define MLXSW_SP_SB_POOL_ING_MNG 3
#define MLXSW_SP_SB_POOL_EGR 4
#define MLXSW_SP_SB_POOL_EGR_MC 8
/* Order ingress pools before egress pools. */ /* Order ingress pools before egress pools. */
static const struct mlxsw_sp_sb_pool_des mlxsw_sp1_sb_pool_dess[] = { static const struct mlxsw_sp_sb_pool_des mlxsw_sp1_sb_pool_dess[] = {
{MLXSW_REG_SBXX_DIR_INGRESS, 0}, {MLXSW_REG_SBXX_DIR_INGRESS, 0},
...@@ -465,83 +470,104 @@ static int mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp, ...@@ -465,83 +470,104 @@ static int mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp,
.pool_index = _pool, \ .pool_index = _pool, \
} }
#define MLXSW_SP_SB_CM_ING(_min_buff, _max_buff) \
{ \
.min_buff = _min_buff, \
.max_buff = _max_buff, \
.pool_index = MLXSW_SP_SB_POOL_ING, \
}
#define MLXSW_SP_SB_CM_EGR(_min_buff, _max_buff) \
{ \
.min_buff = _min_buff, \
.max_buff = _max_buff, \
.pool_index = MLXSW_SP_SB_POOL_EGR, \
}
#define MLXSW_SP_SB_CM_EGR_MC(_min_buff, _max_buff) \
{ \
.min_buff = _min_buff, \
.max_buff = _max_buff, \
.pool_index = MLXSW_SP_SB_POOL_EGR_MC, \
}
static const struct mlxsw_sp_sb_cm mlxsw_sp1_sb_cms_ingress[] = { static const struct mlxsw_sp_sb_cm mlxsw_sp1_sb_cms_ingress[] = {
MLXSW_SP_SB_CM(10000, 8, 0), MLXSW_SP_SB_CM_ING(10000, 8),
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
MLXSW_SP_SB_CM(0, 0, 0), /* dummy, this PG does not exist */ MLXSW_SP_SB_CM_ING(0, 0), /* dummy, this PG does not exist */
MLXSW_SP_SB_CM(20000, 1, 3), MLXSW_SP_SB_CM(20000, 1, MLXSW_SP_SB_POOL_ING_MNG),
}; };
static const struct mlxsw_sp_sb_cm mlxsw_sp2_sb_cms_ingress[] = { static const struct mlxsw_sp_sb_cm mlxsw_sp2_sb_cms_ingress[] = {
MLXSW_SP_SB_CM(0, 7, 0), MLXSW_SP_SB_CM_ING(0, 7),
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0), MLXSW_SP_SB_CM_ING(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
MLXSW_SP_SB_CM(0, 0, 0), /* dummy, this PG does not exist */ MLXSW_SP_SB_CM_ING(0, 0), /* dummy, this PG does not exist */
MLXSW_SP_SB_CM(20000, 1, 3), MLXSW_SP_SB_CM(20000, 1, MLXSW_SP_SB_POOL_ING_MNG),
}; };
static const struct mlxsw_sp_sb_cm mlxsw_sp1_sb_cms_egress[] = { static const struct mlxsw_sp_sb_cm mlxsw_sp1_sb_cms_egress[] = {
MLXSW_SP_SB_CM(1500, 9, 4), MLXSW_SP_SB_CM_EGR(1500, 9),
MLXSW_SP_SB_CM(1500, 9, 4), MLXSW_SP_SB_CM_EGR(1500, 9),
MLXSW_SP_SB_CM(1500, 9, 4), MLXSW_SP_SB_CM_EGR(1500, 9),
MLXSW_SP_SB_CM(1500, 9, 4), MLXSW_SP_SB_CM_EGR(1500, 9),
MLXSW_SP_SB_CM(1500, 9, 4), MLXSW_SP_SB_CM_EGR(1500, 9),
MLXSW_SP_SB_CM(1500, 9, 4), MLXSW_SP_SB_CM_EGR(1500, 9),
MLXSW_SP_SB_CM(1500, 9, 4), MLXSW_SP_SB_CM_EGR(1500, 9),
MLXSW_SP_SB_CM(1500, 9, 4), MLXSW_SP_SB_CM_EGR(1500, 9),
MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
MLXSW_SP_SB_CM(1, 0xff, 4), MLXSW_SP_SB_CM_EGR(1, 0xff),
}; };
static const struct mlxsw_sp_sb_cm mlxsw_sp2_sb_cms_egress[] = { static const struct mlxsw_sp_sb_cm mlxsw_sp2_sb_cms_egress[] = {
MLXSW_SP_SB_CM(0, 7, 4), MLXSW_SP_SB_CM_EGR(0, 7),
MLXSW_SP_SB_CM(0, 7, 4), MLXSW_SP_SB_CM_EGR(0, 7),
MLXSW_SP_SB_CM(0, 7, 4), MLXSW_SP_SB_CM_EGR(0, 7),
MLXSW_SP_SB_CM(0, 7, 4), MLXSW_SP_SB_CM_EGR(0, 7),
MLXSW_SP_SB_CM(0, 7, 4), MLXSW_SP_SB_CM_EGR(0, 7),
MLXSW_SP_SB_CM(0, 7, 4), MLXSW_SP_SB_CM_EGR(0, 7),
MLXSW_SP_SB_CM(0, 7, 4), MLXSW_SP_SB_CM_EGR(0, 7),
MLXSW_SP_SB_CM(0, 7, 4), MLXSW_SP_SB_CM_EGR(0, 7),
MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
MLXSW_SP_SB_CM(0, MLXSW_SP_SB_INFI, 8), MLXSW_SP_SB_CM_EGR_MC(0, MLXSW_SP_SB_INFI),
MLXSW_SP_SB_CM(1, 0xff, 4), MLXSW_SP_SB_CM_EGR(1, 0xff),
}; };
#define MLXSW_SP_CPU_PORT_SB_CM MLXSW_SP_SB_CM(0, 0, 4) #define MLXSW_SP_CPU_PORT_SB_CM MLXSW_SP_SB_CM(0, 0, MLXSW_SP_SB_POOL_EGR)
static const struct mlxsw_sp_sb_cm mlxsw_sp_cpu_port_sb_cms[] = { static const struct mlxsw_sp_sb_cm mlxsw_sp_cpu_port_sb_cms[] = {
MLXSW_SP_CPU_PORT_SB_CM, MLXSW_SP_CPU_PORT_SB_CM,
MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, 4), MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, MLXSW_SP_SB_POOL_EGR),
MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, 4), MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, MLXSW_SP_SB_POOL_EGR),
MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, 4), MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, MLXSW_SP_SB_POOL_EGR),
MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, 4), MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, MLXSW_SP_SB_POOL_EGR),
MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, 4), MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, MLXSW_SP_SB_POOL_EGR),
MLXSW_SP_CPU_PORT_SB_CM, MLXSW_SP_CPU_PORT_SB_CM,
MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, 4), MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, MLXSW_SP_SB_POOL_EGR),
MLXSW_SP_CPU_PORT_SB_CM, MLXSW_SP_CPU_PORT_SB_CM,
MLXSW_SP_CPU_PORT_SB_CM, MLXSW_SP_CPU_PORT_SB_CM,
MLXSW_SP_CPU_PORT_SB_CM, MLXSW_SP_CPU_PORT_SB_CM,
...@@ -700,29 +726,29 @@ static int mlxsw_sp_port_sb_pms_init(struct mlxsw_sp_port *mlxsw_sp_port) ...@@ -700,29 +726,29 @@ static int mlxsw_sp_port_sb_pms_init(struct mlxsw_sp_port *mlxsw_sp_port)
return 0; return 0;
} }
#define MLXSW_SP_SB_MM(_min_buff, _max_buff, _pool) \ #define MLXSW_SP_SB_MM(_min_buff, _max_buff) \
{ \ { \
.min_buff = _min_buff, \ .min_buff = _min_buff, \
.max_buff = _max_buff, \ .max_buff = _max_buff, \
.pool_index = _pool, \ .pool_index = MLXSW_SP_SB_POOL_EGR, \
} }
static const struct mlxsw_sp_sb_mm mlxsw_sp_sb_mms[] = { static const struct mlxsw_sp_sb_mm mlxsw_sp_sb_mms[] = {
MLXSW_SP_SB_MM(0, 6, 4), MLXSW_SP_SB_MM(0, 6),
MLXSW_SP_SB_MM(0, 6, 4), MLXSW_SP_SB_MM(0, 6),
MLXSW_SP_SB_MM(0, 6, 4), MLXSW_SP_SB_MM(0, 6),
MLXSW_SP_SB_MM(0, 6, 4), MLXSW_SP_SB_MM(0, 6),
MLXSW_SP_SB_MM(0, 6, 4), MLXSW_SP_SB_MM(0, 6),
MLXSW_SP_SB_MM(0, 6, 4), MLXSW_SP_SB_MM(0, 6),
MLXSW_SP_SB_MM(0, 6, 4), MLXSW_SP_SB_MM(0, 6),
MLXSW_SP_SB_MM(0, 6, 4), MLXSW_SP_SB_MM(0, 6),
MLXSW_SP_SB_MM(0, 6, 4), MLXSW_SP_SB_MM(0, 6),
MLXSW_SP_SB_MM(0, 6, 4), MLXSW_SP_SB_MM(0, 6),
MLXSW_SP_SB_MM(0, 6, 4), MLXSW_SP_SB_MM(0, 6),
MLXSW_SP_SB_MM(0, 6, 4), MLXSW_SP_SB_MM(0, 6),
MLXSW_SP_SB_MM(0, 6, 4), MLXSW_SP_SB_MM(0, 6),
MLXSW_SP_SB_MM(0, 6, 4), MLXSW_SP_SB_MM(0, 6),
MLXSW_SP_SB_MM(0, 6, 4), MLXSW_SP_SB_MM(0, 6),
}; };
static int mlxsw_sp_sb_mms_init(struct mlxsw_sp *mlxsw_sp) static int mlxsw_sp_sb_mms_init(struct mlxsw_sp *mlxsw_sp)
......
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