Commit 93e537a1 authored by Daniel Vetter's avatar Daniel Vetter

drm/i915: split LVDS update code out of i9xx_crtc_mode_set

Just to make things clearer and reduce the size of this monstrosity.

v2: make sure 8xx PLL update function calls update_lvds too (Daniel)
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
danvet: fixed patch ordering to avoid breaking bisect.
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 23f54bea
...@@ -5134,6 +5134,62 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc, ...@@ -5134,6 +5134,62 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
} }
} }
static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
struct drm_display_mode *adjusted_mode)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_crtc->pipe;
u32 temp, lvds_sync = 0;
temp = I915_READ(LVDS);
temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
if (pipe == 1) {
temp |= LVDS_PIPEB_SELECT;
} else {
temp &= ~LVDS_PIPEB_SELECT;
}
/* set the corresponsding LVDS_BORDER bit */
temp |= dev_priv->lvds_border_bits;
/* Set the B0-B3 data pairs corresponding to whether we're going to
* set the DPLLs for dual-channel mode or not.
*/
if (clock->p2 == 7)
temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
else
temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
* appropriately here, but we need to look more thoroughly into how
* panels behave in the two modes.
*/
/* set the dithering flag on LVDS as needed */
if (INTEL_INFO(dev)->gen >= 4) {
if (dev_priv->lvds_dither)
temp |= LVDS_ENABLE_DITHER;
else
temp &= ~LVDS_ENABLE_DITHER;
}
if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
lvds_sync |= LVDS_HSYNC_POLARITY;
if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
lvds_sync |= LVDS_VSYNC_POLARITY;
if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
!= lvds_sync) {
char flags[2] = "-+";
DRM_INFO("Changing LVDS panel from "
"(%chsync, %cvsync) to (%chsync, %cvsync)\n",
flags[!(temp & LVDS_HSYNC_POLARITY)],
flags[!(temp & LVDS_VSYNC_POLARITY)],
flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
temp |= lvds_sync;
}
I915_WRITE(LVDS, temp);
}
static int i9xx_crtc_mode_set(struct drm_crtc *crtc, static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
struct drm_display_mode *mode, struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode, struct drm_display_mode *adjusted_mode,
...@@ -5155,7 +5211,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, ...@@ -5155,7 +5211,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
const intel_limit_t *limit; const intel_limit_t *limit;
int ret; int ret;
u32 temp; u32 temp;
u32 lvds_sync = 0;
list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
if (encoder->base.crtc != crtc) if (encoder->base.crtc != crtc)
...@@ -5341,53 +5396,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, ...@@ -5341,53 +5396,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
* This is an exception to the general rule that mode_set doesn't turn * This is an exception to the general rule that mode_set doesn't turn
* things on. * things on.
*/ */
if (is_lvds) { if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
temp = I915_READ(LVDS); intel_update_lvds(crtc, &clock, adjusted_mode);
temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
if (pipe == 1) {
temp |= LVDS_PIPEB_SELECT;
} else {
temp &= ~LVDS_PIPEB_SELECT;
}
/* set the corresponsding LVDS_BORDER bit */
temp |= dev_priv->lvds_border_bits;
/* Set the B0-B3 data pairs corresponding to whether we're going to
* set the DPLLs for dual-channel mode or not.
*/
if (clock.p2 == 7)
temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
else
temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
* appropriately here, but we need to look more thoroughly into how
* panels behave in the two modes.
*/
/* set the dithering flag on LVDS as needed */
if (INTEL_INFO(dev)->gen >= 4) {
if (dev_priv->lvds_dither)
temp |= LVDS_ENABLE_DITHER;
else
temp &= ~LVDS_ENABLE_DITHER;
}
if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
lvds_sync |= LVDS_HSYNC_POLARITY;
if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
lvds_sync |= LVDS_VSYNC_POLARITY;
if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
!= lvds_sync) {
char flags[2] = "-+";
DRM_INFO("Changing LVDS panel from "
"(%chsync, %cvsync) to (%chsync, %cvsync)\n",
flags[!(temp & LVDS_HSYNC_POLARITY)],
flags[!(temp & LVDS_VSYNC_POLARITY)],
flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
temp |= lvds_sync;
}
I915_WRITE(LVDS, temp);
}
if (is_dp) { if (is_dp) {
intel_dp_set_m_n(crtc, mode, adjusted_mode); intel_dp_set_m_n(crtc, mode, adjusted_mode);
......
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