Commit 957870f9 authored by Chris Wilson's avatar Chris Wilson

drm/i915: Split out i915_gem_object_set_tiling()

Expose an interface for changing the tiling and stride on an object,
that includes the complexity of checking for conflicting bindings and
fence registers.
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170110121045.27144-2-chris@chris-wilson.co.uk
parent 111dbcab
...@@ -337,6 +337,9 @@ i915_gem_object_get_tile_row_size(struct drm_i915_gem_object *obj) ...@@ -337,6 +337,9 @@ i915_gem_object_get_tile_row_size(struct drm_i915_gem_object *obj)
i915_gem_object_get_tile_height(obj)); i915_gem_object_get_tile_height(obj));
} }
int i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
unsigned int tiling, unsigned int stride);
static inline struct intel_engine_cs * static inline struct intel_engine_cs *
i915_gem_object_last_write_engine(struct drm_i915_gem_object *obj) i915_gem_object_last_write_engine(struct drm_i915_gem_object *obj)
{ {
......
...@@ -129,61 +129,56 @@ u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size, ...@@ -129,61 +129,56 @@ u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
/* Check pitch constriants for all chips & tiling formats */ /* Check pitch constriants for all chips & tiling formats */
static bool static bool
i915_tiling_ok(struct drm_i915_private *dev_priv, i915_tiling_ok(struct drm_i915_gem_object *obj,
int stride, int size, int tiling_mode) unsigned int tiling, unsigned int stride)
{ {
int tile_width; struct drm_i915_private *i915 = to_i915(obj->base.dev);
unsigned int tile_width;
/* Linear is always fine */ /* Linear is always fine */
if (tiling_mode == I915_TILING_NONE) if (tiling == I915_TILING_NONE)
return true; return true;
if (tiling_mode > I915_TILING_LAST) if (tiling > I915_TILING_LAST)
return false; return false;
if (IS_GEN2(dev_priv) ||
(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev_priv)))
tile_width = 128;
else
tile_width = 512;
/* check maximum stride & object size */ /* check maximum stride & object size */
/* i965+ stores the end address of the gtt mapping in the fence /* i965+ stores the end address of the gtt mapping in the fence
* reg, so dont bother to check the size */ * reg, so dont bother to check the size */
if (INTEL_GEN(dev_priv) >= 7) { if (INTEL_GEN(i915) >= 7) {
if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL) if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
return false; return false;
} else if (INTEL_GEN(dev_priv) >= 4) { } else if (INTEL_GEN(i915) >= 4) {
if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
return false; return false;
} else { } else {
if (stride > 8192) if (stride > 8192)
return false; return false;
if (IS_GEN3(dev_priv)) { if (IS_GEN3(i915)) {
if (size > I830_FENCE_MAX_SIZE_VAL << 20) if (obj->base.size > I830_FENCE_MAX_SIZE_VAL << 20)
return false; return false;
} else { } else {
if (size > I830_FENCE_MAX_SIZE_VAL << 19) if (obj->base.size > I830_FENCE_MAX_SIZE_VAL << 19)
return false; return false;
} }
} }
if (stride < tile_width) if (IS_GEN2(i915) ||
return false; (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)))
tile_width = 128;
else
tile_width = 512;
/* 965+ just needs multiples of tile width */
if (INTEL_GEN(dev_priv) >= 4) {
if (stride & (tile_width - 1)) if (stride & (tile_width - 1))
return false; return false;
/* 965+ just needs multiples of tile width */
if (INTEL_GEN(i915) >= 4)
return true; return true;
}
/* Pre-965 needs power of two tile widths */ /* Pre-965 needs power of two tile widths */
if (stride & (stride - 1)) return is_power_of_2(stride);
return false;
return true;
} }
static bool i915_vma_fence_prepare(struct i915_vma *vma, static bool i915_vma_fence_prepare(struct i915_vma *vma,
...@@ -232,79 +227,27 @@ i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj, ...@@ -232,79 +227,27 @@ i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj,
return 0; return 0;
} }
/**
* i915_gem_set_tiling_ioctl - IOCTL handler to set tiling mode
* @dev: DRM device
* @data: data pointer for the ioctl
* @file: DRM file for the ioctl call
*
* Sets the tiling mode of an object, returning the required swizzling of
* bit 6 of addresses in the object.
*
* Called by the user via ioctl.
*
* Returns:
* Zero on success, negative errno on failure.
*/
int int
i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data, i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
struct drm_file *file) unsigned int tiling, unsigned int stride)
{ {
struct drm_i915_gem_set_tiling *args = data; struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct drm_i915_private *dev_priv = to_i915(dev); struct i915_vma *vma;
struct drm_i915_gem_object *obj; int err;
int err = 0;
/* Make sure we don't cross-contaminate obj->tiling_and_stride */ /* Make sure we don't cross-contaminate obj->tiling_and_stride */
BUILD_BUG_ON(I915_TILING_LAST & STRIDE_MASK); BUILD_BUG_ON(I915_TILING_LAST & STRIDE_MASK);
obj = i915_gem_object_lookup(file, args->handle); GEM_BUG_ON(!i915_tiling_ok(obj, tiling, stride));
if (!obj) GEM_BUG_ON(!stride ^ (tiling == I915_TILING_NONE));
return -ENOENT; lockdep_assert_held(&i915->drm.struct_mutex);
if (!i915_tiling_ok(dev_priv,
args->stride, obj->base.size, args->tiling_mode)) {
i915_gem_object_put(obj);
return -EINVAL;
}
mutex_lock(&dev->struct_mutex);
if (obj->pin_display || obj->framebuffer_references) {
err = -EBUSY;
goto err;
}
if (args->tiling_mode == I915_TILING_NONE) {
args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
args->stride = 0;
} else {
if (args->tiling_mode == I915_TILING_X)
args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
else
args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
/* Hide bit 17 swizzling from the user. This prevents old Mesa if ((tiling | stride) == obj->tiling_and_stride)
* from aborting the application on sw fallbacks to bit 17, return 0;
* and we use the pread/pwrite bit17 paths to swizzle for it.
* If there was a user that was relying on the swizzle
* information for drm_intel_bo_map()ed reads/writes this would
* break it, but we don't have any of those.
*/
if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
/* If we can't handle the swizzling, make it untiled. */ if (obj->framebuffer_references)
if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) { return -EBUSY;
args->tiling_mode = I915_TILING_NONE;
args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
args->stride = 0;
}
}
if (args->tiling_mode != i915_gem_object_get_tiling(obj) ||
args->stride != i915_gem_object_get_stride(obj)) {
/* We need to rebind the object if its current allocation /* We need to rebind the object if its current allocation
* no longer meets the alignment restrictions for its new * no longer meets the alignment restrictions for its new
* tiling mode. Otherwise we can just leave it alone, but * tiling mode. Otherwise we can just leave it alone, but
...@@ -318,17 +261,19 @@ i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data, ...@@ -318,17 +261,19 @@ i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
* whilst executing a fenced command for an untiled object. * whilst executing a fenced command for an untiled object.
*/ */
err = i915_gem_object_fence_prepare(obj, err = i915_gem_object_fence_prepare(obj, tiling, stride);
args->tiling_mode, if (err)
args->stride); return err;
if (!err) {
struct i915_vma *vma;
/* If the memory has unknown (i.e. varying) swizzling, we pin the
* pages to prevent them being swapped out and causing corruption
* due to the change in swizzling.
*/
mutex_lock(&obj->mm.lock); mutex_lock(&obj->mm.lock);
if (obj->mm.pages && if (obj->mm.pages &&
obj->mm.madv == I915_MADV_WILLNEED && obj->mm.madv == I915_MADV_WILLNEED &&
dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
if (args->tiling_mode == I915_TILING_NONE) { if (tiling == I915_TILING_NONE) {
GEM_BUG_ON(!obj->mm.quirked); GEM_BUG_ON(!obj->mm.quirked);
__i915_gem_object_unpin_pages(obj); __i915_gem_object_unpin_pages(obj);
obj->mm.quirked = false; obj->mm.quirked = false;
...@@ -345,30 +290,24 @@ i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data, ...@@ -345,30 +290,24 @@ i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
if (!i915_vma_is_ggtt(vma)) if (!i915_vma_is_ggtt(vma))
break; break;
vma->fence_size = i915_gem_fence_size(dev_priv, vma->size, vma->fence_size =
args->tiling_mode, i915_gem_fence_size(i915, vma->size, tiling, stride);
args->stride); vma->fence_alignment =
vma->fence_alignment = i915_gem_fence_alignment(dev_priv, vma->size, i915_gem_fence_alignment(i915,
args->tiling_mode, vma->size, tiling, stride);
args->stride);
if (vma->fence) if (vma->fence)
vma->fence->dirty = true; vma->fence->dirty = true;
} }
obj->tiling_and_stride =
args->stride | args->tiling_mode; obj->tiling_and_stride = tiling | stride;
/* Force the fence to be reacquired for GTT access */ /* Force the fence to be reacquired for GTT access */
i915_gem_release_mmap(obj); i915_gem_release_mmap(obj);
}
}
/* we have to maintain this existing ABI... */
args->stride = i915_gem_object_get_stride(obj);
args->tiling_mode = i915_gem_object_get_tiling(obj);
/* Try to preallocate memory required to save swizzling on put-pages */ /* Try to preallocate memory required to save swizzling on put-pages */
if (i915_gem_object_needs_bit17_swizzle(obj)) { if (i915_gem_object_needs_bit17_swizzle(obj)) {
if (obj->bit_17 == NULL) { if (!obj->bit_17) {
obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT), obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
sizeof(long), GFP_KERNEL); sizeof(long), GFP_KERNEL);
} }
...@@ -377,10 +316,82 @@ i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data, ...@@ -377,10 +316,82 @@ i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
obj->bit_17 = NULL; obj->bit_17 = NULL;
} }
err: return 0;
i915_gem_object_put(obj); }
/**
* i915_gem_set_tiling_ioctl - IOCTL handler to set tiling mode
* @dev: DRM device
* @data: data pointer for the ioctl
* @file: DRM file for the ioctl call
*
* Sets the tiling mode of an object, returning the required swizzling of
* bit 6 of addresses in the object.
*
* Called by the user via ioctl.
*
* Returns:
* Zero on success, negative errno on failure.
*/
int
i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_gem_set_tiling *args = data;
struct drm_i915_gem_object *obj;
int err;
obj = i915_gem_object_lookup(file, args->handle);
if (!obj)
return -ENOENT;
if (!i915_tiling_ok(obj, args->tiling_mode, args->stride)) {
err = -EINVAL;
goto err;
}
if (args->tiling_mode == I915_TILING_NONE) {
args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
args->stride = 0;
} else {
if (args->tiling_mode == I915_TILING_X)
args->swizzle_mode = to_i915(dev)->mm.bit_6_swizzle_x;
else
args->swizzle_mode = to_i915(dev)->mm.bit_6_swizzle_y;
/* Hide bit 17 swizzling from the user. This prevents old Mesa
* from aborting the application on sw fallbacks to bit 17,
* and we use the pread/pwrite bit17 paths to swizzle for it.
* If there was a user that was relying on the swizzle
* information for drm_intel_bo_map()ed reads/writes this would
* break it, but we don't have any of those.
*/
if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
/* If we can't handle the swizzling, make it untiled. */
if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
args->tiling_mode = I915_TILING_NONE;
args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
args->stride = 0;
}
}
err = mutex_lock_interruptible(&dev->struct_mutex);
if (err)
goto err;
err = i915_gem_object_set_tiling(obj, args->tiling_mode, args->stride);
mutex_unlock(&dev->struct_mutex); mutex_unlock(&dev->struct_mutex);
/* We have to maintain this existing ABI... */
args->stride = i915_gem_object_get_stride(obj);
args->tiling_mode = i915_gem_object_get_tiling(obj);
err:
i915_gem_object_put(obj);
return err; return err;
} }
......
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