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Commit 960a0276 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'omap-for-v5.5/ti-sysc-drop-pdata-v2-signed-take2' of... 

Merge tag 'omap-for-v5.5/ti-sysc-drop-pdata-v2-signed-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt

Drop legacy platform data for omaps for v5.5

This series of changes continues dropping legacy platform data for
omaps. With the proper device tree configuration in place in the dts
files for ti-sysc interconnect target module driver, we can drop the
related platform data and legacy ti,hwmods custom property.

Most of the patches in this series drop platform data and custom dts
property one device class and one SoC at time. This way we can easily
revert one patch at a time in case of unexpected issues if the fix is
not trivial.

For am335x musb, we need to first update the device tree to probe with
ti-sysc interconnect target module driver. And then the following
patches drop the legacy platform data.

Note that this series depends on earlier ti-sysc related driver changes

* tag 'omap-for-v5.5/ti-sysc-drop-pdata-v2-signed-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (40 commits)
  ARM: OMAP2+: Drop legacy platform data for am335x musb
  ARM: dts: Drop pointless status changing for am3 musb
  ARM: dts: Probe am335x musb with ti-sysc
  ARM: OMAP2+: Drop legacy platform data for musb on omap4
  ARM: OMAP2+: Drop legacy platform data for omap4 mcasp
  ARM: OMAP2+: Drop legacy platform data for am3 and am4 mcasp
  ARM: OMAP2+: Drop legacy platform data for dra7 rng
  ARM: OMAP2+: Drop legacy platform data for am3 and am4 rng
  ARM: OMAP2+: Drop legacy platform data for omap4 hdq1w
  ARM: OMAP2+: Drop legacy platform data for dra7 hdq1w
  ARM: OMAP2+: Drop legacy platform data for am4 hdq1w
  ARM: OMAP2+: Drop legacy platform data for omap5 mcbsp
  ARM: OMAP2+: Drop legacy platform data for omap4 mcbsp
  ARM: OMAP2+: Drop legacy platform data for omap5 wdt
  ARM: OMAP2+: Drop legacy platform data for dra7 wdt
  ARM: OMAP2+: Drop legacy platform data for am3 and am4 wdt
  ARM: dts: Drop custom hwmod property for omap5 mmc
  ARM: dts: Drop custom hwmod property for am4 mmc
  ARM: dts: Drop custom hwmod property for am3 mmc
  ARM: dts: Drop custom hwmod property for omap5 i2c
  ...

Link: https://lore.kernel.org/r/pull-1571934890-285615@atomide.com-3Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents fcf371fd b08a0c57
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arch/arm/boot/dts/am335x-baltos.dtsi
View file @ 960a0276
......@@ -258,18 +258,6 @@ at24@50 {
};
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&cppi41dma {
status = "okay";
};
#include "tps65910.dtsi"
&tps {
......
arch/arm/boot/dts/am335x-bone-common.dtsi
View file @ 960a0276
......@@ -191,38 +191,16 @@ &uart0 {
status = "okay";
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "peripheral";
interrupts-extended = <&intc 18 &tps 0>;
interrupt-names = "mc", "vbus";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
......
arch/arm/boot/dts/am335x-boneblue.dts
View file @ 960a0276
......@@ -278,38 +278,16 @@ &uart5 {
status = "okay";
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "peripheral";
interrupts-extended = <&intc 18 &tps 0>;
interrupt-names = "mc", "vbus";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
&i2c0 {
baseboard_eeprom: baseboard_eeprom@50 {
compatible = "atmel,24c256";
......
arch/arm/boot/dts/am335x-chiliboard.dts
View file @ 960a0276
......@@ -153,30 +153,12 @@ &cpsw_emac0 {
};
/* USB */
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb1 {
pinctrl-names = "default";
pinctrl-0 = <&usb1_drvvbus>;
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
/* microSD */
&mmc1 {
pinctrl-names = "default";
......
arch/arm/boot/dts/am335x-cm-t335.dts
View file @ 960a0276
......@@ -330,26 +330,6 @@ tlv320aic23: codec@1a {
};
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&cppi41dma {
status = "okay";
};
&epwmss0 {
status = "okay";
......
arch/arm/boot/dts/am335x-evm.dts
View file @ 960a0276
......@@ -433,35 +433,10 @@ tps: tps@2d {
};
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
......
arch/arm/boot/dts/am335x-evmsk.dts
View file @ 960a0276
......@@ -523,35 +523,10 @@ tlv320aic3106: tlv320aic3106@1b {
};
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
&epwmss2 {
status = "okay";
......
arch/arm/boot/dts/am335x-guardian.dts
View file @ 960a0276
......@@ -115,10 +115,6 @@ vmmcsd_fixed: regulator-3v3 {
};
};
&cppi41dma {
status = "okay";
};
&elm {
status = "okay";
};
......@@ -328,30 +324,12 @@ &uart0 {
status = "okay";
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0 {
dr_mode = "peripheral";
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1 {
dr_mode = "host";
status = "okay";
};
&usb1_phy {
status = "okay";
};
&am33xx_pinmux {
......
arch/arm/boot/dts/am335x-igep0033.dtsi
View file @ 960a0276
......@@ -217,35 +217,10 @@ &uart0 {
pinctrl-0 = <&uart0_pins>;
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
#include "tps65910.dtsi"
&tps {
......
arch/arm/boot/dts/am335x-lxm.dts
View file @ 960a0276
......@@ -283,36 +283,14 @@ &uart0 {
status = "okay";
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
&cpsw_emac0 {
phy-handle = <&ethphy0>;
phy-mode = "rmii";
......
arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
View file @ 960a0276
......@@ -111,27 +111,10 @@ rtc_wdt: rtc_wdt@68 {
};
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
/* Power */
&vbat {
regulator-name = "vbat";
......
arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
View file @ 960a0276
......@@ -290,36 +290,14 @@ gpio_xten: gpio_xten@27 {
};
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
#include "tps65910.dtsi"
&tps {
......
arch/arm/boot/dts/am335x-osd3358-sm-red.dts
View file @ 960a0276
......@@ -384,38 +384,16 @@ &uart0 {
status = "okay";
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "peripheral";
interrupts-extended = <&intc 18 &tps 0>;
interrupt-names = "mc", "vbus";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
......
arch/arm/boot/dts/am335x-pcm-953.dtsi
View file @ 960a0276
......@@ -237,31 +237,6 @@ &uart3 {
};
/* USB */
&cppi41dma {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&usb1_phy {
status = "okay";
};
arch/arm/boot/dts/am335x-pdu001.dts
View file @ 960a0276
......@@ -384,34 +384,6 @@ display-controller@0 {
};
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};
&cppi41dma {
status = "okay";
};
/*
* Disable soc's rtc as we have no VBAT for it. This makes the board
* rtc (Microchip MCP79400) the default rtc device 'rtc0'.
......
arch/arm/boot/dts/am335x-pepper.dts
View file @ 960a0276
......@@ -552,38 +552,18 @@ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
/* USB */
&usb {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&usb_pins>;
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
&am33xx_pinmux {
usb_pins: pinmux_usb {
pinctrl-single,pins = <
......
arch/arm/boot/dts/am335x-pocketbeagle.dts
View file @ 960a0276
......@@ -206,32 +206,10 @@ &uart4 {
status = "okay";
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "otg";
};
&usb1_phy {
status = "okay";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
arch/arm/boot/dts/am335x-regor.dtsi
View file @ 960a0276
......@@ -200,24 +200,3 @@ &uart1 {
status = "okay";
linux,rs485-enabled-at-boot-time;
};
/* USB */
&cppi41dma {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb0_phy {
status = "okay";
};
arch/arm/boot/dts/am335x-shc.dts
View file @ 960a0276
......@@ -117,10 +117,6 @@ &aes {
status = "okay";
};
&cppi41dma {
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
......@@ -358,20 +354,7 @@ &uart4 {
status = "okay";
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
......
arch/arm/boot/dts/am335x-sl50.dts
View file @ 960a0276
......@@ -512,36 +512,14 @@ &rtc {
status = "disabled";
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "otg";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
&mmc1 {
status = "okay";
pinctrl-names = "default";
......
arch/arm/boot/dts/am335x-wega.dtsi
View file @ 960a0276
......@@ -191,32 +191,6 @@ &uart1 {
status = "okay";
};
/* USB */
&cppi41dma {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1 {
dr_mode = "host";
status = "okay";
};
&usb1_phy {
status = "okay";
};
arch/arm/boot/dts/am33xx-l4.dtsi
View file @ 960a0276
......@@ -129,7 +129,6 @@ target-module@5000 { /* 0x44e05000, ap 12 30.0 */
gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio1";
reg = <0x7000 0x4>,
<0x7010 0x4>,
<0x7114 0x4>;
......@@ -163,7 +162,6 @@ gpio0: gpio@0 {
target-module@9000 { /* 0x44e09000, ap 16 04.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart1";
reg = <0x9050 0x4>,
<0x9054 0x4>,
<0x9058 0x4>;
......@@ -195,7 +193,6 @@ uart0: serial@0 {
target-module@b000 { /* 0x44e0b000, ap 18 48.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c1";
reg = <0xb000 0x8>,
<0xb010 0x8>,
<0xb090 0x8>;
......@@ -306,6 +303,13 @@ scm_clocks: clocks {
};
};
usb_ctrl_mod: control@620 {
compatible = "ti,am335x-usb-ctrl-module";
reg = <0x620 0x10>,
<0x648 0x4>;
reg-names = "phy_ctrl", "wakeup";
};
wkup_m3_ipc: wkup_m3_ipc@1324 {
compatible = "ti,am3352-wkup-m3-ipc";
reg = <0x1324 0x24>;
......@@ -368,7 +372,6 @@ target-module@33000 { /* 0x44e33000, ap 27 18.0 */
target-module@35000 { /* 0x44e35000, ap 29 50.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "wd_timer2";
reg = <0x35000 0x4>,
<0x35010 0x4>,
<0x35014 0x4>;
......@@ -912,7 +915,6 @@ target-module@16000 { /* 0x48016000, ap 8 3c.0 */
target-module@22000 { /* 0x48022000, ap 10 12.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart2";
reg = <0x22050 0x4>,
<0x22054 0x4>,
<0x22058 0x4>;
......@@ -944,7 +946,6 @@ uart1: serial@0 {
target-module@24000 { /* 0x48024000, ap 12 14.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart3";
reg = <0x24050 0x4>,
<0x24054 0x4>,
<0x24058 0x4>;
......@@ -976,7 +977,6 @@ uart2: serial@0 {
target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c2";
reg = <0x2a000 0x8>,
<0x2a010 0x8>,
<0x2a090 0x8>;
......@@ -1046,7 +1046,6 @@ &edma 18 0
target-module@38000 { /* 0x48038000, ap 16 02.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
ti,hwmods = "mcasp0";
reg = <0x38000 0x4>,
<0x38004 0x4>;
reg-names = "rev", "sysc";
......@@ -1077,7 +1076,6 @@ mcasp0: mcasp@0 {
target-module@3c000 { /* 0x4803c000, ap 20 32.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
ti,hwmods = "mcasp1";
reg = <0x3c000 0x4>,
<0x3c004 0x4>;
reg-names = "rev", "sysc";
......@@ -1270,7 +1268,6 @@ timer7: timer@0 {
target-module@4c000 { /* 0x4804c000, ap 32 36.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio2";
reg = <0x4c000 0x4>,
<0x4c010 0x4>,
<0x4c114 0x4>;
......@@ -1312,7 +1309,6 @@ target-module@50000 { /* 0x48050000, ap 34 2c.0 */
target-module@60000 { /* 0x48060000, ap 36 0c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "mmc1";
reg = <0x602fc 0x4>,
<0x60110 0x4>,
<0x60114 0x4>;
......@@ -1385,7 +1381,6 @@ target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */
target-module@c8000 { /* 0x480c8000, ap 87 06.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mailbox";
reg = <0xc8000 0x4>,
<0xc8010 0x4>;
reg-names = "rev", "sysc";
......@@ -1506,7 +1501,6 @@ target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */
target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c3";
reg = <0x9c000 0x8>,
<0x9c010 0x8>,
<0x9c090 0x8>;
......@@ -1592,7 +1586,6 @@ target-module@a4000 { /* 0x481a4000, ap 83 30.0 */
target-module@a6000 { /* 0x481a6000, ap 48 16.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart4";
reg = <0xa6050 0x4>,
<0xa6054 0x4>,
<0xa6058 0x4>;
......@@ -1622,7 +1615,6 @@ uart3: serial@0 {
target-module@a8000 { /* 0x481a8000, ap 50 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart5";
reg = <0xa8050 0x4>,
<0xa8054 0x4>,
<0xa8058 0x4>;
......@@ -1652,7 +1644,6 @@ uart4: serial@0 {
target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart6";
reg = <0xaa050 0x4>,
<0xaa054 0x4>,
<0xaa058 0x4>;
......@@ -1682,7 +1673,6 @@ uart5: serial@0 {
target-module@ac000 { /* 0x481ac000, ap 54 38.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio3";
reg = <0xac000 0x4>,
<0xac010 0x4>,
<0xac114 0x4>;
......@@ -1716,7 +1706,6 @@ gpio2: gpio@0 {
target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio4";
reg = <0xae000 0x4>,
<0xae010 0x4>,
<0xae114 0x4>;
......@@ -1806,7 +1795,6 @@ dcan1: can@0 {
target-module@d8000 { /* 0x481d8000, ap 64 66.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "mmc2";
reg = <0xd82fc 0x4>,
<0xd8110 0x4>,
<0xd8114 0x4>;
......@@ -2061,7 +2049,6 @@ lcdc: lcdc@0 {
target-module@10000 { /* 0x48310000, ap 76 4e.1 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "rng";
reg = <0x11fe0 0x4>,
<0x11fe4 0x4>;
reg-names = "rev", "sysc";
......
arch/arm/boot/dts/am33xx.dtsi
View file @ 960a0276
......@@ -236,7 +236,6 @@ edma_tptc2: tptc@49a00000 {
target-module@47810000 {
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "mmc3";
reg = <0x478102fc 0x4>,
<0x47810110 0x4>,
<0x47810114 0x4>;
......@@ -263,37 +262,38 @@ mmc3: mmc@0 {
};
};
usb: usb@47400000 {
compatible = "ti,am33xx-usb";
reg = <0x47400000 0x1000>;
ranges;
usb: target-module@47400000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x47400000 0x4>,
<0x47400010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
SYSC_OMAP2_SOFTRESET)>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ti,hwmods = "usb_otg_hs";
status = "disabled";
usb_ctrl_mod: control@44e10620 {
compatible = "ti,am335x-usb-ctrl-module";
reg = <0x44e10620 0x10
0x44e10648 0x4>;
reg-names = "phy_ctrl", "wakeup";
status = "disabled";
};
ranges = <0x0 0x47400000 0x5000>;
usb0_phy: usb-phy@47401300 {
usb0_phy: usb-phy@1300 {
compatible = "ti,am335x-usb-phy";
reg = <0x47401300 0x100>;
reg = <0x1300 0x100>;
reg-names = "phy";
status = "disabled";
ti,ctrl_mod = <&usb_ctrl_mod>;
#phy-cells = <0>;
};
usb0: usb@47401000 {
usb0: usb@1400 {
compatible = "ti,musb-am33xx";
status = "disabled";
reg = <0x47401400 0x400
0x47401000 0x200>;
reg = <0x1400 0x400>,
<0x1000 0x200>;
reg-names = "mc", "control";
interrupts = <18>;
......@@ -329,20 +329,18 @@ &cppi41dma 11 1 &cppi41dma 12 1
"tx14", "tx15";
};
usb1_phy: usb-phy@47401b00 {
usb1_phy: usb-phy@1b00 {
compatible = "ti,am335x-usb-phy";
reg = <0x47401b00 0x100>;
reg = <0x1b00 0x100>;
reg-names = "phy";
status = "disabled";
ti,ctrl_mod = <&usb_ctrl_mod>;
#phy-cells = <0>;
};
usb1: usb@47401800 {
usb1: usb@1800 {
compatible = "ti,musb-am33xx";
status = "disabled";
reg = <0x47401c00 0x400
0x47401800 0x200>;
reg = <0x1c00 0x400>,
<0x1800 0x200>;
reg-names = "mc", "control";
interrupts = <19>;
interrupt-names = "mc";
......@@ -377,19 +375,18 @@ &cppi41dma 26 1 &cppi41dma 27 1
"tx14", "tx15";
};
cppi41dma: dma-controller@47402000 {
cppi41dma: dma-controller@2000 {
compatible = "ti,am3359-cppi41";
reg = <0x47400000 0x1000
0x47402000 0x1000
0x47403000 0x1000
0x47404000 0x4000>;
reg = <0x0000 0x1000>,
<0x2000 0x1000>,
<0x3000 0x1000>,
<0x4000 0x4000>;
reg-names = "glue", "controller", "scheduler", "queuemgr";
interrupts = <17>;
interrupt-names = "glue";
#dma-cells = <2>;
#dma-channels = <30>;
#dma-requests = <256>;
status = "disabled";
};
};
......
arch/arm/boot/dts/am4372.dtsi
View file @ 960a0276
......@@ -230,7 +230,6 @@ edma_tptc2: tptc@49a00000 {
target-module@47810000 {
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "mmc3";
reg = <0x478102fc 0x4>,
<0x47810110 0x4>,
<0x47810114 0x4>;
......
arch/arm/boot/dts/am437x-l4.dtsi
View file @ 960a0276
......@@ -132,7 +132,6 @@ target-module@5000 { /* 0x44e05000, ap 12 30.0 */
target-module@7000 { /* 0x44e07000, ap 14 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio1";
reg = <0x7000 0x4>,
<0x7010 0x4>,
<0x7114 0x4>;
......@@ -167,7 +166,6 @@ gpio0: gpio@0 {
target-module@9000 { /* 0x44e09000, ap 16 04.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart1";
reg = <0x9050 0x4>,
<0x9054 0x4>,
<0x9058 0x4>;
......@@ -195,7 +193,6 @@ uart0: serial@0 {
target-module@b000 { /* 0x44e0b000, ap 18 48.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c1";
reg = <0xb000 0x8>,
<0xb010 0x8>,
<0xb090 0x8>;
......@@ -373,7 +370,6 @@ target-module@33000 { /* 0x44e33000, ap 26 18.0 */
target-module@35000 { /* 0x44e35000, ap 28 50.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "wd_timer2";
reg = <0x35000 0x4>,
<0x35010 0x4>,
<0x35014 0x4>;
......@@ -679,7 +675,6 @@ target-module@8000 { /* 0x48008000, ap 6 10.0 */
target-module@22000 { /* 0x48022000, ap 8 0a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart2";
reg = <0x22050 0x4>,
<0x22054 0x4>,
<0x22058 0x4>;
......@@ -708,7 +703,6 @@ uart1: serial@0 {
target-module@24000 { /* 0x48024000, ap 10 1c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart3";
reg = <0x24050 0x4>,
<0x24054 0x4>,
<0x24058 0x4>;
......@@ -737,7 +731,6 @@ uart2: serial@0 {
target-module@2a000 { /* 0x4802a000, ap 12 22.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c2";
reg = <0x2a000 0x8>,
<0x2a010 0x8>,
<0x2a090 0x8>;
......@@ -817,7 +810,6 @@ target-module@36000 { /* 0x48036000, ap 84 3e.0 */
target-module@38000 { /* 0x48038000, ap 14 04.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
ti,hwmods = "mcasp0";
reg = <0x38000 0x4>,
<0x38004 0x4>;
reg-names = "rev", "sysc";
......@@ -849,7 +841,6 @@ mcasp0: mcasp@0 {
target-module@3c000 { /* 0x4803c000, ap 16 2a.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
ti,hwmods = "mcasp1";
reg = <0x3c000 0x4>,
<0x3c004 0x4>;
reg-names = "rev", "sysc";
......@@ -1048,7 +1039,6 @@ timer7: timer@0 {
target-module@4c000 { /* 0x4804c000, ap 28 36.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio2";
reg = <0x4c000 0x4>,
<0x4c010 0x4>,
<0x4c114 0x4>;
......@@ -1083,7 +1073,6 @@ gpio1: gpio@0 {
target-module@60000 { /* 0x48060000, ap 30 14.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "mmc1";
reg = <0x602fc 0x4>,
<0x60110 0x4>,
<0x60114 0x4>;
......@@ -1149,7 +1138,6 @@ elm: elm@0 {
target-module@c8000 { /* 0x480c8000, ap 73 06.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mailbox";
reg = <0xc8000 0x4>,
<0xc8010 0x4>;
reg-names = "rev", "sysc";
......@@ -1262,7 +1250,6 @@ target-module@8e000 { /* 0x4818e000, ap 36 02.0 */
target-module@9c000 { /* 0x4819c000, ap 38 52.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c3";
reg = <0x9c000 0x8>,
<0x9c010 0x8>,
<0x9c090 0x8>;
......@@ -1388,7 +1375,6 @@ spi3: spi@0 {
target-module@a6000 { /* 0x481a6000, ap 40 16.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart4";
reg = <0xa6050 0x4>,
<0xa6054 0x4>,
<0xa6058 0x4>;
......@@ -1417,7 +1403,6 @@ uart3: serial@0 {
target-module@a8000 { /* 0x481a8000, ap 42 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart5";
reg = <0xa8050 0x4>,
<0xa8054 0x4>,
<0xa8058 0x4>;
......@@ -1446,7 +1431,6 @@ uart4: serial@0 {
target-module@aa000 { /* 0x481aa000, ap 44 12.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart6";
reg = <0xaa050 0x4>,
<0xaa054 0x4>,
<0xaa058 0x4>;
......@@ -1475,7 +1459,6 @@ uart5: serial@0 {
target-module@ac000 { /* 0x481ac000, ap 46 30.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio3";
reg = <0xac000 0x4>,
<0xac010 0x4>,
<0xac114 0x4>;
......@@ -1510,7 +1493,6 @@ gpio2: gpio@0 {
target-module@ae000 { /* 0x481ae000, ap 48 32.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio4";
reg = <0xae000 0x4>,
<0xae010 0x4>,
<0xae114 0x4>;
......@@ -1614,7 +1596,6 @@ dcan1: can@0 {
target-module@d8000 { /* 0x481d8000, ap 54 5e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "mmc2";
reg = <0xd82fc 0x4>,
<0xd8110 0x4>,
<0xd8114 0x4>;
......@@ -1999,7 +1980,6 @@ ehrpwm5: pwm@200 {
target-module@10000 { /* 0x48310000, ap 64 4e.1 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "rng";
reg = <0x11fe0 0x4>,
<0x11fe4 0x4>;
reg-names = "rev", "sysc";
......@@ -2038,7 +2018,6 @@ target-module@18000 { /* 0x48318000, ap 62 4c.0 */
target-module@20000 { /* 0x48320000, ap 82 34.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio5";
reg = <0x20000 0x4>,
<0x20010 0x4>,
<0x20114 0x4>;
......@@ -2073,7 +2052,6 @@ gpio4: gpio@0 {
target-module@22000 { /* 0x48322000, ap 116 64.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio6";
reg = <0x22000 0x4>,
<0x22010 0x4>,
<0x22114 0x4>;
......@@ -2296,7 +2274,6 @@ spi4: spi@0 {
target-module@47000 { /* 0x48347000, ap 110 70.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "hdq1w";
reg = <0x47000 0x4>,
<0x47014 0x4>,
<0x47018 0x4>;
......
arch/arm/boot/dts/dra7-l4.dtsi
View file @ 960a0276
......@@ -442,7 +442,6 @@ target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */
target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mailbox1";
reg = <0xf4000 0x4>,
<0xf4010 0x4>;
reg-names = "rev", "sysc";
......@@ -1899,7 +1898,6 @@ timer11: timer@0 {
target-module@90000 { /* 0x48090000, ap 55 12.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "rng";
reg = <0x91fe0 0x4>,
<0x91fe4 0x4>;
reg-names = "rev", "sysc";
......@@ -2090,7 +2088,6 @@ mmc3: mmc@0 {
target-module@b2000 { /* 0x480b2000, ap 37 52.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "hdq1w";
reg = <0xb2000 0x4>,
<0xb2014 0x4>,
<0xb2018 0x4>;
......@@ -3199,7 +3196,6 @@ segment@0 { /* 0x48800000 */
target-module@2000 { /* 0x48802000, ap 95 7c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mailbox13";
reg = <0x2000 0x4>,
<0x2010 0x4>;
reg-names = "rev", "sysc";
......@@ -3528,7 +3524,6 @@ rtc: rtc@0 {
target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mailbox2";
reg = <0x3a000 0x4>,
<0x3a010 0x4>;
reg-names = "rev", "sysc";
......@@ -3559,7 +3554,6 @@ mailbox2: mailbox@0 {
target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mailbox3";
reg = <0x3c000 0x4>,
<0x3c010 0x4>;
reg-names = "rev", "sysc";
......@@ -3590,7 +3584,6 @@ mailbox3: mailbox@0 {
target-module@3e000 { /* 0x4883e000, ap 37 46.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mailbox4";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
......@@ -3621,7 +3614,6 @@ mailbox4: mailbox@0 {
target-module@40000 { /* 0x48840000, ap 39 64.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mailbox5";
reg = <0x40000 0x4>,
<0x40010 0x4>;
reg-names = "rev", "sysc";
......@@ -3652,7 +3644,6 @@ mailbox5: mailbox@0 {
target-module@42000 { /* 0x48842000, ap 41 4e.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mailbox6";
reg = <0x42000 0x4>,
<0x42010 0x4>;
reg-names = "rev", "sysc";
......@@ -3683,7 +3674,6 @@ mailbox6: mailbox@0 {
target-module@44000 { /* 0x48844000, ap 43 42.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mailbox7";
reg = <0x44000 0x4>,
<0x44010 0x4>;
reg-names = "rev", "sysc";
......@@ -3714,7 +3704,6 @@ mailbox7: mailbox@0 {
target-module@46000 { /* 0x48846000, ap 45 48.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mailbox8";
reg = <0x46000 0x4>,
<0x46010 0x4>;
reg-names = "rev", "sysc";
......@@ -3833,7 +3822,6 @@ target-module@5c000 { /* 0x4885c000, ap 31 32.0 */
target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mailbox9";
reg = <0x5e000 0x4>,
<0x5e010 0x4>;
reg-names = "rev", "sysc";
......@@ -3864,7 +3852,6 @@ mailbox9: mailbox@0 {
target-module@60000 { /* 0x48860000, ap 71 4a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mailbox10";
reg = <0x60000 0x4>,
<0x60010 0x4>;
reg-names = "rev", "sysc";
......@@ -3895,7 +3882,6 @@ mailbox10: mailbox@0 {
target-module@62000 { /* 0x48862000, ap 73 74.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mailbox11";
reg = <0x62000 0x4>,
<0x62010 0x4>;
reg-names = "rev", "sysc";
......@@ -3926,7 +3912,6 @@ mailbox11: mailbox@0 {
target-module@64000 { /* 0x48864000, ap 67 52.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mailbox12";
reg = <0x64000 0x4>,
<0x64010 0x4>;
reg-names = "rev", "sysc";
......@@ -4301,7 +4286,6 @@ gpio1: gpio@0 {
target-module@4000 { /* 0x4ae14000, ap 7 28.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "wd_timer2";
reg = <0x4000 0x4>,
<0x4010 0x4>,
<0x4014 0x4>;
......
arch/arm/boot/dts/omap4-l4-abe.dtsi
View file @ 960a0276
......@@ -86,7 +86,6 @@ segment@0 { /* 0x40100000 */
target-module@22000 { /* 0x40122000, ap 2 02.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "mcbsp1";
reg = <0x2208c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
......@@ -120,7 +119,6 @@ mcbsp1: mcbsp@0 {
target-module@24000 { /* 0x40124000, ap 4 04.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "mcbsp2";
reg = <0x2408c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
......@@ -154,7 +152,6 @@ mcbsp2: mcbsp@0 {
target-module@26000 { /* 0x40126000, ap 6 06.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "mcbsp3";
reg = <0x2608c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
......@@ -188,7 +185,6 @@ mcbsp3: mcbsp@0 {
target-module@28000 { /* 0x40128000, ap 8 08.0 */
compatible = "ti,sysc-mcasp", "ti,sysc";
ti,hwmods = "mcasp";
reg = <0x28000 0x4>,
<0x28004 0x4>;
reg-names = "rev", "sysc";
......
arch/arm/boot/dts/omap4-l4.dtsi
View file @ 960a0276
......@@ -381,7 +381,6 @@ target-module@29000 { /* 0x4a0a9000, ap 82 04.0 */
target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "usb_otg_hs";
reg = <0x2b400 0x4>,
<0x2b404 0x4>,
<0x2b408 0x4>;
......@@ -580,7 +579,6 @@ target-module@60000 { /* 0x4a0e0000, ap 19 1c.0 */
target-module@74000 { /* 0x4a0f4000, ap 27 24.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mailbox";
reg = <0x74000 0x4>,
<0x74010 0x4>;
reg-names = "rev", "sysc";
......@@ -1085,7 +1083,6 @@ segment@10000 { /* 0x4a310000 */
gpio1_target: target-module@0 { /* 0x4a310000, ap 5 14.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio1";
reg = <0x0 0x4>,
<0x10 0x4>,
<0x114 0x4>;
......@@ -1550,7 +1547,6 @@ target-module@40000 { /* 0x48040000, ap 13 0a.0 */
target-module@55000 { /* 0x48055000, ap 15 0c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio2";
reg = <0x55000 0x4>,
<0x55010 0x4>,
<0x55114 0x4>;
......@@ -1584,7 +1580,6 @@ gpio2: gpio@0 {
target-module@57000 { /* 0x48057000, ap 17 16.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio3";
reg = <0x57000 0x4>,
<0x57010 0x4>,
<0x57114 0x4>;
......@@ -1618,7 +1613,6 @@ gpio3: gpio@0 {
target-module@59000 { /* 0x48059000, ap 19 10.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio4";
reg = <0x59000 0x4>,
<0x59010 0x4>,
<0x59114 0x4>;
......@@ -1652,7 +1646,6 @@ gpio4: gpio@0 {
target-module@5b000 { /* 0x4805b000, ap 21 12.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio5";
reg = <0x5b000 0x4>,
<0x5b010 0x4>,
<0x5b114 0x4>;
......@@ -1686,7 +1679,6 @@ gpio5: gpio@0 {
target-module@5d000 { /* 0x4805d000, ap 23 14.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio6";
reg = <0x5d000 0x4>,
<0x5d010 0x4>,
<0x5d114 0x4>;
......@@ -2020,7 +2012,6 @@ target-module@90000 { /* 0x48090000, ap 57 2a.0 */
target-module@96000 { /* 0x48096000, ap 37 26.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "mcbsp4";
reg = <0x9608c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
......@@ -2052,7 +2043,6 @@ mcbsp4: mcbsp@0 {
target-module@98000 { /* 0x48098000, ap 49 22.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mcspi1";
reg = <0x98000 0x4>,
<0x98010 0x4>;
reg-names = "rev", "sysc";
......@@ -2091,7 +2081,6 @@ mcspi1: spi@0 {
target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mcspi2";
reg = <0x9a000 0x4>,
<0x9a010 0x4>;
reg-names = "rev", "sysc";
......@@ -2232,7 +2221,6 @@ target-module@b0000 { /* 0x480b0000, ap 47 40.0 */
target-module@b2000 { /* 0x480b2000, ap 65 3c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "hdq1w";
reg = <0xb2000 0x4>,
<0xb2014 0x4>,
<0xb2018 0x4>;
......@@ -2289,7 +2277,6 @@ mmc2: mmc@0 {
target-module@b8000 { /* 0x480b8000, ap 69 58.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mcspi3";
reg = <0xb8000 0x4>,
<0xb8010 0x4>;
reg-names = "rev", "sysc";
......@@ -2320,7 +2307,6 @@ mcspi3: spi@0 {
target-module@ba000 { /* 0x480ba000, ap 71 32.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mcspi4";
reg = <0xba000 0x4>,
<0xba010 0x4>;
reg-names = "rev", "sysc";
......
arch/arm/boot/dts/omap5-l4-abe.dtsi
View file @ 960a0276
......@@ -86,7 +86,6 @@ segment@0 { /* 0x40100000 */
target-module@22000 { /* 0x40122000, ap 2 02.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "mcbsp1";
reg = <0x2208c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
......@@ -120,7 +119,6 @@ mcbsp1: mcbsp@0 {
target-module@24000 { /* 0x40124000, ap 4 04.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "mcbsp2";
reg = <0x2408c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
......@@ -154,7 +152,6 @@ mcbsp2: mcbsp@0 {
target-module@26000 { /* 0x40126000, ap 6 06.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "mcbsp3";
reg = <0x2608c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
......
arch/arm/boot/dts/omap5-l4.dtsi
View file @ 960a0276
......@@ -593,7 +593,6 @@ target-module@60000 { /* 0x4a0e0000, ap 19 54.0 */
target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mailbox";
reg = <0x74000 0x4>,
<0x74010 0x4>;
reg-names = "rev", "sysc";
......@@ -1033,7 +1032,6 @@ segment@0 { /* 0x48000000 */
target-module@20000 { /* 0x48020000, ap 3 04.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart3";
reg = <0x20050 0x4>,
<0x20054 0x4>,
<0x20058 0x4>;
......@@ -1176,7 +1174,6 @@ timer9: timer@0 {
target-module@51000 { /* 0x48051000, ap 45 2e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio7";
reg = <0x51000 0x4>,
<0x51010 0x4>,
<0x51114 0x4>;
......@@ -1210,7 +1207,6 @@ gpio7: gpio@0 {
target-module@53000 { /* 0x48053000, ap 35 36.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio8";
reg = <0x53000 0x4>,
<0x53010 0x4>,
<0x53114 0x4>;
......@@ -1244,7 +1240,6 @@ gpio8: gpio@0 {
target-module@55000 { /* 0x48055000, ap 13 0e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio2";
reg = <0x55000 0x4>,
<0x55010 0x4>,
<0x55114 0x4>;
......@@ -1278,7 +1273,6 @@ gpio2: gpio@0 {
target-module@57000 { /* 0x48057000, ap 15 06.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio3";
reg = <0x57000 0x4>,
<0x57010 0x4>,
<0x57114 0x4>;
......@@ -1312,7 +1306,6 @@ gpio3: gpio@0 {
target-module@59000 { /* 0x48059000, ap 17 16.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio4";
reg = <0x59000 0x4>,
<0x59010 0x4>,
<0x59114 0x4>;
......@@ -1346,7 +1339,6 @@ gpio4: gpio@0 {
target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio5";
reg = <0x5b000 0x4>,
<0x5b010 0x4>,
<0x5b114 0x4>;
......@@ -1380,7 +1372,6 @@ gpio5: gpio@0 {
target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio6";
reg = <0x5d000 0x4>,
<0x5d010 0x4>,
<0x5d114 0x4>;
......@@ -1414,7 +1405,6 @@ gpio6: gpio@0 {
target-module@60000 { /* 0x48060000, ap 23 24.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c3";
reg = <0x60000 0x8>,
<0x60010 0x8>,
<0x60090 0x8>;
......@@ -1446,7 +1436,6 @@ i2c3: i2c@0 {
target-module@66000 { /* 0x48066000, ap 63 4c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart5";
reg = <0x66050 0x4>,
<0x66054 0x4>,
<0x66058 0x4>;
......@@ -1476,7 +1465,6 @@ uart5: serial@0 {
target-module@68000 { /* 0x48068000, ap 53 54.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart6";
reg = <0x68050 0x4>,
<0x68054 0x4>,
<0x68058 0x4>;
......@@ -1506,7 +1494,6 @@ uart6: serial@0 {
target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart1";
reg = <0x6a050 0x4>,
<0x6a054 0x4>,
<0x6a058 0x4>;
......@@ -1536,7 +1523,6 @@ uart1: serial@0 {
target-module@6c000 { /* 0x4806c000, ap 26 22.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart2";
reg = <0x6c050 0x4>,
<0x6c054 0x4>,
<0x6c058 0x4>;
......@@ -1566,7 +1552,6 @@ uart2: serial@0 {
target-module@6e000 { /* 0x4806e000, ap 28 44.1 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart4";
reg = <0x6e050 0x4>,
<0x6e054 0x4>,
<0x6e058 0x4>;
......@@ -1596,7 +1581,6 @@ uart4: serial@0 {
target-module@70000 { /* 0x48070000, ap 30 14.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c1";
reg = <0x70000 0x8>,
<0x70010 0x8>,
<0x70090 0x8>;
......@@ -1628,7 +1612,6 @@ i2c1: i2c@0 {
target-module@72000 { /* 0x48072000, ap 32 1c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c2";
reg = <0x72000 0x8>,
<0x72010 0x8>,
<0x72090 0x8>;
......@@ -1668,7 +1651,6 @@ target-module@78000 { /* 0x48078000, ap 39 12.0 */
target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c4";
reg = <0x7a000 0x8>,
<0x7a010 0x8>,
<0x7a090 0x8>;
......@@ -1700,7 +1682,6 @@ i2c4: i2c@0 {
target-module@7c000 { /* 0x4807c000, ap 83 34.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c5";
reg = <0x7c000 0x8>,
<0x7c010 0x8>,
<0x7c090 0x8>;
......@@ -1798,7 +1779,6 @@ target-module@90000 { /* 0x48090000, ap 55 1a.0 */
target-module@98000 { /* 0x48098000, ap 47 08.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mcspi1";
reg = <0x98000 0x4>,
<0x98010 0x4>;
reg-names = "rev", "sysc";
......@@ -1837,7 +1817,6 @@ mcspi1: spi@0 {
target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mcspi2";
reg = <0x9a000 0x4>,
<0x9a010 0x4>;
reg-names = "rev", "sysc";
......@@ -1871,7 +1850,6 @@ mcspi2: spi@0 {
target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mmc1";
reg = <0x9c000 0x4>,
<0x9c010 0x4>;
reg-names = "rev", "sysc";
......@@ -1931,7 +1909,6 @@ target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */
target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mmc3";
reg = <0xad000 0x4>,
<0xad010 0x4>;
reg-names = "rev", "sysc";
......@@ -1972,7 +1949,6 @@ target-module@b2000 { /* 0x480b2000, ap 37 0c.0 */
target-module@b4000 { /* 0x480b4000, ap 65 42.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mmc2";
reg = <0xb4000 0x4>,
<0xb4010 0x4>;
reg-names = "rev", "sysc";
......@@ -2005,7 +1981,6 @@ mmc2: mmc@0 {
target-module@b8000 { /* 0x480b8000, ap 67 32.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mcspi3";
reg = <0xb8000 0x4>,
<0xb8010 0x4>;
reg-names = "rev", "sysc";
......@@ -2036,7 +2011,6 @@ mcspi3: spi@0 {
target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mcspi4";
reg = <0xba000 0x4>,
<0xba010 0x4>;
reg-names = "rev", "sysc";
......@@ -2067,7 +2041,6 @@ mcspi4: spi@0 {
target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mmc4";
reg = <0xd1000 0x4>,
<0xd1010 0x4>;
reg-names = "rev", "sysc";
......@@ -2100,7 +2073,6 @@ mmc4: mmc@0 {
target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mmc5";
reg = <0xd5000 0x4>,
<0xd5010 0x4>;
reg-names = "rev", "sysc";
......@@ -2296,7 +2268,6 @@ segment@10000 { /* 0x4ae10000 */
target-module@0 { /* 0x4ae10000, ap 5 10.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio1";
reg = <0x0 0x4>,
<0x10 0x4>,
<0x114 0x4>;
......@@ -2331,7 +2302,6 @@ gpio1: gpio@0 {
target-module@4000 { /* 0x4ae14000, ap 7 14.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "wd_timer2";
reg = <0x4000 0x4>,
<0x4010 0x4>,
<0x4014 0x4>;
......
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
View file @ 960a0276
......@@ -35,10 +35,7 @@ extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2;
extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc;
extern struct omap_hwmod_ocp_if am33xx_l4_per__mailbox;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer2;
......@@ -54,7 +51,6 @@ extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc2;
extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc;
extern struct omap_hwmod_ocp_if am33xx_l3_main__sha0;
extern struct omap_hwmod_ocp_if am33xx_l3_main__aes0;
extern struct omap_hwmod_ocp_if am33xx_l4_per__rng;
extern struct omap_hwmod am33xx_l3_main_hwmod;
extern struct omap_hwmod am33xx_l3_s_hwmod;
......@@ -67,7 +63,6 @@ extern struct omap_hwmod am33xx_gfx_hwmod;
extern struct omap_hwmod am33xx_prcm_hwmod;
extern struct omap_hwmod am33xx_aes0_hwmod;
extern struct omap_hwmod am33xx_sha0_hwmod;
extern struct omap_hwmod am33xx_rng_hwmod;
extern struct omap_hwmod am33xx_ocmcram_hwmod;
extern struct omap_hwmod am33xx_smartreflex0_hwmod;
extern struct omap_hwmod am33xx_smartreflex1_hwmod;
......@@ -78,9 +73,6 @@ extern struct omap_hwmod am33xx_epwmss0_hwmod;
extern struct omap_hwmod am33xx_epwmss1_hwmod;
extern struct omap_hwmod am33xx_epwmss2_hwmod;
extern struct omap_hwmod am33xx_gpmc_hwmod;
extern struct omap_hwmod am33xx_mailbox_hwmod;
extern struct omap_hwmod am33xx_mcasp0_hwmod;
extern struct omap_hwmod am33xx_mcasp1_hwmod;
extern struct omap_hwmod am33xx_rtc_hwmod;
extern struct omap_hwmod am33xx_spi0_hwmod;
extern struct omap_hwmod am33xx_spi1_hwmod;
......@@ -96,7 +88,6 @@ extern struct omap_hwmod am33xx_tpcc_hwmod;
extern struct omap_hwmod am33xx_tptc0_hwmod;
extern struct omap_hwmod am33xx_tptc1_hwmod;
extern struct omap_hwmod am33xx_tptc2_hwmod;
extern struct omap_hwmod am33xx_wd_timer1_hwmod;
extern struct omap_hwmod_class am33xx_emif_hwmod_class;
extern struct omap_hwmod_class am33xx_l4_hwmod_class;
......
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
View file @ 960a0276
......@@ -158,14 +158,6 @@ struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
.user = OCP_USER_MPU,
};
/* l4 ls -> mailbox */
struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_mailbox_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU,
};
/* l4 ls -> spinlock */
struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
.master = &am33xx_l4_ls_hwmod,
......@@ -174,22 +166,6 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
.user = OCP_USER_MPU,
};
/* l4 ls -> mcasp0 */
struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_mcasp0_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU,
};
/* l4 ls -> mcasp1 */
struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_mcasp1_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU,
};
/* l4 ls -> mcspi0 */
struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
.master = &am33xx_l4_ls_hwmod,
......@@ -308,11 +284,3 @@ struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
.clk = "aes0_fck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 per -> rng */
struct omap_hwmod_ocp_if am33xx_l4_per__rng = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_rng_hwmod,
.clk = "rng_fck",
.user = OCP_USER_MPU,
};
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
View file @ 960a0276
......@@ -17,7 +17,6 @@
#include <linux/types.h>
#include "omap_hwmod.h"
#include "wd_timer.h"
#include "cm33xx.h"
#include "prm33xx.h"
#include "omap_hwmod_33xx_43xx_common_data.h"
......@@ -266,33 +265,6 @@ struct omap_hwmod am33xx_sha0_hwmod = {
},
};
/* rng */
static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
.rev_offs = 0x1fe0,
.sysc_offs = 0x1fe4,
.sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
.idlemodes = SIDLE_FORCE | SIDLE_NO,
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class am33xx_rng_hwmod_class = {
.name = "rng",
.sysc = &am33xx_rng_sysc,
};
struct omap_hwmod am33xx_rng_hwmod = {
.name = "rng",
.class = &am33xx_rng_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
.main_clk = "rng_fck",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* ocmcram */
static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
.name = "ocmcram",
......@@ -466,86 +438,6 @@ struct omap_hwmod am33xx_epwmss2_hwmod = {
},
};
/*
* 'gpio' class: for gpio 0,1,2,3
*/
static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0114,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
.name = "gpio",
.sysc = &am33xx_gpio_sysc,
};
/* gpio1 */
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio1_dbclk" },
};
static struct omap_hwmod am33xx_gpio1_hwmod = {
.name = "gpio2",
.class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = gpio1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
};
/* gpio2 */
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio2_dbclk" },
};
static struct omap_hwmod am33xx_gpio2_hwmod = {
.name = "gpio3",
.class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = gpio2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
};
/* gpio3 */
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio3_dbclk" },
};
static struct omap_hwmod am33xx_gpio3_hwmod = {
.name = "gpio4",
.class = &am33xx_gpio_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = gpio3_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
};
/* gpmc */
static struct omap_hwmod_class_sysconfig gpmc_sysc = {
.rev_offs = 0x0,
......@@ -576,78 +468,6 @@ struct omap_hwmod am33xx_gpmc_hwmod = {
},
};
/*
* 'mailbox' class
* mailbox module allowing communication between the on-chip processors using a
* queued mailbox-interrupt mechanism.
*/
static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
.name = "mailbox",
.sysc = &am33xx_mailbox_sysc,
};
struct omap_hwmod am33xx_mailbox_hwmod = {
.name = "mailbox",
.class = &am33xx_mailbox_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'mcasp' class
*/
static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x4,
.sysc_flags = SYSC_HAS_SIDLEMODE,
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type3,
};
static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
.name = "mcasp",
.sysc = &am33xx_mcasp_sysc,
};
/* mcasp0 */
struct omap_hwmod am33xx_mcasp0_hwmod = {
.name = "mcasp0",
.class = &am33xx_mcasp_hwmod_class,
.clkdm_name = "l3s_clkdm",
.main_clk = "mcasp0_fck",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* mcasp1 */
struct omap_hwmod am33xx_mcasp1_hwmod = {
.name = "mcasp1",
.class = &am33xx_mcasp_hwmod_class,
.clkdm_name = "l3s_clkdm",
.main_clk = "mcasp1_fck",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'rtc' class
......@@ -950,41 +770,6 @@ struct omap_hwmod am33xx_tptc2_hwmod = {
},
};
/* 'wd_timer' class */
static struct omap_hwmod_class_sysconfig wdt_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x10,
.syss_offs = 0x14,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
.name = "wd_timer",
.sysc = &wdt_sysc,
.pre_shutdown = &omap2_wd_timer_disable,
};
/*
* XXX: device.c file uses hardcoded name for watchdog timer
* driver "wd_timer2, so we are also using same name as of now...
*/
struct omap_hwmod am33xx_wd_timer1_hwmod = {
.name = "wd_timer2",
.class = &am33xx_wd_timer_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
.main_clk = "wdt1_fck",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static void omap_hwmod_am33xx_clkctrl(void)
{
CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
......@@ -993,12 +778,6 @@ static void omap_hwmod_am33xx_clkctrl(void)
CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
......@@ -1013,7 +792,6 @@ static void omap_hwmod_am33xx_clkctrl(void)
CLKCTRL(am33xx_smartreflex1_hwmod,
AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
......@@ -1031,7 +809,6 @@ static void omap_hwmod_am33xx_clkctrl(void)
CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_rng_hwmod, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET);
}
static void omap_hwmod_am33xx_rst(void)
......@@ -1055,12 +832,6 @@ static void omap_hwmod_am43xx_clkctrl(void)
CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
......@@ -1075,7 +846,6 @@ static void omap_hwmod_am43xx_clkctrl(void)
CLKCTRL(am33xx_smartreflex1_hwmod,
AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
......@@ -1092,7 +862,6 @@ static void omap_hwmod_am43xx_clkctrl(void)
CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_rng_hwmod, AM43XX_CM_PER_RNG_CLKCTRL_OFFSET);
}
static void omap_hwmod_am43xx_rst(void)
......
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
View file @ 960a0276
......@@ -21,7 +21,6 @@
#include "cm33xx.h"
#include "prm33xx.h"
#include "prm-regbits-33xx.h"
#include "wd_timer.h"
#include "omap_hwmod_33xx_43xx_common_data.h"
/*
......@@ -256,39 +255,6 @@ static struct omap_hwmod am33xx_lcdc_hwmod = {
},
};
/*
* 'usb_otg' class
* high-speed on-the-go universal serial bus (usb_otg) controller
*/
static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x10,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class am33xx_usbotg_class = {
.name = "usbotg",
.sysc = &am33xx_usbhsotg_sysc,
};
static struct omap_hwmod am33xx_usbss_hwmod = {
.name = "usb_otg_hs",
.class = &am33xx_usbotg_class,
.clkdm_name = "l3s_clkdm",
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "usbotg_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* Interfaces
*/
......@@ -388,24 +354,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
.user = OCP_USER_MPU,
};
/* l4 wkup -> wd_timer1 */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_wd_timer1_hwmod,
.clk = "dpll_core_m4_div2_ck",
.user = OCP_USER_MPU,
};
/* usbss */
/* l3 s -> USBSS interface */
static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
.master = &am33xx_l3_s_hwmod,
.slave = &am33xx_usbss_hwmod,
.clk = "l3s_gclk",
.user = OCP_USER_MPU,
.flags = OCPIF_SWSUP_IDLE,
};
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__emif,
&am33xx_mpu__l3_main,
......@@ -428,13 +376,9 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_wkup__timer1,
&am33xx_l4_wkup__rtc,
&am33xx_l4_wkup__adc_tsc,
&am33xx_l4_wkup__wd_timer1,
&am33xx_l4_hs__pruss,
&am33xx_l4_per__dcan0,
&am33xx_l4_per__dcan1,
&am33xx_l4_per__mailbox,
&am33xx_l4_ls__mcasp0,
&am33xx_l4_ls__mcasp1,
&am33xx_l4_ls__timer2,
&am33xx_l4_ls__timer3,
&am33xx_l4_ls__timer4,
......@@ -455,10 +399,8 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__tptc1,
&am33xx_l3_main__tptc2,
&am33xx_l3_main__ocmc,
&am33xx_l3_s__usbss,
&am33xx_l3_main__sha0,
&am33xx_l3_main__aes0,
&am33xx_l4_per__rng,
NULL,
};
......
arch/arm/mach-omap2/omap_hwmod_43xx_data.c
View file @ 960a0276
......@@ -18,8 +18,6 @@
#include "omap_hwmod_33xx_43xx_common_data.h"
#include "prcm43xx.h"
#include "omap_hwmod_common_data.h"
#include "hdq1w.h"
/* IP blocks */
static struct omap_hwmod am43xx_emif_hwmod = {
......@@ -468,32 +466,6 @@ static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
.parent_hwmod = &am43xx_dss_core_hwmod,
};
/* HDQ1W */
static struct omap_hwmod_class_sysconfig am43xx_hdq1w_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0014,
.syss_offs = 0x0018,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class am43xx_hdq1w_hwmod_class = {
.name = "hdq1w",
.sysc = &am43xx_hdq1w_sysc,
.reset = &omap_hdq1w_reset,
};
static struct omap_hwmod am43xx_hdq1w_hwmod = {
.name = "hdq1w",
.class = &am43xx_hdq1w_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = {
.rev_offs = 0x0,
......@@ -604,13 +576,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_wd_timer1_hwmod,
.clk = "sys_clkin_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am43xx_synctimer_hwmod,
......@@ -751,13 +716,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am43xx_hdq1w_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = {
.master = &am43xx_vpfe0_hwmod,
.slave = &am33xx_l3_main_hwmod,
......@@ -824,15 +782,10 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
&am43xx_l4_wkup__smartreflex0,
&am43xx_l4_wkup__smartreflex1,
&am43xx_l4_wkup__timer1,
&am43xx_l4_wkup__wd_timer1,
&am43xx_l4_wkup__adc_tsc,
&am43xx_l3_s__qspi,
&am33xx_l4_per__dcan0,
&am33xx_l4_per__dcan1,
&am33xx_l4_per__mailbox,
&am33xx_l4_per__rng,
&am33xx_l4_ls__mcasp0,
&am33xx_l4_ls__mcasp1,
&am33xx_l4_ls__timer2,
&am33xx_l4_ls__timer3,
&am33xx_l4_ls__timer4,
......@@ -863,7 +816,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
&am43xx_l4_ls__dss,
&am43xx_l4_ls__dss_dispc,
&am43xx_l4_ls__dss_rfbi,
&am43xx_l4_ls__hdq1w,
&am43xx_l3__vpfe0,
&am43xx_l3__vpfe1,
&am43xx_l4_ls__vpfe0,
......
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View file @ 960a0276
......@@ -1061,40 +1061,6 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
},
};
/*
* 'hdq1w' class
* hdq / 1-wire serial interface controller
*/
static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0014,
.syss_offs = 0x0018,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
SYSS_HAS_RESET_STATUS),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
.name = "hdq1w",
.sysc = &omap44xx_hdq1w_sysc,
};
/* hdq1w */
static struct omap_hwmod omap44xx_hdq1w_hwmod = {
.name = "hdq1w",
.class = &omap44xx_hdq1w_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
.main_clk = "func_12m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'hsi' class
......@@ -1288,180 +1254,6 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
},
};
/*
* 'mailbox' class
* mailbox module allowing communication between the on-chip processors using a
* queued mailbox-interrupt mechanism.
*/
static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
.name = "mailbox",
.sysc = &omap44xx_mailbox_sysc,
};
/* mailbox */
static struct omap_hwmod omap44xx_mailbox_hwmod = {
.name = "mailbox",
.class = &omap44xx_mailbox_hwmod_class,
.clkdm_name = "l4_cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
},
},
};
/*
* 'mcasp' class
* multi-channel audio serial port controller
*/
/* The IP is not compliant to type1 / type2 scheme */
static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
.rev_offs = 0,
.sysc_offs = 0x0004,
.sysc_flags = SYSC_HAS_SIDLEMODE,
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type_mcasp,
};
static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
.name = "mcasp",
.sysc = &omap44xx_mcasp_sysc,
};
/* mcasp */
static struct omap_hwmod omap44xx_mcasp_hwmod = {
.name = "mcasp",
.class = &omap44xx_mcasp_hwmod_class,
.clkdm_name = "abe_clkdm",
.main_clk = "func_mcasp_abe_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'mcbsp' class
* multi channel buffered serial port controller
*/
static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
.rev_offs = -ENODEV,
.sysc_offs = 0x008c,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
.name = "mcbsp",
.sysc = &omap44xx_mcbsp_sysc,
};
/* mcbsp1 */
static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
};
static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
.name = "mcbsp1",
.class = &omap44xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
.main_clk = "func_mcbsp1_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = mcbsp1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
};
/* mcbsp2 */
static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
};
static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
.name = "mcbsp2",
.class = &omap44xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
.main_clk = "func_mcbsp2_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = mcbsp2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
};
/* mcbsp3 */
static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
};
static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
.name = "mcbsp3",
.class = &omap44xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
.main_clk = "func_mcbsp3_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = mcbsp3_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
};
/* mcbsp4 */
static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
};
static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
.name = "mcbsp4",
.class = &omap44xx_mcbsp_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.main_clk = "per_mcbsp4_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = mcbsp4_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
};
/*
* 'mcpdm' class
......@@ -2294,51 +2086,6 @@ static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
};
/*
* 'usb_otg_hs' class
* high-speed on-the-go universal serial bus (usb_otg_hs) controller
*/
static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
.rev_offs = 0x0400,
.sysc_offs = 0x0404,
.syss_offs = 0x0408,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
.name = "usb_otg_hs",
.sysc = &omap44xx_usb_otg_hs_sysc,
};
/* usb_otg_hs */
static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
{ .role = "xclk", .clk = "usb_otg_hs_xclk" },
};
static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
.name = "usb_otg_hs",
.class = &omap44xx_usb_otg_hs_hwmod_class,
.clkdm_name = "l3_init_clkdm",
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "usb_otg_hs_ick",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
.opt_clks = usb_otg_hs_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
};
/*
* 'usb_tll_hs' class
* usb_tll_hs module is the adapter on the usb_host_hs ports
......@@ -2546,14 +2293,6 @@ static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* usb_otg_hs -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
.master = &omap44xx_usb_otg_hs_hwmod,
.slave = &omap44xx_l3_main_2_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> l3_main_3 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
.master = &omap44xx_l3_main_1_hwmod,
......@@ -2898,14 +2637,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> hdq1w */
static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_hdq1w_hwmod,
.clk = "l4_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> hsi */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
.master = &omap44xx_l4_cfg_hwmod,
......@@ -2954,62 +2685,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> mailbox */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_mailbox_hwmod,
.clk = "l4_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_abe -> mcasp */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcasp_hwmod,
.clk = "ocp_abe_iclk",
.user = OCP_USER_MPU,
};
/* l4_abe -> mcasp (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcasp_hwmod,
.clk = "ocp_abe_iclk",
.user = OCP_USER_SDMA,
};
/* l4_abe -> mcbsp1 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcbsp1_hwmod,
.clk = "ocp_abe_iclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_abe -> mcbsp2 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcbsp2_hwmod,
.clk = "ocp_abe_iclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_abe -> mcbsp3 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_mcbsp3_hwmod,
.clk = "ocp_abe_iclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> mcbsp4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
.master = &omap44xx_l4_per_hwmod,
.slave = &omap44xx_mcbsp4_hwmod,
.clk = "l4_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_abe -> mcpdm */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
.master = &omap44xx_l4_abe_hwmod,
......@@ -3242,14 +2917,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> usb_otg_hs */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_usb_otg_hs_hwmod,
.clk = "l4_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> usb_tll_hs */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
.master = &omap44xx_l4_cfg_hwmod,
......@@ -3296,7 +2963,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l4_cfg__l3_main_2,
/* &omap44xx_usb_host_fs__l3_main_2, */
&omap44xx_usb_host_hs__l3_main_2,
&omap44xx_usb_otg_hs__l3_main_2,
&omap44xx_l3_main_1__l3_main_3,
&omap44xx_l3_main_2__l3_main_3,
&omap44xx_l4_cfg__l3_main_3,
......@@ -3339,20 +3005,12 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l4_per__elm,
&omap44xx_l4_cfg__fdif,
&omap44xx_l3_main_2__gpmc,
&omap44xx_l4_per__hdq1w,
&omap44xx_l4_cfg__hsi,
&omap44xx_l3_main_2__ipu,
&omap44xx_l3_main_2__iss,
/* &omap44xx_iva__sl2if, */
&omap44xx_l3_main_2__iva,
&omap44xx_l4_wkup__kbd,
&omap44xx_l4_cfg__mailbox,
&omap44xx_l4_abe__mcasp,
&omap44xx_l4_abe__mcasp_dma,
&omap44xx_l4_abe__mcbsp1,
&omap44xx_l4_abe__mcbsp2,
&omap44xx_l4_abe__mcbsp3,
&omap44xx_l4_per__mcbsp4,
&omap44xx_l4_abe__mcpdm,
&omap44xx_l3_main_2__mmu_ipu,
&omap44xx_l4_cfg__mmu_dsp,
......@@ -3384,7 +3042,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l4_per__timer11,
/* &omap44xx_l4_cfg__usb_host_fs, */
&omap44xx_l4_cfg__usb_host_hs,
&omap44xx_l4_cfg__usb_otg_hs,
&omap44xx_l4_cfg__usb_tll_hs,
&omap44xx_mpu__emif1,
&omap44xx_mpu__emif2,
......
arch/arm/mach-omap2/omap_hwmod_54xx_data.c
View file @ 960a0276
......@@ -24,7 +24,6 @@
#include "cm1_54xx.h"
#include "cm2_54xx.h"
#include "prm54xx.h"
#include "wd_timer.h"
/* Base offset for all OMAP5 interrupts external to MPUSS */
#define OMAP54XX_IRQ_GIC_START 32
......@@ -628,124 +627,6 @@ static struct omap_hwmod omap54xx_kbd_hwmod = {
},
};
/*
* 'mailbox' class
* mailbox module allowing communication between the on-chip processors using a
* queued mailbox-interrupt mechanism.
*/
static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
.name = "mailbox",
.sysc = &omap54xx_mailbox_sysc,
};
/* mailbox */
static struct omap_hwmod omap54xx_mailbox_hwmod = {
.name = "mailbox",
.class = &omap54xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
},
},
};
/*
* 'mcbsp' class
* multi channel buffered serial port controller
*/
static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
.rev_offs = -ENODEV,
.sysc_offs = 0x008c,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
.name = "mcbsp",
.sysc = &omap54xx_mcbsp_sysc,
};
/* mcbsp1 */
static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
};
static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
.name = "mcbsp1",
.class = &omap54xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
.main_clk = "mcbsp1_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = mcbsp1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
};
/* mcbsp2 */
static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
};
static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
.name = "mcbsp2",
.class = &omap54xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
.main_clk = "mcbsp2_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = mcbsp2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
};
/* mcbsp3 */
static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
{ .role = "pad_fck", .clk = "pad_clks_ck" },
{ .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
};
static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
.name = "mcbsp3",
.class = &omap54xx_mcbsp_hwmod_class,
.clkdm_name = "abe_clkdm",
.main_clk = "mcbsp3_gfclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = mcbsp3_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
};
/*
* 'mcpdm' class
* multi channel pdm controller (proprietary interface with phoenix power
......@@ -795,86 +676,6 @@ static struct omap_hwmod omap54xx_mcpdm_hwmod = {
},
};
/*
* 'mcspi' class
* multichannel serial port interface (mcspi) / master/slave synchronous serial
* bus
*/
static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
.name = "mcspi",
.sysc = &omap54xx_mcspi_sysc,
};
/* mcspi1 */
static struct omap_hwmod omap54xx_mcspi1_hwmod = {
.name = "mcspi1",
.class = &omap54xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* mcspi2 */
static struct omap_hwmod omap54xx_mcspi2_hwmod = {
.name = "mcspi2",
.class = &omap54xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* mcspi3 */
static struct omap_hwmod omap54xx_mcspi3_hwmod = {
.name = "mcspi3",
.class = &omap54xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* mcspi4 */
static struct omap_hwmod omap54xx_mcspi4_hwmod = {
.name = "mcspi4",
.class = &omap54xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'mmu' class
......@@ -1392,43 +1193,6 @@ static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
.opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
};
/*
* 'wd_timer' class
* 32-bit watchdog upward counter that generates a pulse on the reset pin on
* overflow condition
*/
static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
.name = "wd_timer",
.sysc = &omap54xx_wd_timer_sysc,
.pre_shutdown = &omap2_wd_timer_disable,
};
/* wd_timer2 */
static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
.name = "wd_timer2",
.class = &omap54xx_wd_timer_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
.main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'ocp2scp' class
......@@ -1747,38 +1511,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> mailbox */
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
.master = &omap54xx_l4_cfg_hwmod,
.slave = &omap54xx_mailbox_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_abe -> mcbsp1 */
static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
.master = &omap54xx_l4_abe_hwmod,
.slave = &omap54xx_mcbsp1_hwmod,
.clk = "abe_iclk",
.user = OCP_USER_MPU,
};
/* l4_abe -> mcbsp2 */
static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
.master = &omap54xx_l4_abe_hwmod,
.slave = &omap54xx_mcbsp2_hwmod,
.clk = "abe_iclk",
.user = OCP_USER_MPU,
};
/* l4_abe -> mcbsp3 */
static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
.master = &omap54xx_l4_abe_hwmod,
.slave = &omap54xx_mcbsp3_hwmod,
.clk = "abe_iclk",
.user = OCP_USER_MPU,
};
/* l4_abe -> mcpdm */
static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
.master = &omap54xx_l4_abe_hwmod,
......@@ -1787,38 +1519,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
.user = OCP_USER_MPU,
};
/* l4_per -> mcspi1 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_mcspi1_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> mcspi2 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_mcspi2_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> mcspi3 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_mcspi3_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> mcspi4 */
static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
.master = &omap54xx_l4_per_hwmod,
.slave = &omap54xx_mcspi4_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> mpu */
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
.master = &omap54xx_l4_cfg_hwmod,
......@@ -1955,14 +1655,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
.master = &omap54xx_l4_wkup_hwmod,
.slave = &omap54xx_wd_timer2_hwmod,
.clk = "wkupaon_iclk_mux",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
&omap54xx_l3_main_1__dmm,
&omap54xx_l3_main_3__l3_instr,
......@@ -1994,15 +1686,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
&omap54xx_mpu__emif2,
&omap54xx_l3_main_2__mmu_ipu,
&omap54xx_l4_wkup__kbd,
&omap54xx_l4_cfg__mailbox,
&omap54xx_l4_abe__mcbsp1,
&omap54xx_l4_abe__mcbsp2,
&omap54xx_l4_abe__mcbsp3,
&omap54xx_l4_abe__mcpdm,
&omap54xx_l4_per__mcspi1,
&omap54xx_l4_per__mcspi2,
&omap54xx_l4_per__mcspi3,
&omap54xx_l4_per__mcspi4,
&omap54xx_l4_cfg__mpu,
&omap54xx_l4_cfg__spinlock,
&omap54xx_l4_cfg__ocp2scp1,
......@@ -2020,7 +1704,6 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
&omap54xx_l4_cfg__usb_host_hs,
&omap54xx_l4_cfg__usb_tll_hs,
&omap54xx_l4_cfg__usb_otg_ss,
&omap54xx_l4_wkup__wd_timer2,
&omap54xx_l4_cfg__ocp2scp3,
&omap54xx_l4_cfg__sata,
NULL,
......
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
View file @ 960a0276
......@@ -24,7 +24,6 @@
#include "cm1_7xx.h"
#include "cm2_7xx.h"
#include "prm7xx.h"
#include "wd_timer.h"
#include "soc.h"
/* Base offset for all DRA7XX interrupts external to MPUSS */
......@@ -772,229 +771,7 @@ static struct omap_hwmod dra7xx_gpmc_hwmod = {
},
};
/*
* 'hdq1w' class
*
*/
static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0014,
.syss_offs = 0x0018,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
SYSS_HAS_RESET_STATUS),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
.name = "hdq1w",
.sysc = &dra7xx_hdq1w_sysc,
};
/* hdq1w */
static struct omap_hwmod dra7xx_hdq1w_hwmod = {
.name = "hdq1w",
.class = &dra7xx_hdq1w_hwmod_class,
.clkdm_name = "l4per_clkdm",
.flags = HWMOD_INIT_NO_RESET,
.main_clk = "func_12m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'mailbox' class
*
*/
static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
.name = "mailbox",
.sysc = &dra7xx_mailbox_sysc,
};
/* mailbox1 */
static struct omap_hwmod dra7xx_mailbox1_hwmod = {
.name = "mailbox1",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
},
},
};
/* mailbox2 */
static struct omap_hwmod dra7xx_mailbox2_hwmod = {
.name = "mailbox2",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
},
},
};
/* mailbox3 */
static struct omap_hwmod dra7xx_mailbox3_hwmod = {
.name = "mailbox3",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
},
},
};
/* mailbox4 */
static struct omap_hwmod dra7xx_mailbox4_hwmod = {
.name = "mailbox4",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
},
},
};
/* mailbox5 */
static struct omap_hwmod dra7xx_mailbox5_hwmod = {
.name = "mailbox5",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
},
},
};
/* mailbox6 */
static struct omap_hwmod dra7xx_mailbox6_hwmod = {
.name = "mailbox6",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
},
},
};
/* mailbox7 */
static struct omap_hwmod dra7xx_mailbox7_hwmod = {
.name = "mailbox7",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
},
},
};
/* mailbox8 */
static struct omap_hwmod dra7xx_mailbox8_hwmod = {
.name = "mailbox8",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
},
},
};
/* mailbox9 */
static struct omap_hwmod dra7xx_mailbox9_hwmod = {
.name = "mailbox9",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
},
},
};
/* mailbox10 */
static struct omap_hwmod dra7xx_mailbox10_hwmod = {
.name = "mailbox10",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
},
},
};
/* mailbox11 */
static struct omap_hwmod dra7xx_mailbox11_hwmod = {
.name = "mailbox11",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
},
},
};
/* mailbox12 */
static struct omap_hwmod dra7xx_mailbox12_hwmod = {
.name = "mailbox12",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
},
},
};
/* mailbox13 */
static struct omap_hwmod dra7xx_mailbox13_hwmod = {
.name = "mailbox13",
.class = &dra7xx_mailbox_hwmod_class,
.clkdm_name = "l4cfg_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
},
},
};
/*
* 'mpu' class
......@@ -1655,34 +1432,6 @@ static struct omap_hwmod dra7xx_des_hwmod = {
},
};
/* rng */
static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
.rev_offs = 0x1fe0,
.sysc_offs = 0x1fe4,
.sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
.idlemodes = SIDLE_FORCE | SIDLE_NO,
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
.name = "rng",
.sysc = &dra7xx_rng_sysc,
};
static struct omap_hwmod dra7xx_rng_hwmod = {
.name = "rng",
.class = &dra7xx_rng_hwmod_class,
.flags = HWMOD_SWSUP_SIDLE,
.clkdm_name = "l4sec_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/*
* 'usb_otg_ss' class
*
......@@ -1815,43 +1564,6 @@ static struct omap_hwmod dra7xx_vcp2_hwmod = {
},
};
/*
* 'wd_timer' class
*
*/
static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
.name = "wd_timer",
.sysc = &dra7xx_wd_timer_sysc,
.pre_shutdown = &omap2_wd_timer_disable,
.reset = &omap2_wd_timer_reset,
};
/* wd_timer2 */
static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
.name = "wd_timer2",
.class = &dra7xx_wd_timer_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
.main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
......@@ -2090,118 +1802,6 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per1 -> hdq1w */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
.master = &dra7xx_l4_per1_hwmod,
.slave = &dra7xx_hdq1w_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> mailbox1 */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
.master = &dra7xx_l4_cfg_hwmod,
.slave = &dra7xx_mailbox1_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox2_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox3 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox3_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox4 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox4_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox5 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox5_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox6 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox6_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox7 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox7_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox8 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox8_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox9 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox9_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox10 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox10_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox11 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox11_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox12 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox12_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> mailbox13 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
.master = &dra7xx_l4_per3_hwmod,
.slave = &dra7xx_mailbox13_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> mpu */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
.master = &dra7xx_l4_cfg_hwmod,
......@@ -2442,13 +2042,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per1 -> rng */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
.master = &dra7xx_l4_per1_hwmod,
.slave = &dra7xx_rng_hwmod,
.user = OCP_USER_MPU,
};
/* l4_per3 -> usb_otg_ss1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
.master = &dra7xx_l4_per3_hwmod,
......@@ -2513,14 +2106,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
.master = &dra7xx_l4_wkup_hwmod,
.slave = &dra7xx_wd_timer2_hwmod,
.clk = "wkupaon_iclk_mux",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per2 -> epwmss0 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
.master = &dra7xx_l4_per2_hwmod,
......@@ -2575,20 +2160,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l3_main_1__sha0,
&dra7xx_l4_per1__elm,
&dra7xx_l3_main_1__gpmc,
&dra7xx_l4_per1__hdq1w,
&dra7xx_l4_cfg__mailbox1,
&dra7xx_l4_per3__mailbox2,
&dra7xx_l4_per3__mailbox3,
&dra7xx_l4_per3__mailbox4,
&dra7xx_l4_per3__mailbox5,
&dra7xx_l4_per3__mailbox6,
&dra7xx_l4_per3__mailbox7,
&dra7xx_l4_per3__mailbox8,
&dra7xx_l4_per3__mailbox9,
&dra7xx_l4_per3__mailbox10,
&dra7xx_l4_per3__mailbox11,
&dra7xx_l4_per3__mailbox12,
&dra7xx_l4_per3__mailbox13,
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,
......@@ -2624,7 +2195,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_per2__vcp1,
&dra7xx_l3_main_1__vcp2,
&dra7xx_l4_per2__vcp2,
&dra7xx_l4_wkup__wd_timer2,
&dra7xx_l4_per2__epwmss0,
&dra7xx_l4_per2__epwmss1,
&dra7xx_l4_per2__epwmss2,
......@@ -2634,7 +2204,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
/* GP-only hwmod links */
static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_wkup__timer12,
&dra7xx_l4_per1__rng,
NULL,
};
......
drivers/bus/ti-sysc.c
View file @ 960a0276
......@@ -74,6 +74,7 @@ static const char * const clock_names[SYSC_MAX_CLOCKS] = {
* @clk_disable_quirk: module specific clock disable quirk
* @reset_done_quirk: module specific reset done quirk
* @module_enable_quirk: module specific enable quirk
* @module_disable_quirk: module specific disable quirk
*/
struct sysc {
struct device *dev;
......@@ -100,6 +101,7 @@ struct sysc {
void (*clk_disable_quirk)(struct sysc *sysc);
void (*reset_done_quirk)(struct sysc *sysc);
void (*module_enable_quirk)(struct sysc *sysc);
void (*module_disable_quirk)(struct sysc *sysc);
};
static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
......@@ -915,6 +917,9 @@ static int sysc_enable_module(struct device *dev)
return -EINVAL;
}
if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
best_mode = SYSC_IDLE_NO;
reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
reg |= best_mode << regbits->midle_shift;
sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
......@@ -959,6 +964,9 @@ static int sysc_disable_module(struct device *dev)
if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
return 0;
if (ddata->module_disable_quirk)
ddata->module_disable_quirk(ddata);
regbits = ddata->cap->regbits;
reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
......@@ -973,6 +981,9 @@ static int sysc_disable_module(struct device *dev)
return ret;
}
if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
best_mode = SYSC_IDLE_FORCE;
reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
reg |= best_mode << regbits->midle_shift;
sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
......@@ -1032,8 +1043,6 @@ static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
struct ti_sysc_platform_data *pdata;
int error;
reset_control_deassert(ddata->rsts);
pdata = dev_get_platdata(ddata->dev);
if (!pdata)
return 0;
......@@ -1046,6 +1055,8 @@ static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
dev_err(dev, "%s: could not enable: %i\n",
__func__, error);
reset_control_deassert(ddata->rsts);
return 0;
}
......@@ -1099,8 +1110,6 @@ static int __maybe_unused sysc_runtime_resume(struct device *dev)
sysc_clkdm_deny_idle(ddata);
reset_control_deassert(ddata->rsts);
if (sysc_opt_clks_needed(ddata)) {
error = sysc_enable_opt_clocks(ddata);
if (error)
......@@ -1111,6 +1120,8 @@ static int __maybe_unused sysc_runtime_resume(struct device *dev)
if (error)
goto err_opt_clocks;
reset_control_deassert(ddata->rsts);
if (ddata->legacy_mode) {
error = sysc_runtime_resume_legacy(dev, ddata);
if (error)
......@@ -1246,8 +1257,15 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
SYSC_QUIRK("gpu", 0x50000000, 0x14, -1, -1, 0x00010201, 0xffffffff, 0),
SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff,
SYSC_MODULE_QUIRK_SGX),
SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -1, 0x4ea2080d, 0xffffffff,
SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
SYSC_MODULE_QUIRK_WDT),
/* Watchdog on am3 and am4 */
SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
#ifdef DEBUG
SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0),
......@@ -1301,8 +1319,6 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0),
SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0),
SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
0xffffffff, 0),
SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0),
#endif
};
......@@ -1440,14 +1456,14 @@ static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
!(val & 0x10), 100,
MAX_MODULE_SOFTRESET_WAIT);
if (error)
dev_warn(ddata->dev, "wdt disable spr failed\n");
dev_warn(ddata->dev, "wdt disable step1 failed\n");
sysc_write(ddata, wps, 0x5555);
sysc_write(ddata, spr, 0x5555);
error = readl_poll_timeout(ddata->module_va + wps, val,
!(val & 0x10), 100,
MAX_MODULE_SOFTRESET_WAIT);
if (error)
dev_warn(ddata->dev, "wdt disable wps failed\n");
dev_warn(ddata->dev, "wdt disable step2 failed\n");
}
static void sysc_init_module_quirks(struct sysc *ddata)
......@@ -1471,8 +1487,10 @@ static void sysc_init_module_quirks(struct sysc *ddata)
if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT)
if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
}
}
static int sysc_clockdomain_init(struct sysc *ddata)
......@@ -1522,37 +1540,6 @@ static int sysc_legacy_init(struct sysc *ddata)
return error;
}
/**
* sysc_rstctrl_reset_deassert - deassert rstctrl reset
* @ddata: device driver data
* @reset: reset before deassert
*
* A module can have both OCP softreset control and external rstctrl.
* If more complicated rstctrl resets are needed, please handle these
* directly from the child device driver and map only the module reset
* for the parent interconnect target module device.
*
* Automatic reset of the module on init can be skipped with the
* "ti,no-reset-on-init" device tree property.
*/
static int sysc_rstctrl_reset_deassert(struct sysc *ddata, bool reset)
{
int error;
if (!ddata->rsts)
return 0;
if (reset) {
error = reset_control_assert(ddata->rsts);
if (error)
return error;
}
reset_control_deassert(ddata->rsts);
return 0;
}
/*
* Note that the caller must ensure the interconnect target module is enabled
* before calling reset. Otherwise reset will not complete.
......@@ -1615,15 +1602,6 @@ static int sysc_reset(struct sysc *ddata)
static int sysc_init_module(struct sysc *ddata)
{
int error = 0;
bool manage_clocks = true;
error = sysc_rstctrl_reset_deassert(ddata, false);
if (error)
return error;
if (ddata->cfg.quirks &
(SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))
manage_clocks = false;
error = sysc_clockdomain_init(ddata);
if (error)
......@@ -1644,7 +1622,7 @@ static int sysc_init_module(struct sysc *ddata)
goto err_opt_clocks;
if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
error = sysc_rstctrl_reset_deassert(ddata, true);
error = reset_control_deassert(ddata->rsts);
if (error)
goto err_main_clocks;
}
......@@ -1656,28 +1634,32 @@ static int sysc_init_module(struct sysc *ddata)
if (ddata->legacy_mode) {
error = sysc_legacy_init(ddata);
if (error)
goto err_main_clocks;
goto err_reset;
}
if (!ddata->legacy_mode) {
error = sysc_enable_module(ddata->dev);
if (error)
goto err_main_clocks;
goto err_reset;
}
error = sysc_reset(ddata);
if (error)
dev_err(ddata->dev, "Reset failed with %d\n", error);
if (!ddata->legacy_mode && manage_clocks)
if (error && !ddata->legacy_mode)
sysc_disable_module(ddata->dev);
err_reset:
if (error && !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
reset_control_assert(ddata->rsts);
err_main_clocks:
if (manage_clocks)
if (error)
sysc_disable_main_clocks(ddata);
err_opt_clocks:
/* No re-enable of clockdomain autoidle to prevent module autoidle */
if (manage_clocks) {
if (error) {
sysc_disable_opt_clocks(ddata);
sysc_clkdm_allow_idle(ddata);
}
......@@ -2450,10 +2432,17 @@ static int sysc_probe(struct platform_device *pdev)
goto unprepare;
}
/* Balance reset counts */
if (ddata->rsts)
/* Balance use counts as PM runtime should have enabled these all */
if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
reset_control_assert(ddata->rsts);
if (!(ddata->cfg.quirks &
(SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) {
sysc_disable_main_clocks(ddata);
sysc_disable_opt_clocks(ddata);
sysc_clkdm_allow_idle(ddata);
}
sysc_show_registers(ddata);
ddata->dev->type = &sysc_device_type;
......
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