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Commit 98c4217c authored by Kai Germaschewski's avatar Kai Germaschewski
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ISDN: Add support for Eicon Diva 2.02 

(by Joerg Petersohn/Karsten Keil)
parent 91239976
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Showing with 1311 additions and 16 deletions
Documentation/isdn/README.HiSax
View file @ 98c4217c
......@@ -41,9 +41,10 @@ ELSA Quickstep 3000 (same settings as QS1000)
ELSA Quickstep 3000PCI
ELSA PCMCIA
ITK ix1-micro Rev.2
Eicon.Diehl Diva 2.0 ISA and PCI (S0 and U interface, no PRO version)
Eicon.Diehl Diva 2.01 ISA and PCI
Eicon.Diehl Diva Piccola
Eicon Diva 2.0 ISA and PCI (S0 and U interface, no PRO version)
Eicon Diva 2.01 ISA and PCI
Eicon Diva 2.02 PCI
Eicon Diva Piccola
ASUSCOM NETWORK INC. ISDNLink 128K PC adapter (order code I-IN100-ST-D)
Dynalink IS64PH (OEM version of ASUSCOM NETWORK INC. ISDNLink 128K adapter)
PCBIT-DP (OEM version of ASUSCOM NETWORK INC. ISDNLink)
......
drivers/isdn/hisax/Makefile
View file @ 98c4217c
......@@ -39,7 +39,7 @@ hisax-objs-$(CONFIG_HISAX_AVM_A1_PCMCIA) += avm_a1p.o isac.o arcofi.o hscx.o
hisax-objs-$(CONFIG_HISAX_FRITZPCI) += avm_pci.o isac.o arcofi.o
hisax-objs-$(CONFIG_HISAX_ELSA) += elsa.o isac.o arcofi.o hscx.o
hisax-objs-$(CONFIG_HISAX_IX1MICROR2) += ix1_micro.o isac.o arcofi.o hscx.o
hisax-objs-$(CONFIG_HISAX_DIEHLDIVA) += diva.o isac.o arcofi.o hscx.o
hisax-objs-$(CONFIG_HISAX_DIEHLDIVA) += diva.o isac.o arcofi.o hscx.o ipacx.o
hisax-objs-$(CONFIG_HISAX_ASUSCOM) += asuscom.o isac.o arcofi.o hscx.o
hisax-objs-$(CONFIG_HISAX_TELEINT) += teleint.o isac.o arcofi.o hfc_2bs0.o
hisax-objs-$(CONFIG_HISAX_SEDLBAUER) += sedlbauer.o isac.o arcofi.o hscx.o isar.o
......
drivers/isdn/hisax/config.c
View file @ 98c4217c
......@@ -2094,6 +2094,7 @@ static struct pci_device_id hisax_pci_tbl[] __initdata = {
{PCI_VENDOR_ID_EICON, PCI_DEVICE_ID_EICON_DIVA20, PCI_ANY_ID, PCI_ANY_ID},
{PCI_VENDOR_ID_EICON, PCI_DEVICE_ID_EICON_DIVA20_U, PCI_ANY_ID, PCI_ANY_ID},
{PCI_VENDOR_ID_EICON, PCI_DEVICE_ID_EICON_DIVA201, PCI_ANY_ID, PCI_ANY_ID},
{PCI_VENDOR_ID_EICON, PCI_DEVICE_ID_EICON_DIVA202, PCI_ANY_ID, PCI_ANY_ID},
#endif
#ifdef CONFIG_HISAX_ELSA
{PCI_VENDOR_ID_ELSA, PCI_DEVICE_ID_ELSA_MICROLINK, PCI_ANY_ID, PCI_ANY_ID},
......
drivers/isdn/hisax/diva.c
View file @ 98c4217c
......@@ -22,6 +22,7 @@
#include "isac.h"
#include "hscx.h"
#include "ipac.h"
#include "ipacx.h"
#include "isdnl1.h"
#include <linux/pci.h>
......@@ -49,6 +50,7 @@ const char *Diva_revision = "$Revision: 1.25.6.5 $";
#define DIVA_PCI 2
#define DIVA_IPAC_ISA 3
#define DIVA_IPAC_PCI 4
#define DIVA_IPACX_PCI 5
/* CTRL (Read) */
#define DIVA_IRQ_STAT 0x01
......@@ -68,10 +70,12 @@ const char *Diva_revision = "$Revision: 1.25.6.5 $";
#define PITA_MISC_REG 0x1c
#ifdef __BIG_ENDIAN
#define PITA_PARA_SOFTRESET 0x00000001
#define PITA_SER_SOFTRESET 0x00000002
#define PITA_PARA_MPX_MODE 0x00000004
#define PITA_INT0_ENABLE 0x00000200
#else
#define PITA_PARA_SOFTRESET 0x01000000
#define PITA_SER_SOFTRESET 0x02000000
#define PITA_PARA_MPX_MODE 0x04000000
#define PITA_INT0_ENABLE 0x00020000
#endif
......@@ -239,6 +243,47 @@ MemWriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
memwritereg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0), value);
}
/* IO-Functions for IPACX type cards */
static u_char
MemReadISAC_IPACX(struct IsdnCardState *cs, u_char offset)
{
return (memreadreg(cs->hw.diva.cfg_reg, offset));
}
static void
MemWriteISAC_IPACX(struct IsdnCardState *cs, u_char offset, u_char value)
{
memwritereg(cs->hw.diva.cfg_reg, offset, value);
}
static void
MemReadISACfifo_IPACX(struct IsdnCardState *cs, u_char * data, int size)
{
while(size--)
*data++ = memreadreg(cs->hw.diva.cfg_reg, 0);
}
static void
MemWriteISACfifo_IPACX(struct IsdnCardState *cs, u_char * data, int size)
{
while(size--)
memwritereg(cs->hw.diva.cfg_reg, 0, *data++);
}
static u_char
MemReadHSCX_IPACX(struct IsdnCardState *cs, int hscx, u_char offset)
{
return(memreadreg(cs->hw.diva.cfg_reg, offset +
(hscx ? IPACX_OFF_B2 : IPACX_OFF_B1)));
}
static void
MemWriteHSCX_IPACX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
{
memwritereg(cs->hw.diva.cfg_reg, offset +
(hscx ? IPACX_OFF_B2 : IPACX_OFF_B1), value);
}
/*
* fast interrupt HSCX stuff goes here
*/
......@@ -549,7 +594,7 @@ Memhscx_int_main(struct IsdnCardState *cs, u_char val)
u_char exval;
struct BCState *bcs;
if (val & 0x01) {
if (val & 0x01) { // EXB
bcs = cs->bcs + 1;
exval = MemReadHSCX(cs, 1, HSCX_EXIR);
if (exval & 0x40) {
......@@ -576,7 +621,7 @@ Memhscx_int_main(struct IsdnCardState *cs, u_char val)
debugl1(cs, "HSCX B interrupt %x", val);
Memhscx_interrupt(cs, val, 1);
}
if (val & 0x02) {
if (val & 0x02) { // EXA
bcs = cs->bcs;
exval = MemReadHSCX(cs, 0, HSCX_EXIR);
if (exval & 0x40) {
......@@ -598,7 +643,7 @@ Memhscx_int_main(struct IsdnCardState *cs, u_char val)
} else if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "HSCX A EXIR %x", exval);
}
if (val & 0x04) {
if (val & 0x04) { // ICA
exval = MemReadHSCX(cs, 0, HSCX_ISTA);
if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "HSCX A interrupt %x", exval);
......@@ -659,12 +704,31 @@ diva_irq_ipac_pci(int intno, void *dev_id, struct pt_regs *regs)
memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xC0);
}
static void
diva_irq_ipacx_pci(int intno, void *dev_id, struct pt_regs *regs)
{
struct IsdnCardState *cs = dev_id;
u_char val;
u_char *cfg;
if (!cs) {
printk(KERN_WARNING "Diva: Spurious interrupt!\n");
return;
}
cfg = (u_char *) cs->hw.diva.pci_cfg;
val = *cfg;
if (!(val &PITA_INT0_STATUS)) return; // other shared IRQ
interrupt_ipacx(cs); // handler for chip
*cfg = PITA_INT0_STATUS; // Reset PLX interrupt
}
void
release_io_diva(struct IsdnCardState *cs)
{
int bytecnt;
if (cs->subtyp == DIVA_IPAC_PCI) {
if ((cs->subtyp == DIVA_IPAC_PCI) ||
(cs->subtyp == DIVA_IPACX_PCI) ) {
u_int *cfg = (unsigned int *)cs->hw.diva.pci_cfg;
*cfg = 0; /* disable INT0/1 */
......@@ -711,6 +775,16 @@ reset_diva(struct IsdnCardState *cs)
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout((10*HZ)/1000);
memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xc0);
} else if (cs->subtyp == DIVA_IPACX_PCI) {
unsigned int *ireg = (unsigned int *)(cs->hw.diva.pci_cfg +
PITA_MISC_REG);
*ireg = PITA_PARA_SOFTRESET | PITA_PARA_MPX_MODE;
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout((10*HZ)/1000);
*ireg = PITA_PARA_MPX_MODE | PITA_SER_SOFTRESET;
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout((10*HZ)/1000);
MemWriteISAC_IPACX(cs, IPACX_MASK, 0xff); // Interrupts off
} else { /* DIVA 2.0 */
cs->hw.diva.ctrl_reg = 0; /* Reset On */
byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
......@@ -739,7 +813,10 @@ diva_led_handler(struct IsdnCardState *cs)
{
int blink = 0;
if ((cs->subtyp == DIVA_IPAC_ISA) || (cs->subtyp == DIVA_IPAC_PCI))
// if ((cs->subtyp == DIVA_IPAC_ISA) || (cs->subtyp == DIVA_IPAC_PCI))
if ((cs->subtyp == DIVA_IPAC_ISA) ||
(cs->subtyp == DIVA_IPAC_PCI) ||
(cs->subtyp == DIVA_IPACX_PCI) )
return;
del_timer(&cs->hw.diva.tl);
if (cs->hw.diva.status & DIVA_ASSIGN)
......@@ -782,6 +859,12 @@ Diva_card_msg(struct IsdnCardState *cs, int mt, void *arg)
release_io_diva(cs);
return(0);
case CARD_INIT:
if (cs->subtyp == DIVA_IPACX_PCI) {
ireg = (unsigned int *)cs->hw.diva.pci_cfg;
*ireg = PITA_INT0_ENABLE;
init_ipacx(cs, 3); // init chip and enable interrupts
return (0);
}
if (cs->subtyp == DIVA_IPAC_PCI) {
ireg = (unsigned int *)cs->hw.diva.pci_cfg;
*ireg = PITA_INT0_ENABLE;
......@@ -818,7 +901,9 @@ Diva_card_msg(struct IsdnCardState *cs, int mt, void *arg)
}
break;
}
if ((cs->subtyp != DIVA_IPAC_ISA) && (cs->subtyp != DIVA_IPAC_PCI))
if ((cs->subtyp != DIVA_IPAC_ISA) &&
(cs->subtyp != DIVA_IPAC_PCI) &&
(cs->subtyp != DIVA_IPACX_PCI) )
diva_led_handler(cs);
return(0);
}
......@@ -916,7 +1001,8 @@ setup_diva(struct IsdnCard *card)
printk(KERN_WARNING "Diva: unable to config DIVA PCI\n");
return (0);
#endif /* CONFIG_PCI */
if (cs->subtyp == DIVA_IPAC_PCI) {
if ((cs->subtyp == DIVA_IPAC_PCI) ||
(cs->subtyp == DIVA_IPACX_PCI) ) {
cs->hw.diva.ctrl = 0;
cs->hw.diva.isac = 0;
cs->hw.diva.hscx = 0;
......@@ -938,13 +1024,18 @@ setup_diva(struct IsdnCard *card)
"Diva: %s card configured at %#lx IRQ %d\n",
(cs->subtyp == DIVA_PCI) ? "PCI" :
(cs->subtyp == DIVA_ISA) ? "ISA" :
(cs->subtyp == DIVA_IPAC_ISA) ? "IPAC ISA" : "IPAC PCI",
(cs->subtyp == DIVA_IPAC_ISA) ? "IPAC ISA" :
(cs->subtyp == DIVA_IPAC_PCI) ? "IPAC PCI" : "IPACX PCI",
cs->hw.diva.cfg_reg, cs->irq);
if ((cs->subtyp == DIVA_IPAC_PCI) || (cs->subtyp == DIVA_PCI))
printk(KERN_INFO "Diva: %s PCI space at %#lx\n",
(cs->subtyp == DIVA_PCI) ? "PCI" : "IPAC PCI",
if ((cs->subtyp == DIVA_IPAC_PCI) ||
(cs->subtyp == DIVA_IPACX_PCI) ||
(cs->subtyp == DIVA_PCI) )
printk(KERN_INFO "Diva: %s space at %#lx\n",
(cs->subtyp == DIVA_PCI) ? "PCI" :
(cs->subtyp == DIVA_IPAC_PCI) ? "IPAC PCI" : "IPACX PCI",
cs->hw.diva.pci_cfg);
if (cs->subtyp != DIVA_IPAC_PCI) {
if ((cs->subtyp != DIVA_IPAC_PCI) &&
(cs->subtyp != DIVA_IPACX_PCI) ) {
if (check_region(cs->hw.diva.cfg_reg, bytecnt)) {
printk(KERN_WARNING
"HiSax: %s config port %lx-%lx already in use\n",
......@@ -980,6 +1071,17 @@ setup_diva(struct IsdnCard *card)
cs->irq_func = &diva_irq_ipac_pci;
val = memreadreg(cs->hw.diva.cfg_reg, IPAC_ID);
printk(KERN_INFO "Diva: IPAC version %x\n", val);
} else if (cs->subtyp == DIVA_IPACX_PCI) {
cs->readisac = &MemReadISAC_IPACX;
cs->writeisac = &MemWriteISAC_IPACX;
cs->readisacfifo = &MemReadISACfifo_IPACX;
cs->writeisacfifo = &MemWriteISACfifo_IPACX;
cs->BC_Read_Reg = &MemReadHSCX_IPACX;
cs->BC_Write_Reg = &MemWriteHSCX_IPACX;
cs->BC_Send_Data = 0; // function located in ipacx module
cs->irq_func = &diva_irq_ipacx_pci;
printk(KERN_INFO "Diva: IPACX Design Id: %x\n",
MemReadISAC_IPACX(cs, IPACX_ID) &0x3F);
} else { /* DIVA 2.0 */
cs->hw.diva.tl.function = (void *) diva_led_handler;
cs->hw.diva.tl.data = (long) cs;
......
drivers/isdn/hisax/ipacx.c 0 → 100644
View file @ 98c4217c
This diff is collapsed.
drivers/isdn/hisax/ipacx.h 0 → 100644
View file @ 98c4217c
/*
*
* IPACX specific defines
*
* This software may be used and distributed according to the terms
* of the GNU General Public License, incorporated herein by reference.
*
*/
/* All Registers original Siemens Spec */
#ifndef INCLUDE_IPACX_H
#define INCLUDE_IPACX_H
/* D-channel registers */
#define IPACX_RFIFOD 0x00 /* RD */
#define IPACX_XFIFOD 0x00 /* WR */
#define IPACX_ISTAD 0x20 /* RD */
#define IPACX_MASKD 0x20 /* WR */
#define IPACX_STARD 0x21 /* RD */
#define IPACX_CMDRD 0x21 /* WR */
#define IPACX_MODED 0x22 /* RD/WR */
#define IPACX_EXMD1 0x23 /* RD/WR */
#define IPACX_TIMR1 0x24 /* RD/WR */
#define IPACX_SAP1 0x25 /* WR */
#define IPACX_SAP2 0x26 /* WR */
#define IPACX_RBCLD 0x26 /* RD */
#define IPACX_RBCHD 0x27 /* RD */
#define IPACX_TEI1 0x27 /* WR */
#define IPACX_TEI2 0x28 /* WR */
#define IPACX_RSTAD 0x28 /* RD */
#define IPACX_TMD 0x29 /* RD/WR */
#define IPACX_CIR0 0x2E /* RD */
#define IPACX_CIX0 0x2E /* WR */
#define IPACX_CIR1 0x2F /* RD */
#define IPACX_CIX1 0x2F /* WR */
/* Transceiver registers */
#define IPACX_TR_CONF0 0x30 /* RD/WR */
#define IPACX_TR_CONF1 0x31 /* RD/WR */
#define IPACX_TR_CONF2 0x32 /* RD/WR */
#define IPACX_TR_STA 0x33 /* RD */
#define IPACX_TR_CMD 0x34 /* RD/WR */
#define IPACX_SQRR1 0x35 /* RD */
#define IPACX_SQXR1 0x35 /* WR */
#define IPACX_SQRR2 0x36 /* RD */
#define IPACX_SQXR2 0x36 /* WR */
#define IPACX_SQRR3 0x37 /* RD */
#define IPACX_SQXR3 0x37 /* WR */
#define IPACX_ISTATR 0x38 /* RD */
#define IPACX_MASKTR 0x39 /* RD/WR */
#define IPACX_TR_MODE 0x3A /* RD/WR */
#define IPACX_ACFG1 0x3C /* RD/WR */
#define IPACX_ACFG2 0x3D /* RD/WR */
#define IPACX_AOE 0x3E /* RD/WR */
#define IPACX_ARX 0x3F /* RD */
#define IPACX_ATX 0x3F /* WR */
/* IOM: Timeslot, DPS, CDA */
#define IPACX_CDA10 0x40 /* RD/WR */
#define IPACX_CDA11 0x41 /* RD/WR */
#define IPACX_CDA20 0x42 /* RD/WR */
#define IPACX_CDA21 0x43 /* RD/WR */
#define IPACX_CDA_TSDP10 0x44 /* RD/WR */
#define IPACX_CDA_TSDP11 0x45 /* RD/WR */
#define IPACX_CDA_TSDP20 0x46 /* RD/WR */
#define IPACX_CDA_TSDP21 0x47 /* RD/WR */
#define IPACX_BCHA_TSDP_BC1 0x48 /* RD/WR */
#define IPACX_BCHA_TSDP_BC2 0x49 /* RD/WR */
#define IPACX_BCHB_TSDP_BC1 0x4A /* RD/WR */
#define IPACX_BCHB_TSDP_BC2 0x4B /* RD/WR */
#define IPACX_TR_TSDP_BC1 0x4C /* RD/WR */
#define IPACX_TR_TSDP_BC2 0x4D /* RD/WR */
#define IPACX_CDA1_CR 0x4E /* RD/WR */
#define IPACX_CDA2_CR 0x4F /* RD/WR */
/* IOM: Contol, Sync transfer, Monitor */
#define IPACX_TR_CR 0x50 /* RD/WR */
#define IPACX_TRC_CR 0x50 /* RD/WR */
#define IPACX_BCHA_CR 0x51 /* RD/WR */
#define IPACX_BCHB_CR 0x52 /* RD/WR */
#define IPACX_DCI_CR 0x53 /* RD/WR */
#define IPACX_DCIC_CR 0x53 /* RD/WR */
#define IPACX_MON_CR 0x54 /* RD/WR */
#define IPACX_SDS1_CR 0x55 /* RD/WR */
#define IPACX_SDS2_CR 0x56 /* RD/WR */
#define IPACX_IOM_CR 0x57 /* RD/WR */
#define IPACX_STI 0x58 /* RD */
#define IPACX_ASTI 0x58 /* WR */
#define IPACX_MSTI 0x59 /* RD/WR */
#define IPACX_SDS_CONF 0x5A /* RD/WR */
#define IPACX_MCDA 0x5B /* RD */
#define IPACX_MOR 0x5C /* RD */
#define IPACX_MOX 0x5C /* WR */
#define IPACX_MOSR 0x5D /* RD */
#define IPACX_MOCR 0x5E /* RD/WR */
#define IPACX_MSTA 0x5F /* RD */
#define IPACX_MCONF 0x5F /* WR */
/* Interrupt and general registers */
#define IPACX_ISTA 0x60 /* RD */
#define IPACX_MASK 0x60 /* WR */
#define IPACX_AUXI 0x61 /* RD */
#define IPACX_AUXM 0x61 /* WR */
#define IPACX_MODE1 0x62 /* RD/WR */
#define IPACX_MODE2 0x63 /* RD/WR */
#define IPACX_ID 0x64 /* RD */
#define IPACX_SRES 0x64 /* WR */
#define IPACX_TIMR2 0x65 /* RD/WR */
/* B-channel registers */
#define IPACX_OFF_B1 0x70
#define IPACX_OFF_B2 0x80
#define IPACX_ISTAB 0x00 /* RD */
#define IPACX_MASKB 0x00 /* WR */
#define IPACX_STARB 0x01 /* RD */
#define IPACX_CMDRB 0x01 /* WR */
#define IPACX_MODEB 0x02 /* RD/WR */
#define IPACX_EXMB 0x03 /* RD/WR */
#define IPACX_RAH1 0x05 /* WR */
#define IPACX_RAH2 0x06 /* WR */
#define IPACX_RBCLB 0x06 /* RD */
#define IPACX_RBCHB 0x07 /* RD */
#define IPACX_RAL1 0x07 /* WR */
#define IPACX_RAL2 0x08 /* WR */
#define IPACX_RSTAB 0x08 /* RD */
#define IPACX_TMB 0x09 /* RD/WR */
#define IPACX_RFIFOB 0x0A /*- RD */
#define IPACX_XFIFOB 0x0A /*- WR */
/* Layer 1 Commands */
#define IPACX_CMD_TIM 0x0
#define IPACX_CMD_RES 0x1
#define IPACX_CMD_SSP 0x2
#define IPACX_CMD_SCP 0x3
#define IPACX_CMD_AR8 0x8
#define IPACX_CMD_AR10 0x9
#define IPACX_CMD_ARL 0xa
#define IPACX_CMD_DI 0xf
/* Layer 1 Indications */
#define IPACX_IND_DR 0x0
#define IPACX_IND_RES 0x1
#define IPACX_IND_TMA 0x2
#define IPACX_IND_SLD 0x3
#define IPACX_IND_RSY 0x4
#define IPACX_IND_DR6 0x5
#define IPACX_IND_PU 0x7
#define IPACX_IND_AR 0x8
#define IPACX_IND_ARL 0xa
#define IPACX_IND_CVR 0xb
#define IPACX_IND_AI8 0xc
#define IPACX_IND_AI10 0xd
#define IPACX_IND_AIL 0xe
#define IPACX_IND_DC 0xf
extern void init_ipacx(struct IsdnCardState *cs, int part);
extern void interrupt_ipacx(struct IsdnCardState *cs);
#endif
include/linux/pci_ids.h
View file @ 98c4217c
......@@ -1054,6 +1054,7 @@
#define PCI_DEVICE_ID_EICON_DIVA20PRO_U 0xe003
#define PCI_DEVICE_ID_EICON_DIVA20_U 0xe004
#define PCI_DEVICE_ID_EICON_DIVA201 0xe005
#define PCI_DEVICE_ID_EICON_DIVA202 0xe00b
#define PCI_DEVICE_ID_EICON_MAESTRA 0xe010
#define PCI_DEVICE_ID_EICON_MAESTRAQ 0xe012
#define PCI_DEVICE_ID_EICON_MAESTRAQ_U 0xe013
......
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