Commit 99dc804d authored by Shaohua Li's avatar Shaohua Li Committed by Greg Kroah-Hartman

[PATCH] PCI: disable msi mode in pci_disable_device

Brice said the pci_save_msi_state breaks his driver in his special usage
(not in suspend/resume), as pci_save_msi_state will disable msi mode. In
his usage, pci_save_state will be called at runtime, and later (after
the device operates for some time and has an error) pci_restore_state
will be called.
In another hand, suspend/resume needs disable msi mode, as device should
stop working completely. This patch try to workaround this issue.
Drivers are expected call pci_disable_device in suspend time after
pci_save_state.
Signed-off-by: default avatarShaohua Li <shaohua.li@intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 020d5024
...@@ -453,9 +453,11 @@ static void enable_msi_mode(struct pci_dev *dev, int pos, int type) ...@@ -453,9 +453,11 @@ static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
/* Set enabled bits to single MSI & enable MSI_enable bit */ /* Set enabled bits to single MSI & enable MSI_enable bit */
msi_enable(control, 1); msi_enable(control, 1);
pci_write_config_word(dev, msi_control_reg(pos), control); pci_write_config_word(dev, msi_control_reg(pos), control);
dev->msi_enabled = 1;
} else { } else {
msix_enable(control); msix_enable(control);
pci_write_config_word(dev, msi_control_reg(pos), control); pci_write_config_word(dev, msi_control_reg(pos), control);
dev->msix_enabled = 1;
} }
if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
/* PCI Express Endpoint device detected */ /* PCI Express Endpoint device detected */
...@@ -472,9 +474,11 @@ void disable_msi_mode(struct pci_dev *dev, int pos, int type) ...@@ -472,9 +474,11 @@ void disable_msi_mode(struct pci_dev *dev, int pos, int type)
/* Set enabled bits to single MSI & enable MSI_enable bit */ /* Set enabled bits to single MSI & enable MSI_enable bit */
msi_disable(control); msi_disable(control);
pci_write_config_word(dev, msi_control_reg(pos), control); pci_write_config_word(dev, msi_control_reg(pos), control);
dev->msi_enabled = 0;
} else { } else {
msix_disable(control); msix_disable(control);
pci_write_config_word(dev, msi_control_reg(pos), control); pci_write_config_word(dev, msi_control_reg(pos), control);
dev->msix_enabled = 0;
} }
if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
/* PCI Express Endpoint device detected */ /* PCI Express Endpoint device detected */
...@@ -549,7 +553,6 @@ int pci_save_msi_state(struct pci_dev *dev) ...@@ -549,7 +553,6 @@ int pci_save_msi_state(struct pci_dev *dev)
pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]); pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]);
if (control & PCI_MSI_FLAGS_MASKBIT) if (control & PCI_MSI_FLAGS_MASKBIT)
pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]); pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]);
disable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
save_state->cap_nr = PCI_CAP_ID_MSI; save_state->cap_nr = PCI_CAP_ID_MSI;
pci_add_saved_cap(dev, save_state); pci_add_saved_cap(dev, save_state);
return 0; return 0;
...@@ -639,7 +642,6 @@ int pci_save_msix_state(struct pci_dev *dev) ...@@ -639,7 +642,6 @@ int pci_save_msix_state(struct pci_dev *dev)
} }
dev->irq = temp; dev->irq = temp;
disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
save_state->cap_nr = PCI_CAP_ID_MSIX; save_state->cap_nr = PCI_CAP_ID_MSIX;
pci_add_saved_cap(dev, save_state); pci_add_saved_cap(dev, save_state);
return 0; return 0;
......
...@@ -552,6 +552,13 @@ pci_disable_device(struct pci_dev *dev) ...@@ -552,6 +552,13 @@ pci_disable_device(struct pci_dev *dev)
{ {
u16 pci_command; u16 pci_command;
if (dev->msi_enabled)
disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
PCI_CAP_ID_MSI);
if (dev->msix_enabled)
disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
PCI_CAP_ID_MSIX);
pci_read_config_word(dev, PCI_COMMAND, &pci_command); pci_read_config_word(dev, PCI_COMMAND, &pci_command);
if (pci_command & PCI_COMMAND_MASTER) { if (pci_command & PCI_COMMAND_MASTER) {
pci_command &= ~PCI_COMMAND_MASTER; pci_command &= ~PCI_COMMAND_MASTER;
......
...@@ -163,6 +163,8 @@ struct pci_dev { ...@@ -163,6 +163,8 @@ struct pci_dev {
unsigned int no_msi:1; /* device may not use msi */ unsigned int no_msi:1; /* device may not use msi */
unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
unsigned int broken_parity_status:1; /* Device generates false positive parity */ unsigned int broken_parity_status:1; /* Device generates false positive parity */
unsigned int msi_enabled:1;
unsigned int msix_enabled:1;
u32 saved_config_space[16]; /* config space saved at suspend time */ u32 saved_config_space[16]; /* config space saved at suspend time */
struct hlist_head saved_cap_space; struct hlist_head saved_cap_space;
......
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