Commit 99e68e9c authored by Yoichi Yuasa's avatar Yoichi Yuasa Committed by Linus Torvalds

[PATCH] mips: add spare timer init

This patch adds spare timer initialization for NEC VR41xx.
Signed-off-by: default avatarYoichi Yuasa <yuasa@hh.iij4u.or.jp>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 728a9e1a
...@@ -19,9 +19,11 @@ ...@@ -19,9 +19,11 @@
*/ */
#include <linux/init.h> #include <linux/init.h>
#include <linux/ioport.h> #include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/string.h> #include <linux/string.h>
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <asm/time.h>
#include <asm/vr41xx/vr41xx.h> #include <asm/vr41xx/vr41xx.h>
#define IO_MEM_RESOURCE_START 0UL #define IO_MEM_RESOURCE_START 0UL
...@@ -33,6 +35,29 @@ static void __init iomem_resource_init(void) ...@@ -33,6 +35,29 @@ static void __init iomem_resource_init(void)
iomem_resource.end = IO_MEM_RESOURCE_END; iomem_resource.end = IO_MEM_RESOURCE_END;
} }
static void __init setup_timer_frequency(void)
{
unsigned long tclock;
tclock = vr41xx_get_tclock_frequency();
if (current_cpu_data.processor_id == PRID_VR4131_REV2_0 ||
current_cpu_data.processor_id == PRID_VR4131_REV2_1)
mips_hpt_frequency = tclock / 2;
else
mips_hpt_frequency = tclock / 4;
}
static void __init setup_timer_irq(struct irqaction *irq)
{
setup_irq(TIMER_IRQ, irq);
}
static void __init timer_init(void)
{
board_time_init = setup_timer_frequency;
board_timer_setup = setup_timer_irq;
}
void __init prom_init(void) void __init prom_init(void)
{ {
int argc, i; int argc, i;
...@@ -49,6 +74,8 @@ void __init prom_init(void) ...@@ -49,6 +74,8 @@ void __init prom_init(void)
vr41xx_calculate_clock_frequency(); vr41xx_calculate_clock_frequency();
timer_init();
iomem_resource_init(); iomem_resource_init();
} }
......
...@@ -84,7 +84,7 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock); ...@@ -84,7 +84,7 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock);
#define INT2_CASCADE_IRQ MIPS_CPU_IRQ(4) #define INT2_CASCADE_IRQ MIPS_CPU_IRQ(4)
#define INT3_CASCADE_IRQ MIPS_CPU_IRQ(5) #define INT3_CASCADE_IRQ MIPS_CPU_IRQ(5)
#define INT4_CASCADE_IRQ MIPS_CPU_IRQ(6) #define INT4_CASCADE_IRQ MIPS_CPU_IRQ(6)
#define MIPS_COUNTER_IRQ MIPS_CPU_IRQ(7) #define TIMER_IRQ MIPS_CPU_IRQ(7)
/* SYINT1 Interrupt Numbers */ /* SYINT1 Interrupt Numbers */
#define SYSINT1_IRQ_BASE 8 #define SYSINT1_IRQ_BASE 8
......
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