Commit 9a38e989 authored by root's avatar root Committed by Russell King

Merge branch 'devel' of...

Merge branch 'devel' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel
parents 7d83f8fc 5fa82eb8
...@@ -3543,6 +3543,22 @@ M: linux@arm.linux.org.uk ...@@ -3543,6 +3543,22 @@ M: linux@arm.linux.org.uk
L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
S: Maintained S: Maintained
PXA168 SUPPORT
P: Eric Miao
M: eric.miao@marvell.com
P: Jason Chagas
M: jason.chagas@marvell.com
L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
T: git kernel.org:/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6.git
S: Supported
PXA910 SUPPORT
P: Eric Miao
M: eric.miao@marvell.com
L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
T: git kernel.org:/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6.git
S: Supported
PXA MMCI DRIVER PXA MMCI DRIVER
S: Orphan S: Orphan
......
...@@ -478,12 +478,29 @@ config ARCH_PXA ...@@ -478,12 +478,29 @@ config ARCH_PXA
select HAVE_CLK select HAVE_CLK
select COMMON_CLKDEV select COMMON_CLKDEV
select ARCH_REQUIRE_GPIOLIB select ARCH_REQUIRE_GPIOLIB
select HAVE_CLK
select COMMON_CLKDEV
select GENERIC_TIME select GENERIC_TIME
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select TICK_ONESHOT select TICK_ONESHOT
select PLAT_PXA
help help
Support for Intel/Marvell's PXA2xx/PXA3xx processor line. Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
config ARCH_MMP
bool "Marvell PXA168/910"
depends on MMU
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
select HAVE_CLK
select COMMON_CLKDEV
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select TICK_ONESHOT
select PLAT_PXA
help
Support for Marvell's PXA168/910 processor line.
config ARCH_RPC config ARCH_RPC
bool "RiscPC" bool "RiscPC"
select ARCH_ACORN select ARCH_ACORN
...@@ -618,6 +635,9 @@ source "arch/arm/mach-loki/Kconfig" ...@@ -618,6 +635,9 @@ source "arch/arm/mach-loki/Kconfig"
source "arch/arm/mach-mv78xx0/Kconfig" source "arch/arm/mach-mv78xx0/Kconfig"
source "arch/arm/mach-pxa/Kconfig" source "arch/arm/mach-pxa/Kconfig"
source "arch/arm/plat-pxa/Kconfig"
source "arch/arm/mach-mmp/Kconfig"
source "arch/arm/mach-sa1100/Kconfig" source "arch/arm/mach-sa1100/Kconfig"
...@@ -687,12 +707,15 @@ config PLAT_IOP ...@@ -687,12 +707,15 @@ config PLAT_IOP
config PLAT_ORION config PLAT_ORION
bool bool
config PLAT_PXA
bool
source arch/arm/mm/Kconfig source arch/arm/mm/Kconfig
config IWMMXT config IWMMXT
bool "Enable iWMMXt support" bool "Enable iWMMXt support"
depends on CPU_XSCALE || CPU_XSC3 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK
default y if PXA27x || PXA3xx default y if PXA27x || PXA3xx || ARCH_MMP
help help
Enable support for iWMMXt context switching at run time if Enable support for iWMMXt context switching at run time if
running on a CPU that supports it. running on a CPU that supports it.
......
...@@ -109,6 +109,8 @@ ifeq ($(CONFIG_ARCH_SA1100),y) ...@@ -109,6 +109,8 @@ ifeq ($(CONFIG_ARCH_SA1100),y)
textofs-$(CONFIG_SA1111) := 0x00208000 textofs-$(CONFIG_SA1111) := 0x00208000
endif endif
machine-$(CONFIG_ARCH_PXA) := pxa machine-$(CONFIG_ARCH_PXA) := pxa
machine-$(CONFIG_ARCH_MMP) := mmp
plat-$(CONFIG_PLAT_PXA) := pxa
machine-$(CONFIG_ARCH_L7200) := l7200 machine-$(CONFIG_ARCH_L7200) := l7200
machine-$(CONFIG_ARCH_INTEGRATOR) := integrator machine-$(CONFIG_ARCH_INTEGRATOR) := integrator
textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000
......
...@@ -636,6 +636,18 @@ proc_types: ...@@ -636,6 +636,18 @@ proc_types:
b __armv4_mmu_cache_off b __armv4_mmu_cache_off
b __armv4_mmu_cache_flush b __armv4_mmu_cache_flush
.word 0x56158000 @ PXA168
.word 0xfffff000
b __armv4_mmu_cache_on
b __armv4_mmu_cache_off
b __armv5tej_mmu_cache_flush
.word 0x56056930
.word 0xff0ffff0 @ PXA935
b __armv4_mmu_cache_on
b __armv4_mmu_cache_off
b __armv4_mmu_cache_flush
.word 0x56050000 @ Feroceon .word 0x56050000 @ Feroceon
.word 0xff0f0000 .word 0xff0f0000
b __armv4_mmu_cache_on b __armv4_mmu_cache_on
......
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...@@ -94,6 +94,14 @@ ...@@ -94,6 +94,14 @@
# endif # endif
#endif #endif
#if defined(CONFIG_CPU_MOHAWK)
# ifdef _CACHE
# define MULTI_CACHE 1
# else
# define _CACHE mohawk
# endif
#endif
#if defined(CONFIG_CPU_FEROCEON) #if defined(CONFIG_CPU_FEROCEON)
# define MULTI_CACHE 1 # define MULTI_CACHE 1
#endif #endif
......
...@@ -185,6 +185,14 @@ ...@@ -185,6 +185,14 @@
# define CPU_NAME cpu_xsc3 # define CPU_NAME cpu_xsc3
# endif # endif
# endif # endif
# ifdef CONFIG_CPU_MOHAWK
# ifdef CPU_NAME
# undef MULTI_CPU
# define MULTI_CPU
# else
# define CPU_NAME cpu_mohawk
# endif
# endif
# ifdef CONFIG_CPU_FEROCEON # ifdef CONFIG_CPU_FEROCEON
# ifdef CPU_NAME # ifdef CPU_NAME
# undef MULTI_CPU # undef MULTI_CPU
......
...@@ -36,6 +36,7 @@ AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 ...@@ -36,6 +36,7 @@ AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312
obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o
obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o
obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o
obj-$(CONFIG_IWMMXT) += iwmmxt.o obj-$(CONFIG_IWMMXT) += iwmmxt.o
AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt
......
if ARCH_MMP
menu "Marvell PXA168/910 Implmentations"
config MACH_ASPENITE
bool "Marvell's PXA168 Aspenite Development Board"
select CPU_PXA168
help
Say 'Y' here if you want to support the Marvell PXA168-based
Aspenite Development Board.
config MACH_ZYLONITE2
bool "Marvell's PXA168 Zylonite2 Development Board"
select CPU_PXA168
help
Say 'Y' here if you want to support the Marvell PXA168-based
Zylonite2 Development Board.
config MACH_TAVOREVB
bool "Marvell's PXA910 TavorEVB Development Board"
select CPU_PXA910
help
Say 'Y' here if you want to support the Marvell PXA910-based
TavorEVB Development Board.
config MACH_TTC_DKB
bool "Marvell's PXA910 TavorEVB Development Board"
select CPU_PXA910
help
Say 'Y' here if you want to support the Marvell PXA910-based
TTC_DKB Development Board.
endmenu
config CPU_PXA168
bool
select CPU_MOHAWK
help
Select code specific to PXA168
config CPU_PXA910
bool
select CPU_MOHAWK
help
Select code specific to PXA910
endif
#
# Makefile for Marvell's PXA168 processors line
#
obj-y += common.o clock.o devices.o irq.o time.o
# SoC support
obj-$(CONFIG_CPU_PXA168) += pxa168.o
obj-$(CONFIG_CPU_PXA910) += pxa910.o
# board support
obj-$(CONFIG_MACH_ASPENITE) += aspenite.o
obj-$(CONFIG_MACH_ZYLONITE2) += aspenite.o
obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o
obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o
zreladdr-y := 0x00008000
/*
* linux/arch/arm/mach-mmp/aspenite.c
*
* Support for the Marvell PXA168-based Aspenite and Zylonite2
* Development Platform.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/smc91x.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/addr-map.h>
#include <mach/mfp-pxa168.h>
#include <mach/pxa168.h>
#include <mach/gpio.h>
#include "common.h"
static unsigned long common_pin_config[] __initdata = {
/* Data Flash Interface */
GPIO0_DFI_D15,
GPIO1_DFI_D14,
GPIO2_DFI_D13,
GPIO3_DFI_D12,
GPIO4_DFI_D11,
GPIO5_DFI_D10,
GPIO6_DFI_D9,
GPIO7_DFI_D8,
GPIO8_DFI_D7,
GPIO9_DFI_D6,
GPIO10_DFI_D5,
GPIO11_DFI_D4,
GPIO12_DFI_D3,
GPIO13_DFI_D2,
GPIO14_DFI_D1,
GPIO15_DFI_D0,
/* Static Memory Controller */
GPIO18_SMC_nCS0,
GPIO34_SMC_nCS1,
GPIO23_SMC_nLUA,
GPIO25_SMC_nLLA,
GPIO28_SMC_RDY,
GPIO29_SMC_SCLK,
GPIO35_SMC_BE1,
GPIO36_SMC_BE2,
GPIO27_GPIO, /* Ethernet IRQ */
/* UART1 */
GPIO107_UART1_RXD,
GPIO108_UART1_TXD,
};
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};
static struct resource smc91x_resources[] = {
[0] = {
.start = SMC_CS1_PHYS_BASE + 0x300,
.end = SMC_CS1_PHYS_BASE + 0xfffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = gpio_to_irq(27),
.end = gpio_to_irq(27),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
}
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.dev = {
.platform_data = &smc91x_info,
},
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
static void __init common_init(void)
{
mfp_config(ARRAY_AND_SIZE(common_pin_config));
/* on-chip devices */
pxa168_add_uart(1);
/* off-chip devices */
platform_device_register(&smc91x_device);
}
MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")
.phys_io = APB_PHYS_BASE,
.boot_params = 0x00000100,
.io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
.map_io = pxa_map_io,
.init_irq = pxa168_init_irq,
.timer = &pxa168_timer,
.init_machine = common_init,
MACHINE_END
MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform")
.phys_io = APB_PHYS_BASE,
.boot_params = 0x00000100,
.io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
.map_io = pxa_map_io,
.init_irq = pxa168_init_irq,
.timer = &pxa168_timer,
.init_machine = common_init,
MACHINE_END
/*
* linux/arch/arm/mach-mmp/clock.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <mach/regs-apbc.h>
#include "clock.h"
static void apbc_clk_enable(struct clk *clk)
{
uint32_t clk_rst;
clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(clk->fnclksel);
__raw_writel(clk_rst, clk->clk_rst);
}
static void apbc_clk_disable(struct clk *clk)
{
__raw_writel(0, clk->clk_rst);
}
struct clkops apbc_clk_ops = {
.enable = apbc_clk_enable,
.disable = apbc_clk_disable,
};
static DEFINE_SPINLOCK(clocks_lock);
int clk_enable(struct clk *clk)
{
unsigned long flags;
spin_lock_irqsave(&clocks_lock, flags);
if (clk->enabled++ == 0)
clk->ops->enable(clk);
spin_unlock_irqrestore(&clocks_lock, flags);
return 0;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
unsigned long flags;
WARN_ON(clk->enabled == 0);
spin_lock_irqsave(&clocks_lock, flags);
if (--clk->enabled == 0)
clk->ops->disable(clk);
spin_unlock_irqrestore(&clocks_lock, flags);
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
unsigned long rate;
if (clk->ops->getrate)
rate = clk->ops->getrate(clk);
else
rate = clk->rate;
return rate;
}
EXPORT_SYMBOL(clk_get_rate);
void clks_register(struct clk_lookup *clks, size_t num)
{
int i;
for (i = 0; i < num; i++)
clkdev_add(&clks[i]);
}
/*
* linux/arch/arm/mach-mmp/clock.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <asm/clkdev.h>
struct clkops {
void (*enable)(struct clk *);
void (*disable)(struct clk *);
unsigned long (*getrate)(struct clk *);
};
struct clk {
const struct clkops *ops;
void __iomem *clk_rst; /* clock reset control register */
int fnclksel; /* functional clock select (APBC) */
uint32_t enable_val; /* value for clock enable (APMU) */
unsigned long rate;
int enabled;
};
extern struct clkops apbc_clk_ops;
#define APBC_CLK(_name, _reg, _fnclksel, _rate) \
struct clk clk_##_name = { \
.clk_rst = (void __iomem *)APBC_##_reg, \
.fnclksel = _fnclksel, \
.rate = _rate, \
.ops = &apbc_clk_ops, \
}
#define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops) \
struct clk clk_##_name = { \
.clk_rst = (void __iomem *)APBC_##_reg, \
.fnclksel = _fnclksel, \
.rate = _rate, \
.ops = _ops, \
}
#define APMU_CLK(_name, _reg, _eval, _rate) \
struct clk clk_##_name = { \
.clk_rst = (void __iomem *)APMU_##_reg, \
.enable_val = _eval, \
.rate = _rate, \
.ops = &apmu_clk_ops, \
}
#define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops) \
struct clk clk_##_name = { \
.clk_rst = (void __iomem *)APMU_##_reg, \
.enable_val = _eval, \
.rate = _rate, \
.ops = _ops, \
}
#define INIT_CLKREG(_clk, _devname, _conname) \
{ \
.clk = _clk, \
.dev_id = _devname, \
.con_id = _conname, \
}
extern struct clk clk_pxa168_gpio;
extern struct clk clk_pxa168_timers;
extern void clks_register(struct clk_lookup *, size_t);
/*
* linux/arch/arm/mach-mmp/common.c
*
* Code common to PXA168 processor lines
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#include <mach/addr-map.h>
#include "common.h"
static struct map_desc standard_io_desc[] __initdata = {
{
.pfn = __phys_to_pfn(APB_PHYS_BASE),
.virtual = APB_VIRT_BASE,
.length = APB_PHYS_SIZE,
.type = MT_DEVICE,
}, {
.pfn = __phys_to_pfn(AXI_PHYS_BASE),
.virtual = AXI_VIRT_BASE,
.length = AXI_PHYS_SIZE,
.type = MT_DEVICE,
},
};
void __init pxa_map_io(void)
{
iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
}
#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
struct sys_timer;
extern void timer_init(int irq);
extern struct sys_timer pxa168_timer;
extern struct sys_timer pxa910_timer;
extern void __init pxa168_init_irq(void);
extern void __init pxa910_init_irq(void);
extern void __init icu_init_irq(void);
extern void __init pxa_map_io(void);
/*
* linux/arch/arm/mach-mmp/devices.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <asm/irq.h>
#include <mach/devices.h>
int __init pxa_register_device(struct pxa_device_desc *desc,
void *data, size_t size)
{
struct platform_device *pdev;
struct resource res[2 + MAX_RESOURCE_DMA];
int i, ret = 0, nres = 0;
pdev = platform_device_alloc(desc->drv_name, desc->id);
if (pdev == NULL)
return -ENOMEM;
pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
memset(res, 0, sizeof(res));
if (desc->start != -1ul && desc->size > 0) {
res[nres].start = desc->start;
res[nres].end = desc->start + desc->size - 1;
res[nres].flags = IORESOURCE_MEM;
nres++;
}
if (desc->irq != NO_IRQ) {
res[nres].start = desc->irq;
res[nres].end = desc->irq;
res[nres].flags = IORESOURCE_IRQ;
nres++;
}
for (i = 0; i < MAX_RESOURCE_DMA; i++, nres++) {
if (desc->dma[i] == 0)
break;
res[nres].start = desc->dma[i];
res[nres].end = desc->dma[i];
res[nres].flags = IORESOURCE_DMA;
}
ret = platform_device_add_resources(pdev, res, nres);
if (ret) {
platform_device_put(pdev);
return ret;
}
if (data && size) {
ret = platform_device_add_data(pdev, data, size);
if (ret) {
platform_device_put(pdev);
return ret;
}
}
return platform_device_add(pdev);
}
/*
* linux/arch/arm/mach-mmp/include/mach/addr-map.h
*
* Common address map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_MACH_ADDR_MAP_H
#define __ASM_MACH_ADDR_MAP_H
/* APB - Application Subsystem Peripheral Bus
*
* NOTE: the DMA controller registers are actually on the AXI fabric #1
* slave port to AHB/APB bridge, due to its close relationship to those
* peripherals on APB, let's count it into the ABP mapping area.
*/
#define APB_PHYS_BASE 0xd4000000
#define APB_VIRT_BASE 0xfe000000
#define APB_PHYS_SIZE 0x00200000
#define AXI_PHYS_BASE 0xd4200000
#define AXI_VIRT_BASE 0xfe200000
#define AXI_PHYS_SIZE 0x00200000
/* Static Memory Controller - Chip Select 0 and 1 */
#define SMC_CS0_PHYS_BASE 0x80000000
#define SMC_CS0_PHYS_SIZE 0x10000000
#define SMC_CS1_PHYS_BASE 0x90000000
#define SMC_CS1_PHYS_SIZE 0x10000000
#endif /* __ASM_MACH_ADDR_MAP_H */
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif /* __ASM_MACH_CLKDEV_H */
#ifndef __ASM_MACH_CPUTYPE_H
#define __ASM_MACH_CPUTYPE_H
#include <asm/cputype.h>
/*
* CPU Stepping OLD_ID CPU_ID CHIP_ID
*
* PXA168 A0 0x41159263 0x56158400 0x00A0A333
* PXA910 Y0 0x41159262 0x56158000 0x00F0C910
*/
#ifdef CONFIG_CPU_PXA168
# define __cpu_is_pxa168(id) \
({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x84; })
#else
# define __cpu_is_pxa168(id) (0)
#endif
#ifdef CONFIG_CPU_PXA910
# define __cpu_is_pxa910(id) \
({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x80; })
#else
# define __cpu_is_pxa910(id) (0)
#endif
#define cpu_is_pxa168() ({ __cpu_is_pxa168(read_cpuid_id()); })
#define cpu_is_pxa910() ({ __cpu_is_pxa910(read_cpuid_id()); })
#endif /* __ASM_MACH_CPUTYPE_H */
/* arch/arm/mach-mmp/include/mach/debug-macro.S
*
* Debugging macro include header
*
* Copied from arch/arm/mach-pxa/include/mach/debug.S
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <mach/addr-map.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
ldreq \rx, =APB_PHYS_BASE @ physical
ldrne \rx, =APB_VIRT_BASE @ virtual
orr \rx, \rx, #0x00017000
.endm
#define UART_SHIFT 2
#include <asm/hardware/debug-8250.S>
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/*
* linux/arch/arm/mach-mmp/include/mach/dma.h
*/
#ifndef __ASM_MACH_DMA_H
#define __ASM_MACH_DMA_H
#include <mach/addr-map.h>
#define DMAC_REGS_VIRT (APB_VIRT_BASE + 0x00000)
#include <plat/dma.h>
#endif /* __ASM_MACH_DMA_H */
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#ifndef __ASM_MACH_HARDWARE_H
#define __ASM_MACH_HARDWARE_H
#endif /* __ASM_MACH_HARDWARE_H */
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