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Commit 9a8665ab authored by Maciej Purski's avatar Maciej Purski Committed by Krzysztof Kozlowski
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ARM: dts: exynos: Add soc node to exynos4210 

Soc nodes are used in other exynos DTS. Exynos4210 boards should use
them as well.
Signed-off-by: default avatarMaciej Purski <m.purski@samsung.com>
Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parent 73a901d0
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arch/arm/boot/dts/exynos4210.dtsi
View file @ 9a8665ab
...@@ -60,314 +60,317 @@ cpu@901 { ...@@ -60,314 +60,317 @@ cpu@901 {
}; };
}; };
sysram: sysram@2020000 { soc: soc {
compatible = "mmio-sram"; sysram: sysram@2020000 {
reg = <0x02020000 0x20000>; compatible = "mmio-sram";
#address-cells = <1>; reg = <0x02020000 0x20000>;
#size-cells = <1>; #address-cells = <1>;
ranges = <0 0x02020000 0x20000>; #size-cells = <1>;
ranges = <0 0x02020000 0x20000>;
smp-sysram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
smp-sysram@0 { smp-sysram@1f000 {
compatible = "samsung,exynos4210-sysram"; compatible = "samsung,exynos4210-sysram-ns";
reg = <0x0 0x1000>; reg = <0x1f000 0x1000>;
};
}; };
smp-sysram@1f000 { pd_lcd1: lcd1-power-domain@10023ca0 {
compatible = "samsung,exynos4210-sysram-ns"; compatible = "samsung,exynos4210-pd";
reg = <0x1f000 0x1000>; reg = <0x10023CA0 0x20>;
#power-domain-cells = <0>;
label = "LCD1";
}; };
};
pd_lcd1: lcd1-power-domain@10023ca0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CA0 0x20>;
#power-domain-cells = <0>;
label = "LCD1";
};
l2c: l2-cache-controller@10502000 { l2c: l2-cache-controller@10502000 {
compatible = "arm,pl310-cache"; compatible = "arm,pl310-cache";
reg = <0x10502000 0x1000>; reg = <0x10502000 0x1000>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
arm,tag-latency = <2 2 1>; arm,tag-latency = <2 2 1>;
arm,data-latency = <2 2 1>; arm,data-latency = <2 2 1>;
}; };
mct: mct@10050000 { mct: mct@10050000 {
compatible = "samsung,exynos4210-mct"; compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>; reg = <0x10050000 0x800>;
interrupt-parent = <&mct_map>; interrupt-parent = <&mct_map>;
interrupts = <0>, <1>, <2>, <3>, <4>, <5>; interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct"; clock-names = "fin_pll", "mct";
mct_map: mct-map { mct_map: mct-map {
#interrupt-cells = <1>; #interrupt-cells = <1>;
#address-cells = <0>; #address-cells = <0>;
#size-cells = <0>; #size-cells = <0>;
interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, interrupt-map =
<0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
<1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>, <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
<2 &combiner 12 6>, <2 &combiner 12 6>,
<3 &combiner 12 7>, <3 &combiner 12 7>,
<4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>, <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
<5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>; <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
};
}; };
};
watchdog: watchdog@10060000 { watchdog: watchdog@10060000 {
compatible = "samsung,s3c6410-wdt"; compatible = "samsung,s3c6410-wdt";
reg = <0x10060000 0x100>; reg = <0x10060000 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_WDT>; clocks = <&clock CLK_WDT>;
clock-names = "watchdog"; clock-names = "watchdog";
}; };
clock: clock-controller@10030000 { clock: clock-controller@10030000 {
compatible = "samsung,exynos4210-clock"; compatible = "samsung,exynos4210-clock";
reg = <0x10030000 0x20000>; reg = <0x10030000 0x20000>;
#clock-cells = <1>; #clock-cells = <1>;
}; };
pinctrl_0: pinctrl@11400000 { pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4210-pinctrl"; compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>; reg = <0x11400000 0x1000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
}; };
pinctrl_1: pinctrl@11000000 { pinctrl_1: pinctrl@11000000 {
compatible = "samsung,exynos4210-pinctrl"; compatible = "samsung,exynos4210-pinctrl";
reg = <0x11000000 0x1000>; reg = <0x11000000 0x1000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
wakup_eint: wakeup-interrupt-controller { wakup_eint: wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint"; compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
}; };
};
pinctrl_2: pinctrl@3860000 { pinctrl_2: pinctrl@3860000 {
compatible = "samsung,exynos4210-pinctrl"; compatible = "samsung,exynos4210-pinctrl";
reg = <0x03860000 0x1000>; reg = <0x03860000 0x1000>;
}; };
thermal-zones { g2d: g2d@12800000 {
cpu_thermal: cpu-thermal { compatible = "samsung,s5pv210-g2d";
polling-delay-passive = <0>; reg = <0x12800000 0x1000>;
polling-delay = <0>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
thermal-sensors = <&tmu 0>; clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
clock-names = "sclk_fimg2d", "fimg2d";
power-domains = <&pd_lcd0>;
iommus = <&sysmmu_g2d>;
};
trips { ppmu_lcd1: ppmu_lcd1@12240000 {
cpu_alert0: cpu-alert-0 { compatible = "samsung,exynos-ppmu";
temperature = <85000>; /* millicelsius */ reg = <0x12240000 0x2000>;
}; clocks = <&clock CLK_PPMULCD1>;
cpu_alert1: cpu-alert-1 { clock-names = "ppmu";
temperature = <100000>; /* millicelsius */ status = "disabled";
};
cpu_alert2: cpu-alert-2 {
temperature = <110000>; /* millicelsius */
};
};
}; };
};
g2d: g2d@12800000 { sysmmu_g2d: sysmmu@12a20000 {
compatible = "samsung,s5pv210-g2d"; compatible = "samsung,exynos-sysmmu";
reg = <0x12800000 0x1000>; reg = <0x12A20000 0x1000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&combiner>;
clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; interrupts = <4 7>;
clock-names = "sclk_fimg2d", "fimg2d"; clock-names = "sysmmu", "master";
power-domains = <&pd_lcd0>; clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
iommus = <&sysmmu_g2d>; power-domains = <&pd_lcd0>;
}; #iommu-cells = <0>;
};
ppmu_lcd1: ppmu_lcd1@12240000 { sysmmu_fimd1: sysmmu@12220000 {
compatible = "samsung,exynos-ppmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x12240000 0x2000>; interrupt-parent = <&combiner>;
clocks = <&clock CLK_PPMULCD1>; reg = <0x12220000 0x1000>;
clock-names = "ppmu"; interrupts = <5 3>;
status = "disabled"; clock-names = "sysmmu", "master";
}; clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
power-domains = <&pd_lcd1>;
#iommu-cells = <0>;
};
sysmmu_g2d: sysmmu@12a20000 { bus_dmc: bus_dmc {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-bus";
reg = <0x12A20000 0x1000>; clocks = <&clock CLK_DIV_DMC>;
interrupt-parent = <&combiner>; clock-names = "bus";
interrupts = <4 7>; operating-points-v2 = <&bus_dmc_opp_table>;
clock-names = "sysmmu", "master"; status = "disabled";
clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; };
power-domains = <&pd_lcd0>;
#iommu-cells = <0>;
};
sysmmu_fimd1: sysmmu@12220000 { bus_acp: bus_acp {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-bus";
interrupt-parent = <&combiner>; clocks = <&clock CLK_DIV_ACP>;
reg = <0x12220000 0x1000>; clock-names = "bus";
interrupts = <5 3>; operating-points-v2 = <&bus_acp_opp_table>;
clock-names = "sysmmu", "master"; status = "disabled";
clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; };
power-domains = <&pd_lcd1>;
#iommu-cells = <0>;
};
bus_dmc: bus_dmc { bus_peri: bus_peri {
compatible = "samsung,exynos-bus"; compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DIV_DMC>; clocks = <&clock CLK_ACLK100>;
clock-names = "bus"; clock-names = "bus";
operating-points-v2 = <&bus_dmc_opp_table>; operating-points-v2 = <&bus_peri_opp_table>;
status = "disabled"; status = "disabled";
}; };
bus_acp: bus_acp { bus_fsys: bus_fsys {
compatible = "samsung,exynos-bus"; compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DIV_ACP>; clocks = <&clock CLK_ACLK133>;
clock-names = "bus"; clock-names = "bus";
operating-points-v2 = <&bus_acp_opp_table>; operating-points-v2 = <&bus_fsys_opp_table>;
status = "disabled"; status = "disabled";
}; };
bus_peri: bus_peri { bus_display: bus_display {
compatible = "samsung,exynos-bus"; compatible = "samsung,exynos-bus";
clocks = <&clock CLK_ACLK100>; clocks = <&clock CLK_ACLK160>;
clock-names = "bus"; clock-names = "bus";
operating-points-v2 = <&bus_peri_opp_table>; operating-points-v2 = <&bus_display_opp_table>;
status = "disabled"; status = "disabled";
}; };
bus_fsys: bus_fsys { bus_lcd0: bus_lcd0 {
compatible = "samsung,exynos-bus"; compatible = "samsung,exynos-bus";
clocks = <&clock CLK_ACLK133>; clocks = <&clock CLK_ACLK200>;
clock-names = "bus"; clock-names = "bus";
operating-points-v2 = <&bus_fsys_opp_table>; operating-points-v2 = <&bus_leftbus_opp_table>;
status = "disabled"; status = "disabled";
}; };
bus_display: bus_display { bus_leftbus: bus_leftbus {
compatible = "samsung,exynos-bus"; compatible = "samsung,exynos-bus";
clocks = <&clock CLK_ACLK160>; clocks = <&clock CLK_DIV_GDL>;
clock-names = "bus"; clock-names = "bus";
operating-points-v2 = <&bus_display_opp_table>; operating-points-v2 = <&bus_leftbus_opp_table>;
status = "disabled"; status = "disabled";
}; };
bus_lcd0: bus_lcd0 { bus_rightbus: bus_rightbus {
compatible = "samsung,exynos-bus"; compatible = "samsung,exynos-bus";
clocks = <&clock CLK_ACLK200>; clocks = <&clock CLK_DIV_GDR>;
clock-names = "bus"; clock-names = "bus";
operating-points-v2 = <&bus_leftbus_opp_table>; operating-points-v2 = <&bus_leftbus_opp_table>;
status = "disabled"; status = "disabled";
}; };
bus_leftbus: bus_leftbus { bus_mfc: bus_mfc {
compatible = "samsung,exynos-bus"; compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DIV_GDL>; clocks = <&clock CLK_SCLK_MFC>;
clock-names = "bus"; clock-names = "bus";
operating-points-v2 = <&bus_leftbus_opp_table>; operating-points-v2 = <&bus_leftbus_opp_table>;
status = "disabled"; status = "disabled";
}; };
bus_rightbus: bus_rightbus { bus_dmc_opp_table: opp_table1 {
compatible = "samsung,exynos-bus"; compatible = "operating-points-v2";
clocks = <&clock CLK_DIV_GDR>; opp-shared;
clock-names = "bus";
operating-points-v2 = <&bus_leftbus_opp_table>;
status = "disabled";
};
bus_mfc: bus_mfc { opp-134000000 {
compatible = "samsung,exynos-bus"; opp-hz = /bits/ 64 <134000000>;
clocks = <&clock CLK_SCLK_MFC>; opp-microvolt = <1025000>;
clock-names = "bus"; };
operating-points-v2 = <&bus_leftbus_opp_table>; opp-267000000 {
status = "disabled"; opp-hz = /bits/ 64 <267000000>;
}; opp-microvolt = <1050000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1150000>;
};
};
bus_dmc_opp_table: opp_table1 { bus_acp_opp_table: opp_table2 {
compatible = "operating-points-v2"; compatible = "operating-points-v2";
opp-shared; opp-shared;
opp-134000000 { opp-134000000 {
opp-hz = /bits/ 64 <134000000>; opp-hz = /bits/ 64 <134000000>;
opp-microvolt = <1025000>; };
}; opp-160000000 {
opp-267000000 { opp-hz = /bits/ 64 <160000000>;
opp-hz = /bits/ 64 <267000000>; };
opp-microvolt = <1050000>; opp-200000000 {
}; opp-hz = /bits/ 64 <200000000>;
opp-400000000 { };
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1150000>;
}; };
};
bus_acp_opp_table: opp_table2 { bus_peri_opp_table: opp_table3 {
compatible = "operating-points-v2"; compatible = "operating-points-v2";
opp-shared; opp-shared;
opp-134000000 { opp-5000000 {
opp-hz = /bits/ 64 <134000000>; opp-hz = /bits/ 64 <5000000>;
}; };
opp-160000000 { opp-100000000 {
opp-hz = /bits/ 64 <160000000>; opp-hz = /bits/ 64 <100000000>;
}; };
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
}; };
};
bus_peri_opp_table: opp_table3 { bus_fsys_opp_table: opp_table4 {
compatible = "operating-points-v2"; compatible = "operating-points-v2";
opp-shared; opp-shared;
opp-5000000 { opp-10000000 {
opp-hz = /bits/ 64 <5000000>; opp-hz = /bits/ 64 <10000000>;
}; };
opp-100000000 { opp-134000000 {
opp-hz = /bits/ 64 <100000000>; opp-hz = /bits/ 64 <134000000>;
};
}; };
};
bus_fsys_opp_table: opp_table4 { bus_display_opp_table: opp_table5 {
compatible = "operating-points-v2"; compatible = "operating-points-v2";
opp-shared; opp-shared;
opp-10000000 { opp-100000000 {
opp-hz = /bits/ 64 <10000000>; opp-hz = /bits/ 64 <100000000>;
}; };
opp-134000000 { opp-134000000 {
opp-hz = /bits/ 64 <134000000>; opp-hz = /bits/ 64 <134000000>;
};
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
};
}; };
};
bus_display_opp_table: opp_table5 { bus_leftbus_opp_table: opp_table6 {
compatible = "operating-points-v2"; compatible = "operating-points-v2";
opp-shared; opp-shared;
opp-100000000 { opp-100000000 {
opp-hz = /bits/ 64 <100000000>; opp-hz = /bits/ 64 <100000000>;
}; };
opp-134000000 { opp-160000000 {
opp-hz = /bits/ 64 <134000000>; opp-hz = /bits/ 64 <160000000>;
}; };
opp-160000000 { opp-200000000 {
opp-hz = /bits/ 64 <160000000>; opp-hz = /bits/ 64 <200000000>;
};
}; };
}; };
bus_leftbus_opp_table: opp_table6 { thermal-zones {
compatible = "operating-points-v2"; cpu_thermal: cpu-thermal {
opp-shared; polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tmu 0>;
opp-100000000 { trips {
opp-hz = /bits/ 64 <100000000>; cpu_alert0: cpu-alert-0 {
}; temperature = <85000>; /* millicelsius */
opp-160000000 { };
opp-hz = /bits/ 64 <160000000>; cpu_alert1: cpu-alert-1 {
}; temperature = <100000>; /* millicelsius */
opp-200000000 { };
opp-hz = /bits/ 64 <200000000>; cpu_alert2: cpu-alert-2 {
temperature = <110000>; /* millicelsius */
};
};
}; };
}; };
}; };
......
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