Commit 9a95b370 authored by Stanislaw Gruszka's avatar Stanislaw Gruszka

iwlegacy: use FH49_ prefix in 4965 code

Signed-off-by: default avatarStanislaw Gruszka <sgruszka@redhat.com>
parent 53143a18
...@@ -138,22 +138,22 @@ int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq) ...@@ -138,22 +138,22 @@ int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
u32 rb_timeout = 0; u32 rb_timeout = 0;
if (il->cfg->mod_params->amsdu_size_8K) if (il->cfg->mod_params->amsdu_size_8K)
rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
else else
rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
/* Stop Rx DMA */ /* Stop Rx DMA */
il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
/* Reset driver's Rx queue write idx */ /* Reset driver's Rx queue write idx */
il_wr(il, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
/* Tell device where to find RBD circular buffer in DRAM */ /* Tell device where to find RBD circular buffer in DRAM */
il_wr(il, FH_RSCSR_CHNL0_RBDCB_BASE_REG, il_wr(il, FH49_RSCSR_CHNL0_RBDCB_BASE_REG,
(u32)(rxq->bd_dma >> 8)); (u32)(rxq->bd_dma >> 8));
/* Tell device where in DRAM to update its Rx status */ /* Tell device where in DRAM to update its Rx status */
il_wr(il, FH_RSCSR_CHNL0_STTS_WPTR_REG, il_wr(il, FH49_RSCSR_CHNL0_STTS_WPTR_REG,
rxq->rb_stts_dma >> 4); rxq->rb_stts_dma >> 4);
/* Enable Rx DMA /* Enable Rx DMA
...@@ -162,13 +162,13 @@ int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq) ...@@ -162,13 +162,13 @@ int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
* RB timeout 0x10 * RB timeout 0x10
* 256 RBDs * 256 RBDs
*/ */
il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG,
FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK | FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
rb_size| rb_size|
(rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)| (rb_timeout << FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
(rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); (rfdnlog << FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
/* Set interrupt coalescing timer to default (2048 usecs) */ /* Set interrupt coalescing timer to default (2048 usecs) */
il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF); il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF);
...@@ -443,9 +443,9 @@ int il4965_rxq_stop(struct il_priv *il) ...@@ -443,9 +443,9 @@ int il4965_rxq_stop(struct il_priv *il)
{ {
/* stop Rx DMA */ /* stop Rx DMA */
il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
il_poll_bit(il, FH_MEM_RSSR_RX_STATUS_REG, il_poll_bit(il, FH49_MEM_RSSR_RX_STATUS_REG,
FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
return 0; return 0;
} }
...@@ -1180,15 +1180,15 @@ u8 il4965_toggle_tx_ant(struct il_priv *il, u8 ant, u8 valid) ...@@ -1180,15 +1180,15 @@ u8 il4965_toggle_tx_ant(struct il_priv *il, u8 ant, u8 valid)
static const char *il4965_get_fh_string(int cmd) static const char *il4965_get_fh_string(int cmd)
{ {
switch (cmd) { switch (cmd) {
IL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG); IL_CMD(FH49_RSCSR_CHNL0_STTS_WPTR_REG);
IL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG); IL_CMD(FH49_RSCSR_CHNL0_RBDCB_BASE_REG);
IL_CMD(FH_RSCSR_CHNL0_WPTR); IL_CMD(FH49_RSCSR_CHNL0_WPTR);
IL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG); IL_CMD(FH49_MEM_RCSR_CHNL0_CONFIG_REG);
IL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG); IL_CMD(FH49_MEM_RSSR_SHARED_CTRL_REG);
IL_CMD(FH_MEM_RSSR_RX_STATUS_REG); IL_CMD(FH49_MEM_RSSR_RX_STATUS_REG);
IL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV); IL_CMD(FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
IL_CMD(FH_TSSR_TX_STATUS_REG); IL_CMD(FH49_TSSR_TX_STATUS_REG);
IL_CMD(FH_TSSR_TX_ERROR_REG); IL_CMD(FH49_TSSR_TX_ERROR_REG);
default: default:
return "UNKNOWN"; return "UNKNOWN";
} }
...@@ -1202,15 +1202,15 @@ int il4965_dump_fh(struct il_priv *il, char **buf, bool display) ...@@ -1202,15 +1202,15 @@ int il4965_dump_fh(struct il_priv *il, char **buf, bool display)
size_t bufsz = 0; size_t bufsz = 0;
#endif #endif
static const u32 fh_tbl[] = { static const u32 fh_tbl[] = {
FH_RSCSR_CHNL0_STTS_WPTR_REG, FH49_RSCSR_CHNL0_STTS_WPTR_REG,
FH_RSCSR_CHNL0_RBDCB_BASE_REG, FH49_RSCSR_CHNL0_RBDCB_BASE_REG,
FH_RSCSR_CHNL0_WPTR, FH49_RSCSR_CHNL0_WPTR,
FH_MEM_RCSR_CHNL0_CONFIG_REG, FH49_MEM_RCSR_CHNL0_CONFIG_REG,
FH_MEM_RSSR_SHARED_CTRL_REG, FH49_MEM_RSSR_SHARED_CTRL_REG,
FH_MEM_RSSR_RX_STATUS_REG, FH49_MEM_RSSR_RX_STATUS_REG,
FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV, FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
FH_TSSR_TX_STATUS_REG, FH49_TSSR_TX_STATUS_REG,
FH_TSSR_TX_ERROR_REG FH49_TSSR_TX_ERROR_REG
}; };
#ifdef CONFIG_IWLEGACY_DEBUG #ifdef CONFIG_IWLEGACY_DEBUG
if (display) { if (display) {
...@@ -2010,7 +2010,7 @@ int il4965_txq_ctx_alloc(struct il_priv *il) ...@@ -2010,7 +2010,7 @@ int il4965_txq_ctx_alloc(struct il_priv *il)
il4965_txq_set_sched(il, 0); il4965_txq_set_sched(il, 0);
/* Tell NIC where to find the "keep warm" buffer */ /* Tell NIC where to find the "keep warm" buffer */
il_wr(il, FH_KW_MEM_ADDR_REG, il->kw.dma >> 4); il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
spin_unlock_irqrestore(&il->lock, flags); spin_unlock_irqrestore(&il->lock, flags);
...@@ -2049,7 +2049,7 @@ void il4965_txq_ctx_reset(struct il_priv *il) ...@@ -2049,7 +2049,7 @@ void il4965_txq_ctx_reset(struct il_priv *il)
il4965_txq_set_sched(il, 0); il4965_txq_set_sched(il, 0);
/* Tell NIC where to find the "keep warm" buffer */ /* Tell NIC where to find the "keep warm" buffer */
il_wr(il, FH_KW_MEM_ADDR_REG, il->kw.dma >> 4); il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
spin_unlock_irqrestore(&il->lock, flags); spin_unlock_irqrestore(&il->lock, flags);
...@@ -2078,14 +2078,14 @@ void il4965_txq_ctx_stop(struct il_priv *il) ...@@ -2078,14 +2078,14 @@ void il4965_txq_ctx_stop(struct il_priv *il)
/* Stop each Tx DMA channel, and wait for it to be idle */ /* Stop each Tx DMA channel, and wait for it to be idle */
for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) { for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) {
il_wr(il, il_wr(il,
FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
if (il_poll_bit(il, FH_TSSR_TX_STATUS_REG, if (il_poll_bit(il, FH49_TSSR_TX_STATUS_REG,
FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
1000)) 1000))
IL_ERR("Failing on timeout while stopping" IL_ERR("Failing on timeout while stopping"
" DMA channel %d [0x%08x]", ch, " DMA channel %d [0x%08x]", ch,
il_rd(il, il_rd(il,
FH_TSSR_TX_STATUS_REG)); FH49_TSSR_TX_STATUS_REG));
} }
spin_unlock_irqrestore(&il->lock, flags); spin_unlock_irqrestore(&il->lock, flags);
...@@ -3743,7 +3743,7 @@ int il4965_hw_tx_queue_init(struct il_priv *il, ...@@ -3743,7 +3743,7 @@ int il4965_hw_tx_queue_init(struct il_priv *il,
int txq_id = txq->q.id; int txq_id = txq->q.id;
/* Circular buffer (TFD queue in DRAM) physical base address */ /* Circular buffer (TFD queue in DRAM) physical base address */
il_wr(il, FH_MEM_CBBC_QUEUE(txq_id), il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id),
txq->q.dma_addr >> 8); txq->q.dma_addr >> 8);
return 0; return 0;
...@@ -4262,7 +4262,7 @@ static void il4965_irq_tasklet(struct il_priv *il) ...@@ -4262,7 +4262,7 @@ static void il4965_irq_tasklet(struct il_priv *il)
if (inta & ~(il->inta_mask)) { if (inta & ~(il->inta_mask)) {
IL_WARN("Disabled INTA bits 0x%08x were pending\n", IL_WARN("Disabled INTA bits 0x%08x were pending\n",
inta & ~il->inta_mask); inta & ~il->inta_mask);
IL_WARN(" with FH_INT = 0x%08x\n", inta_fh); IL_WARN(" with FH49_INT = 0x%08x\n", inta_fh);
} }
/* Re-enable all interrupts */ /* Re-enable all interrupts */
...@@ -4798,7 +4798,7 @@ static const char * const desc_lookup_text[] = { ...@@ -4798,7 +4798,7 @@ static const char * const desc_lookup_text[] = {
"HW_ERROR_TEMPERATURE", "HW_ERROR_TEMPERATURE",
"ILLEGAL_CHAN_FREQ", "ILLEGAL_CHAN_FREQ",
"VCC_NOT_STBL", "VCC_NOT_STBL",
"FH_ERROR", "FH49_ERROR",
"NMI_INTERRUPT_HOST", "NMI_INTERRUPT_HOST",
"NMI_INTERRUPT_ACTION_PT", "NMI_INTERRUPT_ACTION_PT",
"NMI_INTERRUPT_UNKNOWN", "NMI_INTERRUPT_UNKNOWN",
...@@ -4969,14 +4969,14 @@ static int il4965_alive_notify(struct il_priv *il) ...@@ -4969,14 +4969,14 @@ static int il4965_alive_notify(struct il_priv *il)
/* Enable DMA channel */ /* Enable DMA channel */
for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++) for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
il_wr(il, il_wr(il,
FH_TCSR_CHNL_TX_CONFIG_REG(chan), FH49_TCSR_CHNL_TX_CONFIG_REG(chan),
FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
/* Update FH chicken bits */ /* Update FH chicken bits */
reg_val = il_rd(il, FH_TX_CHICKEN_BITS_REG); reg_val = il_rd(il, FH49_TX_CHICKEN_BITS_REG);
il_wr(il, FH_TX_CHICKEN_BITS_REG, il_wr(il, FH49_TX_CHICKEN_BITS_REG,
reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); reg_val | FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
/* Disable chain mode for all queues */ /* Disable chain mode for all queues */
il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0); il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0);
......
...@@ -630,7 +630,7 @@ static int il4965_hw_set_hw_params(struct il_priv *il) ...@@ -630,7 +630,7 @@ static int il4965_hw_set_hw_params(struct il_priv *il)
il->hw_params.max_bsm_size = BSM_SRAM_SIZE; il->hw_params.max_bsm_size = BSM_SRAM_SIZE;
il->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ); il->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ);
il->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR; il->hw_params.rx_wrt_ptr_reg = FH49_RSCSR_CHNL0_WPTR;
il->hw_params.tx_chains_num = il4965_num_of_ant(il->cfg->valid_tx_ant); il->hw_params.tx_chains_num = il4965_num_of_ant(il->cfg->valid_tx_ant);
il->hw_params.rx_chains_num = il4965_num_of_ant(il->cfg->valid_rx_ant); il->hw_params.rx_chains_num = il4965_num_of_ant(il->cfg->valid_rx_ant);
......
...@@ -2835,7 +2835,7 @@ struct il_tfd_tb { ...@@ -2835,7 +2835,7 @@ struct il_tfd_tb {
* contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
* *
* Driver must indicate the physical address of the base of each * Driver must indicate the physical address of the base of each
* circular buffer via the FH_MEM_CBBC_QUEUE registers. * circular buffer via the FH49_MEM_CBBC_QUEUE registers.
* *
* Each TFD contains pointer/size information for up to 20 data buffers * Each TFD contains pointer/size information for up to 20 data buffers
* in host DRAM. These buffers collectively contain the (one) frame described * in host DRAM. These buffers collectively contain the (one) frame described
......
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