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Commit 9b63dd17 authored by Paul Mackerras's avatar Paul Mackerras Committed by Linus Torvalds
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[PATCH] Clean up head.S whitespace 

The whitespace in arch/ppc64/kernel/head.S is a bit all over the place. 
This patch fixes it up.  This patch changes nothing other than
whitespace. 
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 59f87247
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Showing with 241 additions and 241 deletions
arch/ppc64/kernel/head.S
View file @ 9b63dd17
...@@ -44,8 +44,8 @@ ...@@ -44,8 +44,8 @@
/* /*
* hcall interface to pSeries LPAR * hcall interface to pSeries LPAR
*/ */
#define HVSC .long 0x44000022 #define HVSC .long 0x44000022
#define H_SET_ASR 0x30 #define H_SET_ASR 0x30
/* /*
* We layout physical memory as follows: * We layout physical memory as follows:
...@@ -54,19 +54,19 @@ ...@@ -54,19 +54,19 @@
* 0x3000 - 0x3fff : Interrupt support * 0x3000 - 0x3fff : Interrupt support
* 0x4000 - 0x4fff : NACA * 0x4000 - 0x4fff : NACA
* 0x5000 - 0x5fff : SystemCfg * 0x5000 - 0x5fff : SystemCfg
* 0x6000 : iSeries and common interrupt prologs * 0x6000 : iSeries and common interrupt prologs
* 0x9000 - 0x9fff : Initial segment table * 0x9000 - 0x9fff : Initial segment table
*/ */
/* /*
* SPRG Usage * SPRG Usage
* *
* Register Definition * Register Definition
* *
* SPRG0 reserved for hypervisor * SPRG0 reserved for hypervisor
* SPRG1 temp - used to save gpr * SPRG1 temp - used to save gpr
* SPRG2 temp - used to save gpr * SPRG2 temp - used to save gpr
* SPRG3 virt addr of paca * SPRG3 virt addr of paca
*/ */
/* /*
...@@ -107,7 +107,7 @@ END_FTR_SECTION(0, 1) ...@@ -107,7 +107,7 @@ END_FTR_SECTION(0, 1)
* to the pidhash table (also used by the debugger) * to the pidhash table (also used by the debugger)
*/ */
.llong msChunks-KERNELBASE .llong msChunks-KERNELBASE
.llong 0 /* pidhash-KERNELBASE SFRXXX */ .llong 0 /* pidhash-KERNELBASE SFRXXX */
/* Offset 0x38 - Pointer to start of embedded System.map */ /* Offset 0x38 - Pointer to start of embedded System.map */
.globl embedded_sysmap_start .globl embedded_sysmap_start
...@@ -122,13 +122,13 @@ embedded_sysmap_end: ...@@ -122,13 +122,13 @@ embedded_sysmap_end:
/* Secondary processors spin on this value until it goes to 1. */ /* Secondary processors spin on this value until it goes to 1. */
.globl __secondary_hold_spinloop .globl __secondary_hold_spinloop
__secondary_hold_spinloop: __secondary_hold_spinloop:
.llong 0x0 .llong 0x0
/* Secondary processors write this value with their cpu # */ /* Secondary processors write this value with their cpu # */
/* after they enter the spin loop immediately below. */ /* after they enter the spin loop immediately below. */
.globl __secondary_hold_acknowledge .globl __secondary_hold_acknowledge
__secondary_hold_acknowledge: __secondary_hold_acknowledge:
.llong 0x0 .llong 0x0
. = 0x60 . = 0x60
/* /*
...@@ -144,25 +144,25 @@ _GLOBAL(__secondary_hold) ...@@ -144,25 +144,25 @@ _GLOBAL(__secondary_hold)
mtmsrd r24 /* RI on */ mtmsrd r24 /* RI on */
/* Grab our linux cpu number */ /* Grab our linux cpu number */
mr r24,r3 mr r24,r3
/* Tell the master cpu we're here */ /* Tell the master cpu we're here */
/* Relocation is off & we are located at an address less */ /* Relocation is off & we are located at an address less */
/* than 0x100, so only need to grab low order offset. */ /* than 0x100, so only need to grab low order offset. */
std r24,__secondary_hold_acknowledge@l(0) std r24,__secondary_hold_acknowledge@l(0)
sync sync
/* All secondary cpu's wait here until told to start. */ /* All secondary cpu's wait here until told to start. */
100: ld r4,__secondary_hold_spinloop@l(0) 100: ld r4,__secondary_hold_spinloop@l(0)
cmpdi 0,r4,1 cmpdi 0,r4,1
bne 100b bne 100b
#ifdef CONFIG_HMT #ifdef CONFIG_HMT
b .hmt_init b .hmt_init
#else #else
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
mr r3,r24 mr r3,r24
b .pseries_secondary_smp_init b .pseries_secondary_smp_init
#else #else
BUG_OPCODE BUG_OPCODE
#endif #endif
...@@ -201,7 +201,7 @@ exception_marker: ...@@ -201,7 +201,7 @@ exception_marker:
#define EX_SRR0 40 #define EX_SRR0 40
#define EX_DAR 48 #define EX_DAR 48
#define EX_DSISR 56 #define EX_DSISR 56
#define EX_CCR 60 #define EX_CCR 60
#define EXCEPTION_PROLOG_PSERIES(area, label) \ #define EXCEPTION_PROLOG_PSERIES(area, label) \
mfspr r13,SPRG3; /* get paca address into r13 */ \ mfspr r13,SPRG3; /* get paca address into r13 */ \
...@@ -256,10 +256,10 @@ exception_marker: ...@@ -256,10 +256,10 @@ exception_marker:
#define EXCEPTION_PROLOG_COMMON(n, area) \ #define EXCEPTION_PROLOG_COMMON(n, area) \
andi. r10,r12,MSR_PR; /* See if coming from user */ \ andi. r10,r12,MSR_PR; /* See if coming from user */ \
mr r10,r1; /* Save r1 */ \ mr r10,r1; /* Save r1 */ \
subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
beq- 1f; \ beq- 1f; \
ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \ 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
bge- cr1,bad_stack; /* abort if it is */ \ bge- cr1,bad_stack; /* abort if it is */ \
std r9,_CCR(r1); /* save CR in stackframe */ \ std r9,_CCR(r1); /* save CR in stackframe */ \
std r11,_NIP(r1); /* save SRR0 in stackframe */ \ std r11,_NIP(r1); /* save SRR0 in stackframe */ \
...@@ -297,7 +297,7 @@ exception_marker: ...@@ -297,7 +297,7 @@ exception_marker:
/* /*
* Exception vectors. * Exception vectors.
*/ */
#define STD_EXCEPTION_PSERIES(n, label ) \ #define STD_EXCEPTION_PSERIES(n, label) \
. = n; \ . = n; \
.globl label##_Pseries; \ .globl label##_Pseries; \
label##_Pseries: \ label##_Pseries: \
...@@ -312,7 +312,7 @@ label##_Iseries: \ ...@@ -312,7 +312,7 @@ label##_Iseries: \
EXCEPTION_PROLOG_ISERIES_2; \ EXCEPTION_PROLOG_ISERIES_2; \
b label##_common b label##_common
#define MASKABLE_EXCEPTION_ISERIES( n, label ) \ #define MASKABLE_EXCEPTION_ISERIES(n, label) \
.globl label##_Iseries; \ .globl label##_Iseries; \
label##_Iseries: \ label##_Iseries: \
mtspr SPRG1,r13; /* save r13 */ \ mtspr SPRG1,r13; /* save r13 */ \
...@@ -376,7 +376,7 @@ label##_Iseries_profile: \ ...@@ -376,7 +376,7 @@ label##_Iseries_profile: \
#endif #endif
#define STD_EXCEPTION_COMMON( trap, label, hdlr ) \ #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
.align 7; \ .align 7; \
.globl label##_common; \ .globl label##_common; \
label##_common: \ label##_common: \
...@@ -384,8 +384,8 @@ label##_common: \ ...@@ -384,8 +384,8 @@ label##_common: \
DISABLE_INTS; \ DISABLE_INTS; \
bl .save_nvgprs; \ bl .save_nvgprs; \
addi r3,r1,STACK_FRAME_OVERHEAD; \ addi r3,r1,STACK_FRAME_OVERHEAD; \
bl hdlr; \ bl hdlr; \
b .ret_from_except b .ret_from_except
#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \ #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
.align 7; \ .align 7; \
...@@ -404,7 +404,7 @@ label##_common: \ ...@@ -404,7 +404,7 @@ label##_common: \
.globl __start_interrupts .globl __start_interrupts
__start_interrupts: __start_interrupts:
STD_EXCEPTION_PSERIES( 0x100, SystemReset ) STD_EXCEPTION_PSERIES(0x100, SystemReset)
. = 0x200 . = 0x200
.globl MachineCheck_Pseries .globl MachineCheck_Pseries
...@@ -444,15 +444,15 @@ DataAccessSLB_Pseries: ...@@ -444,15 +444,15 @@ DataAccessSLB_Pseries:
mfspr r12,SPRG2 mfspr r12,SPRG2
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, DataAccessSLB_common) EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, DataAccessSLB_common)
STD_EXCEPTION_PSERIES( 0x400, InstructionAccess ) STD_EXCEPTION_PSERIES(0x400, InstructionAccess)
STD_EXCEPTION_PSERIES( 0x480, InstructionAccessSLB ) STD_EXCEPTION_PSERIES(0x480, InstructionAccessSLB)
STD_EXCEPTION_PSERIES( 0x500, HardwareInterrupt ) STD_EXCEPTION_PSERIES(0x500, HardwareInterrupt)
STD_EXCEPTION_PSERIES( 0x600, Alignment ) STD_EXCEPTION_PSERIES(0x600, Alignment)
STD_EXCEPTION_PSERIES( 0x700, ProgramCheck ) STD_EXCEPTION_PSERIES(0x700, ProgramCheck)
STD_EXCEPTION_PSERIES( 0x800, FPUnavailable ) STD_EXCEPTION_PSERIES(0x800, FPUnavailable)
STD_EXCEPTION_PSERIES( 0x900, Decrementer ) STD_EXCEPTION_PSERIES(0x900, Decrementer)
STD_EXCEPTION_PSERIES( 0xa00, Trap_0a ) STD_EXCEPTION_PSERIES(0xa00, Trap_0a)
STD_EXCEPTION_PSERIES( 0xb00, Trap_0b ) STD_EXCEPTION_PSERIES(0xb00, Trap_0b)
. = 0xc00 . = 0xc00
.globl SystemCall_Pseries .globl SystemCall_Pseries
...@@ -470,8 +470,8 @@ SystemCall_Pseries: ...@@ -470,8 +470,8 @@ SystemCall_Pseries:
mtspr SRR1,r10 mtspr SRR1,r10
rfid rfid
STD_EXCEPTION_PSERIES( 0xd00, SingleStep ) STD_EXCEPTION_PSERIES(0xd00, SingleStep)
STD_EXCEPTION_PSERIES( 0xe00, Trap_0e ) STD_EXCEPTION_PSERIES(0xe00, Trap_0e)
/* We need to deal with the Altivec unavailable exception /* We need to deal with the Altivec unavailable exception
* here which is at 0xf20, thus in the middle of the * here which is at 0xf20, thus in the middle of the
...@@ -483,12 +483,12 @@ SystemCall_Pseries: ...@@ -483,12 +483,12 @@ SystemCall_Pseries:
STD_EXCEPTION_PSERIES(0xf20, AltivecUnavailable) STD_EXCEPTION_PSERIES(0xf20, AltivecUnavailable)
STD_EXCEPTION_PSERIES( 0x1300, InstructionBreakpoint ) STD_EXCEPTION_PSERIES(0x1300, InstructionBreakpoint)
STD_EXCEPTION_PSERIES( 0x1700, AltivecAssist ) STD_EXCEPTION_PSERIES(0x1700, AltivecAssist)
/* moved from 0xf00 */ /* moved from 0xf00 */
STD_EXCEPTION_PSERIES(0x3000, PerformanceMonitor) STD_EXCEPTION_PSERIES(0x3000, PerformanceMonitor)
. = 0x3100 . = 0x3100
_GLOBAL(do_stab_bolted_Pseries) _GLOBAL(do_stab_bolted_Pseries)
mtcrf 0x80,r12 mtcrf 0x80,r12
...@@ -499,8 +499,8 @@ _GLOBAL(do_slb_bolted_Pseries) ...@@ -499,8 +499,8 @@ _GLOBAL(do_slb_bolted_Pseries)
mtcrf 0x80,r12 mtcrf 0x80,r12
mfspr r12,SPRG2 mfspr r12,SPRG2
EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_slb_bolted) EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_slb_bolted)
/* Space for the naca. Architected to be located at real address /* Space for the naca. Architected to be located at real address
* NACA_PHYS_ADDR. Various tools rely on this location being fixed. * NACA_PHYS_ADDR. Various tools rely on this location being fixed.
* The first dword of the naca is required by iSeries LPAR to * The first dword of the naca is required by iSeries LPAR to
...@@ -539,16 +539,16 @@ __end_systemcfg: ...@@ -539,16 +539,16 @@ __end_systemcfg:
* VSID generation algorithm. See include/asm/mmu_context.h. * VSID generation algorithm. See include/asm/mmu_context.h.
*/ */
.llong 1 /* # ESIDs to be mapped by hypervisor */ .llong 1 /* # ESIDs to be mapped by hypervisor */
.llong 1 /* # memory ranges to be mapped by hypervisor */ .llong 1 /* # memory ranges to be mapped by hypervisor */
.llong STAB0_PAGE /* Page # of segment table within load area */ .llong STAB0_PAGE /* Page # of segment table within load area */
.llong 0 /* Reserved */
.llong 0 /* Reserved */
.llong 0 /* Reserved */ .llong 0 /* Reserved */
.llong 0 /* Reserved */
.llong 0 /* Reserved */
.llong 0 /* Reserved */ .llong 0 /* Reserved */
.llong 0 /* Reserved */ .llong 0 /* Reserved */
.llong 0x0c00000000 /* ESID to map (Kernel at EA = 0xC000000000000000) */ .llong 0x0c00000000 /* ESID to map (Kernel at EA = 0xC000000000000000) */
.llong 0x06a99b4b14 /* VSID to map (Kernel at VA = 0x6a99b4b140000000) */ .llong 0x06a99b4b14 /* VSID to map (Kernel at VA = 0x6a99b4b140000000) */
.llong 8192 /* # pages to map (32 MB) */ .llong 8192 /* # pages to map (32 MB) */
.llong 0 /* Offset from start of loadarea to start of map */ .llong 0 /* Offset from start of loadarea to start of map */
.llong 0x0006a99b4b140000 /* VPN of first page to map */ .llong 0x0006a99b4b140000 /* VPN of first page to map */
...@@ -663,7 +663,7 @@ iseries_secondary_smp_loop: ...@@ -663,7 +663,7 @@ iseries_secondary_smp_loop:
rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */ rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
#else /* CONFIG_SMP */ #else /* CONFIG_SMP */
/* Yield the processor. This is required for non-SMP kernels /* Yield the processor. This is required for non-SMP kernels
which are running on multi-threaded machines. */ which are running on multi-threaded machines. */
lis r3,0x8000 lis r3,0x8000
rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */ rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */ addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
...@@ -702,7 +702,7 @@ HardwareInterrupt_Iseries_masked: ...@@ -702,7 +702,7 @@ HardwareInterrupt_Iseries_masked:
/* /*
* Data area reserved for FWNMI option. * Data area reserved for FWNMI option.
*/ */
.= 0x7000 .= 0x7000
.globl fwnmi_data_area .globl fwnmi_data_area
fwnmi_data_area: fwnmi_data_area:
...@@ -735,7 +735,7 @@ __end_stab: ...@@ -735,7 +735,7 @@ __end_stab:
/*** Common interrupt handlers ***/ /*** Common interrupt handlers ***/
STD_EXCEPTION_COMMON( 0x100, SystemReset, .SystemResetException ) STD_EXCEPTION_COMMON(0x100, SystemReset, .SystemResetException)
/* /*
* Machine check is different because we use a different * Machine check is different because we use a different
...@@ -752,16 +752,16 @@ MachineCheck_common: ...@@ -752,16 +752,16 @@ MachineCheck_common:
b .ret_from_except b .ret_from_except
STD_EXCEPTION_COMMON_LITE(0x900, Decrementer, .timer_interrupt) STD_EXCEPTION_COMMON_LITE(0x900, Decrementer, .timer_interrupt)
STD_EXCEPTION_COMMON( 0xa00, Trap_0a, .UnknownException ) STD_EXCEPTION_COMMON(0xa00, Trap_0a, .UnknownException)
STD_EXCEPTION_COMMON( 0xb00, Trap_0b, .UnknownException ) STD_EXCEPTION_COMMON(0xb00, Trap_0b, .UnknownException)
STD_EXCEPTION_COMMON( 0xd00, SingleStep, .SingleStepException ) STD_EXCEPTION_COMMON(0xd00, SingleStep, .SingleStepException)
STD_EXCEPTION_COMMON( 0xe00, Trap_0e, .UnknownException ) STD_EXCEPTION_COMMON(0xe00, Trap_0e, .UnknownException)
STD_EXCEPTION_COMMON( 0xf00, PerformanceMonitor, .PerformanceMonitorException ) STD_EXCEPTION_COMMON(0xf00, PerformanceMonitor, .PerformanceMonitorException)
STD_EXCEPTION_COMMON(0x1300, InstructionBreakpoint, .InstructionBreakpointException ) STD_EXCEPTION_COMMON(0x1300, InstructionBreakpoint, .InstructionBreakpointException)
#ifdef CONFIG_ALTIVEC #ifdef CONFIG_ALTIVEC
STD_EXCEPTION_COMMON(0x1700, AltivecAssist, .AltivecAssistException ) STD_EXCEPTION_COMMON(0x1700, AltivecAssist, .AltivecAssistException)
#else #else
STD_EXCEPTION_COMMON(0x1700, AltivecAssist, .UnknownException ) STD_EXCEPTION_COMMON(0x1700, AltivecAssist, .UnknownException)
#endif #endif
/* /*
...@@ -788,7 +788,7 @@ bad_stack: ...@@ -788,7 +788,7 @@ bad_stack:
std r10,_LINK(r1) std r10,_LINK(r1)
std r11,_CTR(r1) std r11,_CTR(r1)
std r12,_XER(r1) std r12,_XER(r1)
SAVE_GPR(0, r1) SAVE_GPR(0,r1)
SAVE_GPR(2,r1) SAVE_GPR(2,r1)
SAVE_4GPRS(3,r1) SAVE_4GPRS(3,r1)
SAVE_2GPRS(7,r1) SAVE_2GPRS(7,r1)
...@@ -816,13 +816,13 @@ fast_exception_return: ...@@ -816,13 +816,13 @@ fast_exception_return:
ld r11,_NIP(r1) ld r11,_NIP(r1)
andi. r3,r12,MSR_RI /* check if RI is set */ andi. r3,r12,MSR_RI /* check if RI is set */
beq- unrecov_fer beq- unrecov_fer
ld r3,_CCR(r1) ld r3,_CCR(r1)
ld r4,_LINK(r1) ld r4,_LINK(r1)
ld r5,_CTR(r1) ld r5,_CTR(r1)
ld r6,_XER(r1) ld r6,_XER(r1)
mtcr r3 mtcr r3
mtlr r4 mtlr r4
mtctr r5 mtctr r5
mtxer r6 mtxer r6
REST_GPR(0, r1) REST_GPR(0, r1)
REST_8GPRS(2, r1) REST_8GPRS(2, r1)
...@@ -834,7 +834,7 @@ fast_exception_return: ...@@ -834,7 +834,7 @@ fast_exception_return:
mtspr SRR1,r12 mtspr SRR1,r12
mtspr SRR0,r11 mtspr SRR0,r11
REST_4GPRS(10, r1) REST_4GPRS(10, r1)
ld r1,GPR1(r1) ld r1,GPR1(r1)
rfid rfid
unrecov_fer: unrecov_fer:
...@@ -871,7 +871,7 @@ DataAccessSLB_common: ...@@ -871,7 +871,7 @@ DataAccessSLB_common:
std r3,_DAR(r1) std r3,_DAR(r1)
bl .slb_allocate bl .slb_allocate
cmpdi r3,0 /* Check return code */ cmpdi r3,0 /* Check return code */
beq fast_exception_return /* Return if we succeeded */ beq fast_exception_return /* Return if we succeeded */
li r5,0 li r5,0
std r5,_DSISR(r1) std r5,_DSISR(r1)
b .handle_page_fault b .handle_page_fault
...@@ -892,7 +892,7 @@ InstructionAccessSLB_common: ...@@ -892,7 +892,7 @@ InstructionAccessSLB_common:
ld r3,_NIP(r1) /* SRR0 = NIA */ ld r3,_NIP(r1) /* SRR0 = NIA */
bl .slb_allocate bl .slb_allocate
or. r3,r3,r3 /* Check return code */ or. r3,r3,r3 /* Check return code */
beq+ fast_exception_return /* Return if we succeeded */ beq+ fast_exception_return /* Return if we succeeded */
ld r4,_NIP(r1) ld r4,_NIP(r1)
li r5,0 li r5,0
...@@ -908,7 +908,7 @@ HardwareInterrupt_common: ...@@ -908,7 +908,7 @@ HardwareInterrupt_common:
HardwareInterrupt_entry: HardwareInterrupt_entry:
DISABLE_INTS DISABLE_INTS
addi r3,r1,STACK_FRAME_OVERHEAD addi r3,r1,STACK_FRAME_OVERHEAD
bl .do_IRQ bl .do_IRQ
b .ret_from_except_lite b .ret_from_except_lite
.align 7 .align 7
...@@ -926,8 +926,8 @@ Alignment_common: ...@@ -926,8 +926,8 @@ Alignment_common:
bl .save_nvgprs bl .save_nvgprs
addi r3,r1,STACK_FRAME_OVERHEAD addi r3,r1,STACK_FRAME_OVERHEAD
ENABLE_INTS ENABLE_INTS
bl .AlignmentException bl .AlignmentException
b .ret_from_except b .ret_from_except
.align 7 .align 7
.globl ProgramCheck_common .globl ProgramCheck_common
...@@ -936,8 +936,8 @@ ProgramCheck_common: ...@@ -936,8 +936,8 @@ ProgramCheck_common:
bl .save_nvgprs bl .save_nvgprs
addi r3,r1,STACK_FRAME_OVERHEAD addi r3,r1,STACK_FRAME_OVERHEAD
ENABLE_INTS ENABLE_INTS
bl .ProgramCheckException bl .ProgramCheckException
b .ret_from_except b .ret_from_except
.align 7 .align 7
.globl FPUnavailable_common .globl FPUnavailable_common
...@@ -947,7 +947,7 @@ FPUnavailable_common: ...@@ -947,7 +947,7 @@ FPUnavailable_common:
bl .save_nvgprs bl .save_nvgprs
addi r3,r1,STACK_FRAME_OVERHEAD addi r3,r1,STACK_FRAME_OVERHEAD
ENABLE_INTS ENABLE_INTS
bl .KernelFPUnavailableException bl .KernelFPUnavailableException
BUG_OPCODE BUG_OPCODE
.align 7 .align 7
...@@ -962,7 +962,7 @@ AltivecUnavailable_common: ...@@ -962,7 +962,7 @@ AltivecUnavailable_common:
ENABLE_INTS ENABLE_INTS
bl .AltivecUnavailableException bl .AltivecUnavailableException
b .ret_from_except b .ret_from_except
/* /*
* Hash table stuff * Hash table stuff
*/ */
...@@ -1092,19 +1092,19 @@ _GLOBAL(do_stab_bolted) ...@@ -1092,19 +1092,19 @@ _GLOBAL(do_stab_bolted)
andi. r11,r10,0x70 andi. r11,r10,0x70
bne 1b bne 1b
/* Stick for only searching the primary group for now. */ /* Stick for only searching the primary group for now. */
/* At least for now, we use a very simple random castout scheme */ /* At least for now, we use a very simple random castout scheme */
/* Use the TB as a random number ; OR in 1 to avoid entry 0 */ /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
mftb r11 mftb r11
rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
ori r11,r11,0x10 ori r11,r11,0x10
/* r10 currently points to an ste one past the group of interest */ /* r10 currently points to an ste one past the group of interest */
/* make it point to the randomly selected entry */ /* make it point to the randomly selected entry */
subi r10,r10,128 subi r10,r10,128
or r10,r10,r11 /* r10 is the entry to invalidate */ or r10,r10,r11 /* r10 is the entry to invalidate */
isync /* mark the entry invalid */ isync /* mark the entry invalid */
ld r11,0(r10) ld r11,0(r10)
rldicl r11,r11,56,1 /* clear the valid bit */ rldicl r11,r11,56,1 /* clear the valid bit */
rotldi r11,r11,8 rotldi r11,r11,8
...@@ -1302,24 +1302,24 @@ _GLOBAL(pseries_secondary_smp_init) ...@@ -1302,24 +1302,24 @@ _GLOBAL(pseries_secondary_smp_init)
isync isync
/* Set up a paca value for this processor. */ /* Set up a paca value for this processor. */
LOADADDR(r24, paca) /* Get base vaddr of paca array */ LOADADDR(r24, paca) /* Get base vaddr of paca array */
mulli r13,r3,PACA_SIZE /* Calculate vaddr of right paca */ mulli r13,r3,PACA_SIZE /* Calculate vaddr of right paca */
add r13,r13,r24 /* for this processor. */ add r13,r13,r24 /* for this processor. */
mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */ mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
mr r24,r3 /* __secondary_start needs cpu# */ mr r24,r3 /* __secondary_start needs cpu# */
1: 1:
HMT_LOW HMT_LOW
lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
/* start. */ /* start. */
sync sync
/* Create a temp kernel stack for use before relocation is on. */ /* Create a temp kernel stack for use before relocation is on. */
mr r1,r13 mr r1,r13
addi r1,r1,PACAGUARD addi r1,r1,PACAGUARD
addi r1,r1,0x1000 addi r1,r1,0x1000
subi r1,r1,STACK_FRAME_OVERHEAD subi r1,r1,STACK_FRAME_OVERHEAD
cmpwi 0,r23,0 cmpwi 0,r23,0
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
...@@ -1327,7 +1327,7 @@ _GLOBAL(pseries_secondary_smp_init) ...@@ -1327,7 +1327,7 @@ _GLOBAL(pseries_secondary_smp_init)
bne .__secondary_start bne .__secondary_start
#endif #endif
#endif #endif
b 1b /* Loop until told to go */ b 1b /* Loop until told to go */
#ifdef CONFIG_PPC_ISERIES #ifdef CONFIG_PPC_ISERIES
_GLOBAL(__start_initialization_iSeries) _GLOBAL(__start_initialization_iSeries)
/* Clear out the BSS */ /* Clear out the BSS */
...@@ -1335,13 +1335,13 @@ _GLOBAL(__start_initialization_iSeries) ...@@ -1335,13 +1335,13 @@ _GLOBAL(__start_initialization_iSeries)
LOADADDR(r8,__bss_start) LOADADDR(r8,__bss_start)
sub r11,r11,r8 /* bss size */ sub r11,r11,r8 /* bss size */
addi r11,r11,7 /* round up to an even double word */ addi r11,r11,7 /* round up to an even double word */
rldicl. r11,r11,61,3 /* shift right by 3 */ rldicl. r11,r11,61,3 /* shift right by 3 */
beq 4f beq 4f
addi r8,r8,-8 addi r8,r8,-8
li r0,0 li r0,0
mtctr r11 /* zero this many doublewords */ mtctr r11 /* zero this many doublewords */
3: stdu r0,8(r8) 3: stdu r0,8(r8)
bdnz 3b bdnz 3b
4: 4:
...@@ -1368,10 +1368,10 @@ _GLOBAL(__start_initialization_iSeries) ...@@ -1368,10 +1368,10 @@ _GLOBAL(__start_initialization_iSeries)
std r4,0(r9) /* set the naca pointer */ std r4,0(r9) /* set the naca pointer */
/* Get the pointer to the segment table */ /* Get the pointer to the segment table */
ld r6,PACA(r4) /* Get the base paca pointer */ ld r6,PACA(r4) /* Get the base paca pointer */
ld r4,PACASTABVIRT(r6) ld r4,PACASTABVIRT(r6)
bl .iSeries_fixup_klimit bl .iSeries_fixup_klimit
/* relocation is on at this point */ /* relocation is on at this point */
...@@ -1402,8 +1402,8 @@ _GLOBAL(__start_initialization_pSeries) ...@@ -1402,8 +1402,8 @@ _GLOBAL(__start_initialization_pSeries)
bl .reloc_offset bl .reloc_offset
LOADADDR(r2,__toc_start) LOADADDR(r2,__toc_start)
addi r2,r2,0x4000 addi r2,r2,0x4000
addi r2,r2,0x4000 addi r2,r2,0x4000
/* Relocate the TOC from a virt addr to a real addr */ /* Relocate the TOC from a virt addr to a real addr */
sub r2,r2,r3 sub r2,r2,r3
...@@ -1444,33 +1444,33 @@ _STATIC(__after_prom_start) ...@@ -1444,33 +1444,33 @@ _STATIC(__after_prom_start)
* unknown exception placeholders. * unknown exception placeholders.
* *
* Note: This process overwrites the OF exception vectors. * Note: This process overwrites the OF exception vectors.
* r26 == relocation offset * r26 == relocation offset
* r27 == KERNELBASE * r27 == KERNELBASE
*/ */
bl .reloc_offset bl .reloc_offset
mr r26,r3 mr r26,r3
SET_REG_TO_CONST(r27,KERNELBASE) SET_REG_TO_CONST(r27,KERNELBASE)
li r3,0 /* target addr */ li r3,0 /* target addr */
// XXX FIXME: Use phys returned by OF (r23) // XXX FIXME: Use phys returned by OF (r23)
sub r4,r27,r26 /* source addr */ sub r4,r27,r26 /* source addr */
/* current address of _start */ /* current address of _start */
/* i.e. where we are running */ /* i.e. where we are running */
/* the source addr */ /* the source addr */
LOADADDR(r5,copy_to_here) /* # bytes of memory to copy */ LOADADDR(r5,copy_to_here) /* # bytes of memory to copy */
sub r5,r5,r27 sub r5,r5,r27
li r6,0x100 /* Start offset, the first 0x100 */ li r6,0x100 /* Start offset, the first 0x100 */
/* bytes were copied earlier. */ /* bytes were copied earlier. */
bl .copy_and_flush /* copy the first n bytes */ bl .copy_and_flush /* copy the first n bytes */
/* this includes the code being */ /* this includes the code being */
/* executed here. */ /* executed here. */
LOADADDR(r0, 4f) /* Jump to the copy of this code */ LOADADDR(r0, 4f) /* Jump to the copy of this code */
mtctr r0 /* that we just made/relocated */ mtctr r0 /* that we just made/relocated */
bctr bctr
4: LOADADDR(r5,klimit) 4: LOADADDR(r5,klimit)
...@@ -1492,23 +1492,23 @@ _STATIC(__after_prom_start) ...@@ -1492,23 +1492,23 @@ _STATIC(__after_prom_start)
_GLOBAL(copy_and_flush) _GLOBAL(copy_and_flush)
addi r5,r5,-8 addi r5,r5,-8
addi r6,r6,-8 addi r6,r6,-8
4: li r0,16 /* Use the least common */ 4: li r0,16 /* Use the least common */
/* denominator cache line */ /* denominator cache line */
/* size. This results in */ /* size. This results in */
/* extra cache line flushes */ /* extra cache line flushes */
/* but operation is correct. */ /* but operation is correct. */
/* Can't get cache line size */ /* Can't get cache line size */
/* from NACA as it is being */ /* from NACA as it is being */
/* moved too. */ /* moved too. */
mtctr r0 /* put # words/line in ctr */ mtctr r0 /* put # words/line in ctr */
3: addi r6,r6,8 /* copy a cache line */ 3: addi r6,r6,8 /* copy a cache line */
ldx r0,r6,r4 ldx r0,r6,r4
stdx r0,r6,r3 stdx r0,r6,r3
bdnz 3b bdnz 3b
dcbst r6,r3 /* write it to memory */ dcbst r6,r3 /* write it to memory */
sync sync
icbi r6,r3 /* flush the icache line */ icbi r6,r3 /* flush the icache line */
cmpld 0,r6,r5 cmpld 0,r6,r5
blt 4b blt 4b
sync sync
...@@ -1529,9 +1529,9 @@ copy_to_here: ...@@ -1529,9 +1529,9 @@ copy_to_here:
* On entry: r13 == 'current' && last_task_used_math != 'current' * On entry: r13 == 'current' && last_task_used_math != 'current'
*/ */
_STATIC(load_up_fpu) _STATIC(load_up_fpu)
mfmsr r5 /* grab the current MSR */ mfmsr r5 /* grab the current MSR */
ori r5,r5,MSR_FP ori r5,r5,MSR_FP
mtmsrd r5 /* enable use of fpu now */ mtmsrd r5 /* enable use of fpu now */
isync isync
/* /*
* For SMP, we don't do lazy FPU switching because it just gets too * For SMP, we don't do lazy FPU switching because it just gets too
...@@ -1580,10 +1580,10 @@ _STATIC(load_up_fpu) ...@@ -1580,10 +1580,10 @@ _STATIC(load_up_fpu)
* Disable the FPU. * Disable the FPU.
*/ */
_GLOBAL(disable_kernel_fp) _GLOBAL(disable_kernel_fp)
mfmsr r3 mfmsr r3
rldicl r0,r3,(63-MSR_FP_LG),1 rldicl r0,r3,(63-MSR_FP_LG),1
rldicl r3,r0,(MSR_FP_LG+1),0 rldicl r3,r0,(MSR_FP_LG+1),0
mtmsrd r3 /* disable use of fpu now */ mtmsrd r3 /* disable use of fpu now */
isync isync
blr blr
...@@ -1632,9 +1632,9 @@ _GLOBAL(giveup_fpu) ...@@ -1632,9 +1632,9 @@ _GLOBAL(giveup_fpu)
* On entry: r13 == 'current' && last_task_used_altivec != 'current' * On entry: r13 == 'current' && last_task_used_altivec != 'current'
*/ */
_STATIC(load_up_altivec) _STATIC(load_up_altivec)
mfmsr r5 /* grab the current MSR */ mfmsr r5 /* grab the current MSR */
oris r5,r5,MSR_VEC@h oris r5,r5,MSR_VEC@h
mtmsrd r5 /* enable use of VMX now */ mtmsrd r5 /* enable use of VMX now */
isync isync
/* /*
...@@ -1698,10 +1698,10 @@ _STATIC(load_up_altivec) ...@@ -1698,10 +1698,10 @@ _STATIC(load_up_altivec)
* Disable the VMX. * Disable the VMX.
*/ */
_GLOBAL(disable_kernel_altivec) _GLOBAL(disable_kernel_altivec)
mfmsr r3 mfmsr r3
rldicl r0,r3,(63-MSR_VEC_LG),1 rldicl r0,r3,(63-MSR_VEC_LG),1
rldicl r3,r0,(MSR_VEC_LG+1),0 rldicl r3,r0,(MSR_VEC_LG+1),0
mtmsrd r3 /* disable use of VMX now */ mtmsrd r3 /* disable use of VMX now */
isync isync
blr blr
...@@ -1778,16 +1778,16 @@ _GLOBAL(pmac_secondary_start) ...@@ -1778,16 +1778,16 @@ _GLOBAL(pmac_secondary_start)
mtmsrd r3 /* RI on */ mtmsrd r3 /* RI on */
/* Set up a paca value for this processor. */ /* Set up a paca value for this processor. */
LOADADDR(r4, paca) /* Get base vaddr of paca array */ LOADADDR(r4, paca) /* Get base vaddr of paca array */
mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
add r13,r13,r4 /* for this processor. */ add r13,r13,r4 /* for this processor. */
mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */ mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
/* Create a temp kernel stack for use before relocation is on. */ /* Create a temp kernel stack for use before relocation is on. */
mr r1,r13 mr r1,r13
addi r1,r1,PACAGUARD addi r1,r1,PACAGUARD
addi r1,r1,0x1000 addi r1,r1,0x1000
subi r1,r1,STACK_FRAME_OVERHEAD subi r1,r1,STACK_FRAME_OVERHEAD
b .__secondary_start b .__secondary_start
...@@ -1801,7 +1801,7 @@ _GLOBAL(pmac_secondary_start) ...@@ -1801,7 +1801,7 @@ _GLOBAL(pmac_secondary_start)
* 1. Processor number * 1. Processor number
* 2. Segment table pointer (virtual address) * 2. Segment table pointer (virtual address)
* On entry the following are set: * On entry the following are set:
* r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
* r24 = cpu# (in Linux terms) * r24 = cpu# (in Linux terms)
* r13 = paca virtual address * r13 = paca virtual address
* SPRG3 = paca virtual address * SPRG3 = paca virtual address
...@@ -1812,8 +1812,8 @@ _GLOBAL(__secondary_start) ...@@ -1812,8 +1812,8 @@ _GLOBAL(__secondary_start)
/* set up the TOC (virtual address) */ /* set up the TOC (virtual address) */
LOADADDR(r2,__toc_start) LOADADDR(r2,__toc_start)
addi r2,r2,0x4000 addi r2,r2,0x4000
addi r2,r2,0x4000 addi r2,r2,0x4000
std r2,PACATOC(r13) std r2,PACATOC(r13)
li r6,0 li r6,0
...@@ -1822,24 +1822,24 @@ _GLOBAL(__secondary_start) ...@@ -1822,24 +1822,24 @@ _GLOBAL(__secondary_start)
#ifndef CONFIG_PPC_ISERIES #ifndef CONFIG_PPC_ISERIES
/* Initialize the page table pointer register. */ /* Initialize the page table pointer register. */
LOADADDR(r6,_SDR1) LOADADDR(r6,_SDR1)
ld r6,0(r6) /* get the value of _SDR1 */ ld r6,0(r6) /* get the value of _SDR1 */
mtspr SDR1,r6 /* set the htab location */ mtspr SDR1,r6 /* set the htab location */
#endif #endif
/* Initialize the first segment table (or SLB) entry */ /* Initialize the first segment table (or SLB) entry */
ld r3,PACASTABVIRT(r13) /* get addr of segment table */ ld r3,PACASTABVIRT(r13) /* get addr of segment table */
bl .stab_initialize bl .stab_initialize
/* Initialize the kernel stack. Just a repeat for iSeries. */ /* Initialize the kernel stack. Just a repeat for iSeries. */
LOADADDR(r3,current_set) LOADADDR(r3,current_set)
sldi r28,r24,3 /* get current_set[cpu#] */ sldi r28,r24,3 /* get current_set[cpu#] */
ldx r1,r3,r28 ldx r1,r3,r28
addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
li r0,0 li r0,0
std r0,0(r1) std r0,0(r1)
std r1,PACAKSAVE(r13) std r1,PACAKSAVE(r13)
ld r3,PACASTABREAL(r13) /* get raddr of segment table */ ld r3,PACASTABREAL(r13) /* get raddr of segment table */
ori r4,r3,1 /* turn on valid bit */ ori r4,r3,1 /* turn on valid bit */
#ifdef CONFIG_PPC_ISERIES #ifdef CONFIG_PPC_ISERIES
li r0,-1 /* hypervisor call */ li r0,-1 /* hypervisor call */
...@@ -1849,23 +1849,23 @@ _GLOBAL(__secondary_start) ...@@ -1849,23 +1849,23 @@ _GLOBAL(__secondary_start)
sc /* HvCall_setASR */ sc /* HvCall_setASR */
#else #else
/* set the ASR */ /* set the ASR */
li r3,SYSTEMCFG_PHYS_ADDR /* r3 = ptr to systemcfg */ li r3,SYSTEMCFG_PHYS_ADDR /* r3 = ptr to systemcfg */
lwz r3,PLATFORM(r3) /* r3 = platform flags */ lwz r3,PLATFORM(r3) /* r3 = platform flags */
cmpldi r3,PLATFORM_PSERIES_LPAR cmpldi r3,PLATFORM_PSERIES_LPAR
bne 98f bne 98f
mfspr r3,PVR mfspr r3,PVR
srwi r3,r3,16 srwi r3,r3,16
cmpwi r3,0x37 /* SStar */ cmpwi r3,0x37 /* SStar */
beq 97f beq 97f
cmpwi r3,0x36 /* IStar */ cmpwi r3,0x36 /* IStar */
beq 97f beq 97f
cmpwi r3,0x34 /* Pulsar */ cmpwi r3,0x34 /* Pulsar */
bne 98f bne 98f
97: li r3,H_SET_ASR /* hcall = H_SET_ASR */ 97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
HVSC /* Invoking hcall */ HVSC /* Invoking hcall */
b 99f b 99f
98: /* !(rpa hypervisor) || !(star) */ 98: /* !(rpa hypervisor) || !(star) */
mtasr r4 /* set the stab location */ mtasr r4 /* set the stab location */
99: 99:
#endif #endif
li r7,0 li r7,0
...@@ -1887,7 +1887,7 @@ _GLOBAL(__secondary_start) ...@@ -1887,7 +1887,7 @@ _GLOBAL(__secondary_start)
*/ */
_GLOBAL(start_secondary_prolog) _GLOBAL(start_secondary_prolog)
li r3,0 li r3,0
std r3,0(r1) /* Zero the stack frame pointer */ std r3,0(r1) /* Zero the stack frame pointer */
bl .start_secondary bl .start_secondary
#endif #endif
...@@ -1895,14 +1895,14 @@ _GLOBAL(start_secondary_prolog) ...@@ -1895,14 +1895,14 @@ _GLOBAL(start_secondary_prolog)
* This subroutine clobbers r11 and r12 * This subroutine clobbers r11 and r12
*/ */
_GLOBAL(enable_64b_mode) _GLOBAL(enable_64b_mode)
mfmsr r11 /* grab the current MSR */ mfmsr r11 /* grab the current MSR */
li r12,1 li r12,1
rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG) rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
or r11,r11,r12 or r11,r11,r12
li r12,1 li r12,1
rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG) rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
or r11,r11,r12 or r11,r11,r12
mtmsrd r11 mtmsrd r11
isync isync
blr blr
...@@ -1919,30 +1919,30 @@ _STATIC(start_here_pSeries) ...@@ -1919,30 +1919,30 @@ _STATIC(start_here_pSeries)
ori r6,r6,MSR_RI ori r6,r6,MSR_RI
mtmsrd r6 /* RI on */ mtmsrd r6 /* RI on */
/* setup the systemcfg pointer which is needed by *tab_initialize */ /* setup the systemcfg pointer which is needed by *tab_initialize */
LOADADDR(r6,systemcfg) LOADADDR(r6,systemcfg)
sub r6,r6,r26 /* addr of the variable systemcfg */ sub r6,r6,r26 /* addr of the variable systemcfg */
li r27,SYSTEMCFG_PHYS_ADDR li r27,SYSTEMCFG_PHYS_ADDR
std r27,0(r6) /* set the value of systemcfg */ std r27,0(r6) /* set the value of systemcfg */
/* setup the naca pointer which is needed by *tab_initialize */ /* setup the naca pointer which is needed by *tab_initialize */
LOADADDR(r6,naca) LOADADDR(r6,naca)
sub r6,r6,r26 /* addr of the variable naca */ sub r6,r6,r26 /* addr of the variable naca */
li r27,NACA_PHYS_ADDR li r27,NACA_PHYS_ADDR
std r27,0(r6) /* set the value of naca */ std r27,0(r6) /* set the value of naca */
#ifdef CONFIG_HMT #ifdef CONFIG_HMT
/* Start up the second thread on cpu 0 */ /* Start up the second thread on cpu 0 */
mfspr r3,PVR mfspr r3,PVR
srwi r3,r3,16 srwi r3,r3,16
cmpwi r3,0x34 /* Pulsar */ cmpwi r3,0x34 /* Pulsar */
beq 90f beq 90f
cmpwi r3,0x36 /* Icestar */ cmpwi r3,0x36 /* Icestar */
beq 90f beq 90f
cmpwi r3,0x37 /* SStar */ cmpwi r3,0x37 /* SStar */
beq 90f beq 90f
b 91f /* HMT not supported */ b 91f /* HMT not supported */
90: li r3,0 90: li r3,0
bl .hmt_start_secondary bl .hmt_start_secondary
91: 91:
#endif #endif
...@@ -1957,7 +1957,7 @@ _STATIC(start_here_pSeries) ...@@ -1957,7 +1957,7 @@ _STATIC(start_here_pSeries)
li r3,1 li r3,1
LOADADDR(r5,__secondary_hold_spinloop) LOADADDR(r5,__secondary_hold_spinloop)
tophys(r4,r5) tophys(r4,r5)
std r3,0(r4) std r3,0(r4)
#endif #endif
/* The following gets the stack and TOC set up with the regs */ /* The following gets the stack and TOC set up with the regs */
...@@ -1976,8 +1976,8 @@ _STATIC(start_here_pSeries) ...@@ -1976,8 +1976,8 @@ _STATIC(start_here_pSeries)
/* set up the TOC (physical address) */ /* set up the TOC (physical address) */
LOADADDR(r2,__toc_start) LOADADDR(r2,__toc_start)
addi r2,r2,0x4000 addi r2,r2,0x4000
addi r2,r2,0x4000 addi r2,r2,0x4000
sub r2,r2,r26 sub r2,r2,r26
LOADADDR(r3,cpu_specs) LOADADDR(r3,cpu_specs)
...@@ -1987,44 +1987,44 @@ _STATIC(start_here_pSeries) ...@@ -1987,44 +1987,44 @@ _STATIC(start_here_pSeries)
mr r5,r26 mr r5,r26
bl .identify_cpu bl .identify_cpu
/* Get the pointer to the segment table which is used by */ /* Get the pointer to the segment table which is used by */
/* stab_initialize */ /* stab_initialize */
LOADADDR(r27, boot_cpuid) LOADADDR(r27, boot_cpuid)
sub r27,r27,r26 sub r27,r27,r26
lwz r27,0(r27) lwz r27,0(r27)
LOADADDR(r24, paca) /* Get base vaddr of paca array */ LOADADDR(r24, paca) /* Get base vaddr of paca array */
mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */ mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */
add r13,r13,r24 /* for this processor. */ add r13,r13,r24 /* for this processor. */
sub r13,r13,r26 /* convert to physical addr */ sub r13,r13,r26 /* convert to physical addr */
mtspr SPRG3,r13 /* PPPBBB: Temp... -Peter */ mtspr SPRG3,r13 /* PPPBBB: Temp... -Peter */
ld r3,PACASTABREAL(r13) ld r3,PACASTABREAL(r13)
ori r4,r3,1 /* turn on valid bit */ ori r4,r3,1 /* turn on valid bit */
/* set the ASR */ /* set the ASR */
li r3,SYSTEMCFG_PHYS_ADDR /* r3 = ptr to systemcfg */ li r3,SYSTEMCFG_PHYS_ADDR /* r3 = ptr to systemcfg */
lwz r3,PLATFORM(r3) /* r3 = platform flags */ lwz r3,PLATFORM(r3) /* r3 = platform flags */
cmpldi r3,PLATFORM_PSERIES_LPAR cmpldi r3,PLATFORM_PSERIES_LPAR
bne 98f bne 98f
mfspr r3,PVR mfspr r3,PVR
srwi r3,r3,16 srwi r3,r3,16
cmpwi r3,0x37 /* SStar */ cmpwi r3,0x37 /* SStar */
beq 97f beq 97f
cmpwi r3,0x36 /* IStar */ cmpwi r3,0x36 /* IStar */
beq 97f beq 97f
cmpwi r3,0x34 /* Pulsar */ cmpwi r3,0x34 /* Pulsar */
bne 98f bne 98f
97: li r3,H_SET_ASR /* hcall = H_SET_ASR */ 97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
HVSC /* Invoking hcall */ HVSC /* Invoking hcall */
b 99f b 99f
98: /* !(rpa hypervisor) || !(star) */ 98: /* !(rpa hypervisor) || !(star) */
mtasr r4 /* set the stab location */ mtasr r4 /* set the stab location */
99: 99:
mfspr r6,SPRG3 mfspr r6,SPRG3
ld r3,PACASTABREAL(r6) /* restore r3 for stab_initialize */ ld r3,PACASTABREAL(r6) /* restore r3 for stab_initialize */
/* Initialize an initial memory mapping and turn on relocation. */ /* Initialize an initial memory mapping and turn on relocation. */
bl .stab_initialize bl .stab_initialize
bl .htab_initialize bl .htab_initialize
...@@ -2032,7 +2032,7 @@ _STATIC(start_here_pSeries) ...@@ -2032,7 +2032,7 @@ _STATIC(start_here_pSeries)
lwz r3,PLATFORM(r3) /* r3 = platform flags */ lwz r3,PLATFORM(r3) /* r3 = platform flags */
/* Test if bit 0 is set (LPAR bit) */ /* Test if bit 0 is set (LPAR bit) */
andi. r3,r3,0x1 andi. r3,r3,0x1
bne 98f bne 98f
LOADADDR(r6,_SDR1) /* Only if NOT LPAR */ LOADADDR(r6,_SDR1) /* Only if NOT LPAR */
sub r6,r6,r26 sub r6,r6,r26
ld r6,0(r6) /* get the value of _SDR1 */ ld r6,0(r6) /* get the value of _SDR1 */
...@@ -2061,8 +2061,8 @@ _STATIC(start_here_common) ...@@ -2061,8 +2061,8 @@ _STATIC(start_here_common)
/* set up the TOC */ /* set up the TOC */
LOADADDR(r2,__toc_start) LOADADDR(r2,__toc_start)
addi r2,r2,0x4000 addi r2,r2,0x4000
addi r2,r2,0x4000 addi r2,r2,0x4000
/* Apply the CPUs-specific fixups (nop out sections not relevant /* Apply the CPUs-specific fixups (nop out sections not relevant
* to this CPU * to this CPU
...@@ -2078,14 +2078,14 @@ _STATIC(start_here_common) ...@@ -2078,14 +2078,14 @@ _STATIC(start_here_common)
/* setup the naca pointer */ /* setup the naca pointer */
LOADADDR(r9,naca) LOADADDR(r9,naca)
SET_REG_TO_CONST(r8, NACA_VIRT_ADDR) SET_REG_TO_CONST(r8, NACA_VIRT_ADDR)
std r8,0(r9) /* set the value of the naca ptr */ std r8,0(r9) /* set the value of the naca ptr */
LOADADDR(r26, boot_cpuid) LOADADDR(r26, boot_cpuid)
lwz r26,0(r26) lwz r26,0(r26)
LOADADDR(r24, paca) /* Get base vaddr of paca array */ LOADADDR(r24, paca) /* Get base vaddr of paca array */
mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */ mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */
add r13,r13,r24 /* for this processor. */ add r13,r13,r24 /* for this processor. */
mtspr SPRG3,r13 mtspr SPRG3,r13
/* ptr to current */ /* ptr to current */
...@@ -2124,11 +2124,11 @@ _GLOBAL(hmt_init) ...@@ -2124,11 +2124,11 @@ _GLOBAL(hmt_init)
LOADADDR(r5, hmt_thread_data) LOADADDR(r5, hmt_thread_data)
mfspr r7,PVR mfspr r7,PVR
srwi r7,r7,16 srwi r7,r7,16
cmpwi r7,0x34 /* Pulsar */ cmpwi r7,0x34 /* Pulsar */
beq 90f beq 90f
cmpwi r7,0x36 /* Icestar */ cmpwi r7,0x36 /* Icestar */
beq 91f beq 91f
cmpwi r7,0x37 /* SStar */ cmpwi r7,0x37 /* SStar */
beq 91f beq 91f
b 101f b 101f
90: mfspr r6,PIR 90: mfspr r6,PIR
...@@ -2162,32 +2162,32 @@ __hmt_secondary_hold: ...@@ -2162,32 +2162,32 @@ __hmt_secondary_hold:
104: addi r7,r7,4 104: addi r7,r7,4
lwzx r9,r5,r7 lwzx r9,r5,r7
mr r24,r9 mr r24,r9
101: 101:
#endif #endif
mr r3,r24 mr r3,r24
b .pseries_secondary_smp_init b .pseries_secondary_smp_init
#ifdef CONFIG_HMT #ifdef CONFIG_HMT
_GLOBAL(hmt_start_secondary) _GLOBAL(hmt_start_secondary)
LOADADDR(r4,__hmt_secondary_hold) LOADADDR(r4,__hmt_secondary_hold)
clrldi r4,r4,4 clrldi r4,r4,4
mtspr NIADORM, r4 mtspr NIADORM, r4
mfspr r4, MSRDORM mfspr r4, MSRDORM
li r5, -65 li r5, -65
and r4, r4, r5 and r4, r4, r5
mtspr MSRDORM, r4 mtspr MSRDORM, r4
lis r4,0xffef lis r4,0xffef
ori r4,r4,0x7403 ori r4,r4,0x7403
mtspr TSC, r4 mtspr TSC, r4
li r4,0x1f4 li r4,0x1f4
mtspr TST, r4 mtspr TST, r4
mfspr r4, HID0 mfspr r4, HID0
ori r4, r4, 0x1 ori r4, r4, 0x1
mtspr HID0, r4 mtspr HID0, r4
mfspr r4, CTRLF mfspr r4, CTRLF
oris r4, r4, 0x40 oris r4, r4, 0x40
mtspr CTRLT, r4 mtspr CTRLT, r4
blr blr
#endif #endif
...@@ -2197,7 +2197,7 @@ _GLOBAL(hmt_start_secondary) ...@@ -2197,7 +2197,7 @@ _GLOBAL(hmt_start_secondary)
* which is page-aligned. * which is page-aligned.
*/ */
.data .data
.align 12 .align 12
.globl sdata .globl sdata
sdata: sdata:
.globl empty_zero_page .globl empty_zero_page
...@@ -2215,7 +2215,7 @@ ioremap_dir: ...@@ -2215,7 +2215,7 @@ ioremap_dir:
/* 1 page segment table per cpu (max 48, cpu0 allocated at STAB0_PHYS_ADDR) */ /* 1 page segment table per cpu (max 48, cpu0 allocated at STAB0_PHYS_ADDR) */
.globl stab_array .globl stab_array
stab_array: stab_array:
.space 4096 * 48 .space 4096 * 48
/* /*
* This space gets a copy of optional info passed to us by the bootstrap * This space gets a copy of optional info passed to us by the bootstrap
......
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