Commit 9cb7e5a9 authored by Chunming Zhou's avatar Chunming Zhou Committed by Alex Deucher

drm/amdgpu: add context entity init

Signed-off-by: default avatarChunming Zhou <david1.zhou@amd.com>
Acked-by: default avatarChristian K?nig <christian.koenig@amd.com>
Reviewed-by: default avatarJammy Zhou <Jammy.Zhou@amd.com>
parent b80d8475
...@@ -994,10 +994,12 @@ struct amdgpu_vm_manager { ...@@ -994,10 +994,12 @@ struct amdgpu_vm_manager {
struct amdgpu_ctx_ring { struct amdgpu_ctx_ring {
uint64_t sequence; uint64_t sequence;
struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING]; struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING];
struct amd_context_entity c_entity;
}; };
struct amdgpu_ctx { struct amdgpu_ctx {
struct kref refcount; struct kref refcount;
struct amdgpu_device *adev;
unsigned reset_counter; unsigned reset_counter;
spinlock_t ring_lock; spinlock_t ring_lock;
struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
......
...@@ -28,13 +28,23 @@ ...@@ -28,13 +28,23 @@
static void amdgpu_ctx_do_release(struct kref *ref) static void amdgpu_ctx_do_release(struct kref *ref)
{ {
struct amdgpu_ctx *ctx; struct amdgpu_ctx *ctx;
struct amdgpu_device *adev;
unsigned i, j; unsigned i, j;
ctx = container_of(ref, struct amdgpu_ctx, refcount); ctx = container_of(ref, struct amdgpu_ctx, refcount);
adev = ctx->adev;
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
for (j = 0; j < AMDGPU_CTX_MAX_CS_PENDING; ++j) for (j = 0; j < AMDGPU_CTX_MAX_CS_PENDING; ++j)
fence_put(ctx->rings[i].fences[j]); fence_put(ctx->rings[i].fences[j]);
if (amdgpu_enable_scheduler) {
for (i = 0; i < adev->num_rings; i++)
amd_context_entity_fini(adev->rings[i]->scheduler,
&ctx->rings[i].c_entity);
}
kfree(ctx); kfree(ctx);
} }
...@@ -43,7 +53,7 @@ int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, ...@@ -43,7 +53,7 @@ int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
{ {
struct amdgpu_ctx *ctx; struct amdgpu_ctx *ctx;
struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
int i, r; int i, j, r;
ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
if (!ctx) if (!ctx)
...@@ -59,11 +69,35 @@ int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, ...@@ -59,11 +69,35 @@ int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
*id = (uint32_t)r; *id = (uint32_t)r;
memset(ctx, 0, sizeof(*ctx)); memset(ctx, 0, sizeof(*ctx));
ctx->adev = adev;
kref_init(&ctx->refcount); kref_init(&ctx->refcount);
spin_lock_init(&ctx->ring_lock); spin_lock_init(&ctx->ring_lock);
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
ctx->rings[i].sequence = 1; ctx->rings[i].sequence = 1;
mutex_unlock(&mgr->lock); mutex_unlock(&mgr->lock);
if (amdgpu_enable_scheduler) {
/* create context entity for each ring */
for (i = 0; i < adev->num_rings; i++) {
struct amd_run_queue *rq;
if (fpriv)
rq = &adev->rings[i]->scheduler->sched_rq;
else
rq = &adev->rings[i]->scheduler->kernel_rq;
r = amd_context_entity_init(adev->rings[i]->scheduler,
&ctx->rings[i].c_entity,
NULL, rq, *id);
if (r)
break;
}
if (i < adev->num_rings) {
for (j = 0; j < i; j++)
amd_context_entity_fini(adev->rings[j]->scheduler,
&ctx->rings[j].c_entity);
kfree(ctx);
return -EINVAL;
}
}
return 0; return 0;
} }
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment