Commit 9d67006e authored by Alex Deucher's avatar Alex Deucher

drm/radeon/kms: add dpm support for rs780/rs880

This adds dpm support for rs780/rs880 asics.  This includes:
- clockgating
- dynamic engine clock scaling
- dynamic voltage scaling

set radeon.dpm=1 to enable it.
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2e9d4c05
...@@ -77,7 +77,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ ...@@ -77,7 +77,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \ evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \
atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \ atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \ si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \
r600_dpm.o r600_dpm.o rs780_dpm.o
radeon-$(CONFIG_COMPAT) += radeon_ioc32.o radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
......
...@@ -1242,6 +1242,18 @@ static struct radeon_asic rs780_asic = { ...@@ -1242,6 +1242,18 @@ static struct radeon_asic rs780_asic = {
.set_clock_gating = NULL, .set_clock_gating = NULL,
.get_temperature = &rv6xx_get_temp, .get_temperature = &rv6xx_get_temp,
}, },
.dpm = {
.init = &rs780_dpm_init,
.setup_asic = &rs780_dpm_setup_asic,
.enable = &rs780_dpm_enable,
.disable = &rs780_dpm_disable,
.set_power_state = &rs780_dpm_set_power_state,
.display_configuration_changed = &rs780_dpm_display_configuration_changed,
.fini = &rs780_dpm_fini,
.get_sclk = &rs780_dpm_get_sclk,
.get_mclk = &rs780_dpm_get_mclk,
.print_power_state = &rs780_dpm_print_power_state,
},
.pflip = { .pflip = {
.pre_page_flip = &rs600_pre_page_flip, .pre_page_flip = &rs600_pre_page_flip,
.page_flip = &rs600_page_flip, .page_flip = &rs600_page_flip,
......
...@@ -402,6 +402,18 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev); ...@@ -402,6 +402,18 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev);
u32 r600_get_xclk(struct radeon_device *rdev); u32 r600_get_xclk(struct radeon_device *rdev);
uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev); uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
int rv6xx_get_temp(struct radeon_device *rdev); int rv6xx_get_temp(struct radeon_device *rdev);
/* rs780 dpm */
int rs780_dpm_init(struct radeon_device *rdev);
int rs780_dpm_enable(struct radeon_device *rdev);
void rs780_dpm_disable(struct radeon_device *rdev);
int rs780_dpm_set_power_state(struct radeon_device *rdev);
void rs780_dpm_setup_asic(struct radeon_device *rdev);
void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
void rs780_dpm_fini(struct radeon_device *rdev);
u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
void rs780_dpm_print_power_state(struct radeon_device *rdev,
struct radeon_ps *ps);
/* uvd */ /* uvd */
int r600_uvd_init(struct radeon_device *rdev); int r600_uvd_init(struct radeon_device *rdev);
......
...@@ -1030,6 +1030,13 @@ int radeon_pm_init(struct radeon_device *rdev) ...@@ -1030,6 +1030,13 @@ int radeon_pm_init(struct radeon_device *rdev)
{ {
/* enable dpm on rv6xx+ */ /* enable dpm on rv6xx+ */
switch (rdev->family) { switch (rdev->family) {
case CHIP_RS780:
case CHIP_RS880:
if (radeon_dpm == 1)
rdev->pm.pm_method = PM_METHOD_DPM;
else
rdev->pm.pm_method = PM_METHOD_PROFILE;
break;
default: default:
/* default to profile method */ /* default to profile method */
rdev->pm.pm_method = PM_METHOD_PROFILE; rdev->pm.pm_method = PM_METHOD_PROFILE;
......
This diff is collapsed.
/*
* Copyright 2011 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __RS780_DPM_H__
#define __RS780_DPM_H__
enum rs780_vddc_level {
RS780_VDDC_LEVEL_UNKNOWN = 0,
RS780_VDDC_LEVEL_LOW = 1,
RS780_VDDC_LEVEL_HIGH = 2,
};
struct igp_power_info {
/* flags */
bool invert_pwm_required;
bool pwm_voltage_control;
bool voltage_control;
bool gfx_clock_gating;
/* stored values */
u32 system_config;
u32 bootup_uma_clk;
u16 max_voltage;
u16 min_voltage;
u16 boot_voltage;
u16 inter_voltage_low;
u16 inter_voltage_high;
u16 num_of_cycles_in_period;
/* variable */
int crtc_id;
int refresh_rate;
};
struct igp_ps {
enum rs780_vddc_level min_voltage;
enum rs780_vddc_level max_voltage;
u32 sclk_low;
u32 sclk_high;
u32 flags;
};
#define RS780_CGFTV_DFLT 0x0303000f
#define RS780_FBDIVTIMERVAL_DFLT 0x2710
#define RS780_FVTHROTUTC0_DFLT 0x04010040
#define RS780_FVTHROTUTC1_DFLT 0x04010040
#define RS780_FVTHROTUTC2_DFLT 0x04010040
#define RS780_FVTHROTUTC3_DFLT 0x04010040
#define RS780_FVTHROTUTC4_DFLT 0x04010040
#define RS780_FVTHROTDTC0_DFLT 0x04010040
#define RS780_FVTHROTDTC1_DFLT 0x04010040
#define RS780_FVTHROTDTC2_DFLT 0x04010040
#define RS780_FVTHROTDTC3_DFLT 0x04010040
#define RS780_FVTHROTDTC4_DFLT 0x04010040
#define RS780_FVTHROTFBUSREG0_DFLT 0x00001001
#define RS780_FVTHROTFBUSREG1_DFLT 0x00002002
#define RS780_FVTHROTFBDSREG0_DFLT 0x00004001
#define RS780_FVTHROTFBDSREG1_DFLT 0x00020010
#define RS780_FVTHROTPWMUSREG0_DFLT 0x00002001
#define RS780_FVTHROTPWMUSREG1_DFLT 0x00004003
#define RS780_FVTHROTPWMDSREG0_DFLT 0x00002001
#define RS780_FVTHROTPWMDSREG1_DFLT 0x00004003
#define RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT 0x37
#define RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT 0x4b
#define RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT 0x8b
#define RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT 0x8b
#define RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT 0x8c
#define RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT 0xb5
#define RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT 0x8d
#define RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT 0x8e
#define RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT 0xBa
#define RS780_FVTHROTPWMRANGE0_GPIO_DFLT 0x1a
#define RS780_FVTHROTPWMRANGE1_GPIO_DFLT 0x1a
#define RS780_FVTHROTPWMRANGE2_GPIO_DFLT 0x0
#define RS780_FVTHROTPWMRANGE3_GPIO_DFLT 0x0
#define RS780_SLOWCLKFEEDBACKDIV_DFLT 110
#define RS780_CGCLKGATING_DFLT 0x0000E204
#define RS780_DEFAULT_VCLK_FREQ 53300 /* 10 khz */
#define RS780_DEFAULT_DCLK_FREQ 40000 /* 10 khz */
#endif
/*
* Copyright 2011 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __RS780D_H__
#define __RS780D_H__
#define CG_SPLL_FUNC_CNTL 0x600
# define SPLL_RESET (1 << 0)
# define SPLL_SLEEP (1 << 1)
# define SPLL_REF_DIV(x) ((x) << 2)
# define SPLL_REF_DIV_MASK (7 << 2)
# define SPLL_FB_DIV(x) ((x) << 5)
# define SPLL_FB_DIV_MASK (0xff << 2)
# define SPLL_FB_DIV_SHIFT 2
# define SPLL_PULSEEN (1 << 13)
# define SPLL_PULSENUM(x) ((x) << 14)
# define SPLL_PULSENUM_MASK (3 << 14)
# define SPLL_SW_HILEN(x) ((x) << 16)
# define SPLL_SW_HILEN_MASK (0xf << 16)
# define SPLL_SW_LOLEN(x) ((x) << 20)
# define SPLL_SW_LOLEN_MASK (0xf << 20)
# define SPLL_DIVEN (1 << 24)
# define SPLL_BYPASS_EN (1 << 25)
# define SPLL_CHG_STATUS (1 << 29)
# define SPLL_CTLREQ (1 << 30)
# define SPLL_CTLACK (1 << 31)
/* RS780/RS880 PM */
#define FVTHROT_CNTRL_REG 0x3000
#define DONT_WAIT_FOR_FBDIV_WRAP (1 << 0)
#define MINIMUM_CIP(x) ((x) << 1)
#define MINIMUM_CIP_SHIFT 1
#define MINIMUM_CIP_MASK 0x1fffffe
#define REFRESH_RATE_DIVISOR(x) ((x) << 25)
#define REFRESH_RATE_DIVISOR_SHIFT 25
#define REFRESH_RATE_DIVISOR_MASK (0x3 << 25)
#define ENABLE_FV_THROT (1 << 27)
#define ENABLE_FV_UPDATE (1 << 28)
#define TREND_SEL_MODE (1 << 29)
#define FORCE_TREND_SEL (1 << 30)
#define ENABLE_FV_THROT_IO (1 << 31)
#define FVTHROT_TARGET_REG 0x3004
#define TARGET_IDLE_COUNT(x) ((x) << 0)
#define TARGET_IDLE_COUNT_MASK 0xffffff
#define TARGET_IDLE_COUNT_SHIFT 0
#define FVTHROT_CB1 0x3008
#define FVTHROT_CB2 0x300c
#define FVTHROT_CB3 0x3010
#define FVTHROT_CB4 0x3014
#define FVTHROT_UTC0 0x3018
#define FVTHROT_UTC1 0x301c
#define FVTHROT_UTC2 0x3020
#define FVTHROT_UTC3 0x3024
#define FVTHROT_UTC4 0x3028
#define FVTHROT_DTC0 0x302c
#define FVTHROT_DTC1 0x3030
#define FVTHROT_DTC2 0x3034
#define FVTHROT_DTC3 0x3038
#define FVTHROT_DTC4 0x303c
#define FVTHROT_FBDIV_REG0 0x3040
#define MIN_FEEDBACK_DIV(x) ((x) << 0)
#define MIN_FEEDBACK_DIV_MASK 0xfff
#define MIN_FEEDBACK_DIV_SHIFT 0
#define MAX_FEEDBACK_DIV(x) ((x) << 12)
#define MAX_FEEDBACK_DIV_MASK (0xfff << 12)
#define MAX_FEEDBACK_DIV_SHIFT 12
#define FVTHROT_FBDIV_REG1 0x3044
#define MAX_FEEDBACK_STEP(x) ((x) << 0)
#define MAX_FEEDBACK_STEP_MASK 0xfff
#define MAX_FEEDBACK_STEP_SHIFT 0
#define STARTING_FEEDBACK_DIV(x) ((x) << 12)
#define STARTING_FEEDBACK_DIV_MASK (0xfff << 12)
#define STARTING_FEEDBACK_DIV_SHIFT 12
#define FORCE_FEEDBACK_DIV (1 << 24)
#define FVTHROT_FBDIV_REG2 0x3048
#define FORCED_FEEDBACK_DIV(x) ((x) << 0)
#define FORCED_FEEDBACK_DIV_MASK 0xfff
#define FORCED_FEEDBACK_DIV_SHIFT 0
#define FB_DIV_TIMER_VAL(x) ((x) << 12)
#define FB_DIV_TIMER_VAL_MASK (0xffff << 12)
#define FB_DIV_TIMER_VAL_SHIFT 12
#define FVTHROT_FB_US_REG0 0x304c
#define FVTHROT_FB_US_REG1 0x3050
#define FVTHROT_FB_DS_REG0 0x3054
#define FVTHROT_FB_DS_REG1 0x3058
#define FVTHROT_PWM_CTRL_REG0 0x305c
#define STARTING_PWM_HIGHTIME(x) ((x) << 0)
#define STARTING_PWM_HIGHTIME_MASK 0xfff
#define STARTING_PWM_HIGHTIME_SHIFT 0
#define NUMBER_OF_CYCLES_IN_PERIOD(x) ((x) << 12)
#define NUMBER_OF_CYCLES_IN_PERIOD_MASK (0xfff << 12)
#define NUMBER_OF_CYCLES_IN_PERIOD_SHIFT 12
#define FORCE_STARTING_PWM_HIGHTIME (1 << 24)
#define INVERT_PWM_WAVEFORM (1 << 25)
#define FVTHROT_PWM_CTRL_REG1 0x3060
#define MIN_PWM_HIGHTIME(x) ((x) << 0)
#define MIN_PWM_HIGHTIME_MASK 0xfff
#define MIN_PWM_HIGHTIME_SHIFT 0
#define MAX_PWM_HIGHTIME(x) ((x) << 12)
#define MAX_PWM_HIGHTIME_MASK (0xfff << 12)
#define MAX_PWM_HIGHTIME_SHIFT 12
#define FVTHROT_PWM_US_REG0 0x3064
#define FVTHROT_PWM_US_REG1 0x3068
#define FVTHROT_PWM_DS_REG0 0x306c
#define FVTHROT_PWM_DS_REG1 0x3070
#define FVTHROT_STATUS_REG0 0x3074
#define CURRENT_FEEDBACK_DIV_MASK 0xfff
#define CURRENT_FEEDBACK_DIV_SHIFT 0
#define FVTHROT_STATUS_REG1 0x3078
#define FVTHROT_STATUS_REG2 0x307c
#define CG_INTGFX_MISC 0x3080
#define FVTHROT_VBLANK_SEL (1 << 9)
#define FVTHROT_PWM_FEEDBACK_DIV_REG1 0x308c
#define RANGE0_PWM_FEEDBACK_DIV(x) ((x) << 0)
#define RANGE0_PWM_FEEDBACK_DIV_MASK 0xfff
#define RANGE0_PWM_FEEDBACK_DIV_SHIFT 0
#define RANGE_PWM_FEEDBACK_DIV_EN (1 << 12)
#define FVTHROT_PWM_FEEDBACK_DIV_REG2 0x3090
#define RANGE1_PWM_FEEDBACK_DIV(x) ((x) << 0)
#define RANGE1_PWM_FEEDBACK_DIV_MASK 0xfff
#define RANGE1_PWM_FEEDBACK_DIV_SHIFT 0
#define RANGE2_PWM_FEEDBACK_DIV(x) ((x) << 12)
#define RANGE2_PWM_FEEDBACK_DIV_MASK (0xfff << 12)
#define RANGE2_PWM_FEEDBACK_DIV_SHIFT 12
#define FVTHROT_PWM_FEEDBACK_DIV_REG3 0x3094
#define RANGE0_PWM(x) ((x) << 0)
#define RANGE0_PWM_MASK 0xfff
#define RANGE0_PWM_SHIFT 0
#define RANGE1_PWM(x) ((x) << 12)
#define RANGE1_PWM_MASK (0xfff << 12)
#define RANGE1_PWM_SHIFT 12
#define FVTHROT_PWM_FEEDBACK_DIV_REG4 0x3098
#define RANGE2_PWM(x) ((x) << 0)
#define RANGE2_PWM_MASK 0xfff
#define RANGE2_PWM_SHIFT 0
#define RANGE3_PWM(x) ((x) << 12)
#define RANGE3_PWM_MASK (0xfff << 12)
#define RANGE3_PWM_SHIFT 12
#define FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1 0x30ac
#define RANGE0_SLOW_CLK_FEEDBACK_DIV(x) ((x) << 0)
#define RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK 0xfff
#define RANGE0_SLOW_CLK_FEEDBACK_DIV_SHIFT 0
#define RANGE_SLOW_CLK_FEEDBACK_DIV_EN (1 << 12)
#define GFX_MACRO_BYPASS_CNTL 0x30c0
#define SPLL_BYPASS_CNTL (1 << 0)
#define UPLL_BYPASS_CNTL (1 << 1)
#endif
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