Commit 9e268beb authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (49 commits)
  [ARM] idle: clean up pm_idle calling, obey hlt_counter
  [ARM] S3C: Fix gpio-config off-by-one bug
  [ARM] S3C64XX: add to_irq() support for EINT() GPIO
  [ARM] S3C64XX: clock.c: fix typo in usb-host clock ctrlbit
  [ARM] S3C64XX: fix HCLK gate defines
  [ARM] Update mach-types
  [ARM] wire up rt_tgsigqueueinfo and perf_counter_open
  OMAP2 clock/powerdomain: off by 1 error in loop timeout comparisons
  OMAP3 SDRC: set FIXEDDELAY when disabling SDRC DLL
  OMAP3: Add support for DPLL3 divisor values higher than 2
  OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers
  OMAP3 SRAM: add more comments on the SRAM code
  OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change
  OMAP3 clock: add a short delay when lowering CORE clk rate
  OMAP3 clock: initialize SDRC timings at kernel start
  OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize
  [ARM] Add old Feroceon support to compressed/head.S
  [ARM] 5559/1: Limit the stack unwinding caused by a kthread exit
  [ARM] 5558/1: Add extra checks to ARM unwinder to avoid tracing corrupt stacks
  [ARM] 5557/1: Discard some ARM.ex*.*exit.text sections when !HOTPLUG or !HOTPLUG_CPU
  ...
parents 2e8b5a09 9ccdac36
...@@ -1369,6 +1369,27 @@ and is between 256 and 4096 characters. It is defined in the file ...@@ -1369,6 +1369,27 @@ and is between 256 and 4096 characters. It is defined in the file
min_addr=nn[KMG] [KNL,BOOT,ia64] All physical memory below this min_addr=nn[KMG] [KNL,BOOT,ia64] All physical memory below this
physical address is ignored. physical address is ignored.
mini2440= [ARM,HW,KNL]
Format:[0..2][b][c][t]
Default: "0tb"
MINI2440 configuration specification:
0 - The attached screen is the 3.5" TFT
1 - The attached screen is the 7" TFT
2 - The VGA Shield is attached (1024x768)
Leaving out the screen size parameter will not load
the TFT driver, and the framebuffer will be left
unconfigured.
b - Enable backlight. The TFT backlight pin will be
linked to the kernel VESA blanking code and a GPIO
LED. This parameter is not necessary when using the
VGA shield.
c - Enable the s3c camera interface.
t - Reserved for enabling touchscreen support. The
touchscreen support is not enabled in the mainstream
kernel as of 2.6.30, a preliminary port can be found
in the "bleeding edge" mini2440 support kernel at
http://repo.or.cz/w/linux-2.6/mini2440.git
mminit_loglevel= mminit_loglevel=
[KNL] When CONFIG_DEBUG_MEMORY_INIT is set, this [KNL] When CONFIG_DEBUG_MEMORY_INIT is set, this
parameter allows control of the logging verbosity for parameter allows control of the logging verbosity for
......
...@@ -653,6 +653,8 @@ M: laforge@openezx.org ...@@ -653,6 +653,8 @@ M: laforge@openezx.org
L: openezx-devel@lists.openezx.org (subscribers-only) L: openezx-devel@lists.openezx.org (subscribers-only)
W: http://www.openezx.org/ W: http://www.openezx.org/
S: Maintained S: Maintained
T: topgit git://git.openezx.org/openezx.git
F: arch/arm/mach-pxa/ezx.c
ARM/FARADAY FA526 PORT ARM/FARADAY FA526 PORT
P: Paulius Zaleckas P: Paulius Zaleckas
...@@ -774,11 +776,25 @@ P: Philipp Zabel ...@@ -774,11 +776,25 @@ P: Philipp Zabel
M: philipp.zabel@gmail.com M: philipp.zabel@gmail.com
S: Maintained S: Maintained
ARM/MIOA701 MACHINE SUPPORT
P: Robert Jarzmik
M: robert.jarzmik@free.fr
L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
F: arch/arm/mach-pxa/mioa701.c
S: Maintained
ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT
P: Michael Petchkovsky P: Michael Petchkovsky
M: mkpetch@internode.on.net M: mkpetch@internode.on.net
S: Maintained S: Maintained
ARM/OPENMOKO NEO FREERUNNER (GTA02) MACHINE SUPPORT
P: Nelson Castillo
M: arhuaco@freaks-unidos.net
L: openmoko-kernel@lists.openmoko.org (subscribers-only)
W: http://wiki.openmoko.org/wiki/Neo_FreeRunner
S: Supported
ARM/TOSA MACHINE SUPPORT ARM/TOSA MACHINE SUPPORT
P: Dmitry Eremin-Solenikov P: Dmitry Eremin-Solenikov
M: dbaryshkov@gmail.com M: dbaryshkov@gmail.com
...@@ -792,6 +808,12 @@ M: marek.vasut@gmail.com ...@@ -792,6 +808,12 @@ M: marek.vasut@gmail.com
W: http://hackndev.com W: http://hackndev.com
S: Maintained S: Maintained
ARM/PALM TREO 680 SUPPORT
P: Tomas Cech
M: sleep_walker@suse.cz
W: http://hackndev.com
S: Maintained
ARM/PALMZ72 SUPPORT ARM/PALMZ72 SUPPORT
P: Sergey Lapin P: Sergey Lapin
M: slapin@ossfans.org M: slapin@ossfans.org
......
...@@ -1241,7 +1241,7 @@ endmenu ...@@ -1241,7 +1241,7 @@ endmenu
menu "CPU Power Management" menu "CPU Power Management"
if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA) if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA || ARCH_S3C64XX)
source "drivers/cpufreq/Kconfig" source "drivers/cpufreq/Kconfig"
...@@ -1272,6 +1272,10 @@ config CPU_FREQ_PXA ...@@ -1272,6 +1272,10 @@ config CPU_FREQ_PXA
default y default y
select CPU_FREQ_DEFAULT_GOV_USERSPACE select CPU_FREQ_DEFAULT_GOV_USERSPACE
config CPU_FREQ_S3C64XX
bool "CPUfreq support for Samsung S3C64XX CPUs"
depends on CPU_FREQ && CPU_S3C6410
endif endif
source "drivers/cpuidle/Kconfig" source "drivers/cpuidle/Kconfig"
......
...@@ -674,6 +674,15 @@ proc_types: ...@@ -674,6 +674,15 @@ proc_types:
b __armv4_mmu_cache_off b __armv4_mmu_cache_off
b __armv5tej_mmu_cache_flush b __armv5tej_mmu_cache_flush
#ifdef CONFIG_CPU_FEROCEON_OLD_ID
/* this conflicts with the standard ARMv5TE entry */
.long 0x41009260 @ Old Feroceon
.long 0xff00fff0
b __armv4_mmu_cache_on
b __armv4_mmu_cache_off
b __armv5tej_mmu_cache_flush
#endif
.word 0x66015261 @ FA526 .word 0x66015261 @ FA526
.word 0xff01fff1 .word 0xff01fff1
b __fa526_cache_on b __fa526_cache_on
......
...@@ -117,7 +117,7 @@ static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val) ...@@ -117,7 +117,7 @@ static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
u32 val; u32 val;
spin_lock(&irq_controller_lock); spin_lock(&irq_controller_lock);
irq_desc[irq].cpu = cpu; irq_desc[irq].node = cpu;
val = readl(reg) & ~(0xff << shift); val = readl(reg) & ~(0xff << shift);
val |= 1 << (cpu + shift); val |= 1 << (cpu + shift);
writel(val, reg); writel(val, reg);
......
...@@ -229,14 +229,18 @@ static int vic_set_wake(unsigned int irq, unsigned int on) ...@@ -229,14 +229,18 @@ static int vic_set_wake(unsigned int irq, unsigned int on)
{ {
struct vic_device *v = vic_from_irq(irq); struct vic_device *v = vic_from_irq(irq);
unsigned int off = irq & 31; unsigned int off = irq & 31;
u32 bit = 1 << off;
if (!v) if (!v)
return -EINVAL; return -EINVAL;
if (!(bit & v->resume_sources))
return -EINVAL;
if (on) if (on)
v->resume_irqs |= 1 << off; v->resume_irqs |= bit;
else else
v->resume_irqs &= ~(1 << off); v->resume_irqs &= ~bit;
return 0; return 0;
} }
......
This diff is collapsed.
...@@ -389,6 +389,8 @@ ...@@ -389,6 +389,8 @@
#define __NR_inotify_init1 (__NR_SYSCALL_BASE+360) #define __NR_inotify_init1 (__NR_SYSCALL_BASE+360)
#define __NR_preadv (__NR_SYSCALL_BASE+361) #define __NR_preadv (__NR_SYSCALL_BASE+361)
#define __NR_pwritev (__NR_SYSCALL_BASE+362) #define __NR_pwritev (__NR_SYSCALL_BASE+362)
#define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE+363)
#define __NR_perf_counter_open (__NR_SYSCALL_BASE+364)
/* /*
* The following SWIs are ARM private. * The following SWIs are ARM private.
......
...@@ -372,6 +372,8 @@ ...@@ -372,6 +372,8 @@
/* 360 */ CALL(sys_inotify_init1) /* 360 */ CALL(sys_inotify_init1)
CALL(sys_preadv) CALL(sys_preadv)
CALL(sys_pwritev) CALL(sys_pwritev)
CALL(sys_rt_tgsigqueueinfo)
CALL(sys_perf_counter_open)
#ifndef syscalls_counted #ifndef syscalls_counted
.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
#define syscalls_counted #define syscalls_counted
......
...@@ -167,7 +167,7 @@ void __init init_IRQ(void) ...@@ -167,7 +167,7 @@ void __init init_IRQ(void)
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
cpumask_setall(bad_irq_desc.affinity); cpumask_setall(bad_irq_desc.affinity);
bad_irq_desc.cpu = smp_processor_id(); bad_irq_desc.node = smp_processor_id();
#endif #endif
init_arch_irq(); init_arch_irq();
} }
...@@ -176,7 +176,7 @@ void __init init_IRQ(void) ...@@ -176,7 +176,7 @@ void __init init_IRQ(void)
static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu) static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
{ {
pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->cpu, cpu); pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->node, cpu);
spin_lock_irq(&desc->lock); spin_lock_irq(&desc->lock);
desc->chip->set_affinity(irq, cpumask_of(cpu)); desc->chip->set_affinity(irq, cpumask_of(cpu));
...@@ -195,7 +195,7 @@ void migrate_irqs(void) ...@@ -195,7 +195,7 @@ void migrate_irqs(void)
for (i = 0; i < NR_IRQS; i++) { for (i = 0; i < NR_IRQS; i++) {
struct irq_desc *desc = irq_desc + i; struct irq_desc *desc = irq_desc + i;
if (desc->cpu == cpu) { if (desc->node == cpu) {
unsigned int newcpu = cpumask_any_and(desc->affinity, unsigned int newcpu = cpumask_any_and(desc->affinity,
cpu_online_mask); cpu_online_mask);
if (newcpu >= nr_cpu_ids) { if (newcpu >= nr_cpu_ids) {
......
...@@ -114,9 +114,6 @@ void arm_machine_restart(char mode, const char *cmd) ...@@ -114,9 +114,6 @@ void arm_machine_restart(char mode, const char *cmd)
/* /*
* Function pointers to optional machine specific functions * Function pointers to optional machine specific functions
*/ */
void (*pm_idle)(void);
EXPORT_SYMBOL(pm_idle);
void (*pm_power_off)(void); void (*pm_power_off)(void);
EXPORT_SYMBOL(pm_power_off); EXPORT_SYMBOL(pm_power_off);
...@@ -130,20 +127,19 @@ EXPORT_SYMBOL_GPL(arm_pm_restart); ...@@ -130,20 +127,19 @@ EXPORT_SYMBOL_GPL(arm_pm_restart);
*/ */
static void default_idle(void) static void default_idle(void)
{ {
if (hlt_counter)
cpu_relax();
else {
local_irq_disable();
if (!need_resched()) if (!need_resched())
arch_idle(); arch_idle();
local_irq_enable(); local_irq_enable();
}
} }
void (*pm_idle)(void) = default_idle;
EXPORT_SYMBOL(pm_idle);
/* /*
* The idle thread. We try to conserve power, while trying to keep * The idle thread, has rather strange semantics for calling pm_idle,
* overall latency low. The architecture specific idle is passed * but this is what x86 does and we need to do the same, so that
* a value to indicate the level of "idleness" of the system. * things like cpuidle get called in the same way. The only difference
* is that we always respect 'hlt_counter' to prevent low power idle.
*/ */
void cpu_idle(void) void cpu_idle(void)
{ {
...@@ -151,21 +147,31 @@ void cpu_idle(void) ...@@ -151,21 +147,31 @@ void cpu_idle(void)
/* endless idle loop with no priority at all */ /* endless idle loop with no priority at all */
while (1) { while (1) {
void (*idle)(void) = pm_idle; tick_nohz_stop_sched_tick(1);
#ifdef CONFIG_HOTPLUG_CPU
if (cpu_is_offline(smp_processor_id())) {
leds_event(led_idle_start); leds_event(led_idle_start);
while (!need_resched()) {
#ifdef CONFIG_HOTPLUG_CPU
if (cpu_is_offline(smp_processor_id()))
cpu_die(); cpu_die();
}
#endif #endif
if (!idle) local_irq_disable();
idle = default_idle; if (hlt_counter) {
leds_event(led_idle_start); local_irq_enable();
tick_nohz_stop_sched_tick(1); cpu_relax();
while (!need_resched()) } else {
idle(); stop_critical_timings();
pm_idle();
start_critical_timings();
/*
* This will eventually be removed - pm_idle
* functions should always return with IRQs
* enabled.
*/
WARN_ON(irqs_disabled());
local_irq_enable();
}
}
leds_event(led_idle_end); leds_event(led_idle_end);
tick_nohz_restart_sched_tick(); tick_nohz_restart_sched_tick();
preempt_enable_no_resched(); preempt_enable_no_resched();
...@@ -352,6 +358,23 @@ asm( ".section .text\n" ...@@ -352,6 +358,23 @@ asm( ".section .text\n"
" .size kernel_thread_helper, . - kernel_thread_helper\n" " .size kernel_thread_helper, . - kernel_thread_helper\n"
" .previous"); " .previous");
#ifdef CONFIG_ARM_UNWIND
extern void kernel_thread_exit(long code);
asm( ".section .text\n"
" .align\n"
" .type kernel_thread_exit, #function\n"
"kernel_thread_exit:\n"
" .fnstart\n"
" .cantunwind\n"
" bl do_exit\n"
" nop\n"
" .fnend\n"
" .size kernel_thread_exit, . - kernel_thread_exit\n"
" .previous");
#else
#define kernel_thread_exit do_exit
#endif
/* /*
* Create a kernel thread. * Create a kernel thread.
*/ */
...@@ -363,7 +386,7 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags) ...@@ -363,7 +386,7 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
regs.ARM_r1 = (unsigned long)arg; regs.ARM_r1 = (unsigned long)arg;
regs.ARM_r2 = (unsigned long)fn; regs.ARM_r2 = (unsigned long)fn;
regs.ARM_r3 = (unsigned long)do_exit; regs.ARM_r3 = (unsigned long)kernel_thread_exit;
regs.ARM_pc = (unsigned long)kernel_thread_helper; regs.ARM_pc = (unsigned long)kernel_thread_helper;
regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE; regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE;
......
...@@ -212,6 +212,7 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl) ...@@ -212,6 +212,7 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
ctrl->vrs[14] = *vsp++; ctrl->vrs[14] = *vsp++;
ctrl->vrs[SP] = (unsigned long)vsp; ctrl->vrs[SP] = (unsigned long)vsp;
} else if (insn == 0xb0) { } else if (insn == 0xb0) {
if (ctrl->vrs[PC] == 0)
ctrl->vrs[PC] = ctrl->vrs[LR]; ctrl->vrs[PC] = ctrl->vrs[LR];
/* no further processing */ /* no further processing */
ctrl->entries = 0; ctrl->entries = 0;
...@@ -309,18 +310,20 @@ int unwind_frame(struct stackframe *frame) ...@@ -309,18 +310,20 @@ int unwind_frame(struct stackframe *frame)
} }
while (ctrl.entries > 0) { while (ctrl.entries > 0) {
int urc; int urc = unwind_exec_insn(&ctrl);
if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= high)
return -URC_FAILURE;
urc = unwind_exec_insn(&ctrl);
if (urc < 0) if (urc < 0)
return urc; return urc;
if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= high)
return -URC_FAILURE;
} }
if (ctrl.vrs[PC] == 0) if (ctrl.vrs[PC] == 0)
ctrl.vrs[PC] = ctrl.vrs[LR]; ctrl.vrs[PC] = ctrl.vrs[LR];
/* check for infinite loop */
if (frame->pc == ctrl.vrs[PC])
return -URC_FAILURE;
frame->fp = ctrl.vrs[FP]; frame->fp = ctrl.vrs[FP];
frame->sp = ctrl.vrs[SP]; frame->sp = ctrl.vrs[SP];
frame->lr = ctrl.vrs[LR]; frame->lr = ctrl.vrs[LR];
...@@ -332,7 +335,6 @@ int unwind_frame(struct stackframe *frame) ...@@ -332,7 +335,6 @@ int unwind_frame(struct stackframe *frame)
void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk) void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk)
{ {
struct stackframe frame; struct stackframe frame;
unsigned long high, low;
register unsigned long current_sp asm ("sp"); register unsigned long current_sp asm ("sp");
pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk); pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk);
...@@ -362,9 +364,6 @@ void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk) ...@@ -362,9 +364,6 @@ void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk)
frame.pc = thread_saved_pc(tsk); frame.pc = thread_saved_pc(tsk);
} }
low = frame.sp & ~(THREAD_SIZE - 1);
high = low + THREAD_SIZE;
while (1) { while (1) {
int urc; int urc;
unsigned long where = frame.pc; unsigned long where = frame.pc;
......
...@@ -84,6 +84,14 @@ SECTIONS ...@@ -84,6 +84,14 @@ SECTIONS
*(.exitcall.exit) *(.exitcall.exit)
*(.ARM.exidx.exit.text) *(.ARM.exidx.exit.text)
*(.ARM.extab.exit.text) *(.ARM.extab.exit.text)
#ifndef CONFIG_HOTPLUG_CPU
*(.ARM.exidx.cpuexit.text)
*(.ARM.extab.cpuexit.text)
#endif
#ifndef CONFIG_HOTPLUG
*(.ARM.exidx.devexit.text)
*(.ARM.extab.devexit.text)
#endif
#ifndef CONFIG_MMU #ifndef CONFIG_MMU
*(.fixup) *(.fixup)
*(__ex_table) *(__ex_table)
......
...@@ -302,7 +302,7 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) ...@@ -302,7 +302,7 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
udelay(1); udelay(1);
} }
if (i < MAX_CLOCK_ENABLE_WAIT) if (i <= MAX_CLOCK_ENABLE_WAIT)
pr_debug("Clock %s stable after %d loops\n", name, i); pr_debug("Clock %s stable after %d loops\n", name, i);
else else
printk(KERN_ERR "Clock %s didn't enable in %d tries\n", printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
......
...@@ -286,6 +286,20 @@ static struct omap_clk omap34xx_clks[] = { ...@@ -286,6 +286,20 @@ static struct omap_clk omap34xx_clks[] = {
#define MIN_SDRC_DLL_LOCK_FREQ 83000000 #define MIN_SDRC_DLL_LOCK_FREQ 83000000
#define CYCLES_PER_MHZ 1000000
/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
#define SDRC_MPURATE_SCALE 8
/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
#define SDRC_MPURATE_BASE_SHIFT 9
/*
* SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
* 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
*/
#define SDRC_MPURATE_LOOPS 96
/** /**
* omap3_dpll_recalc - recalculate DPLL rate * omap3_dpll_recalc - recalculate DPLL rate
* @clk: DPLL struct clk * @clk: DPLL struct clk
...@@ -709,7 +723,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) ...@@ -709,7 +723,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
{ {
u32 new_div = 0; u32 new_div = 0;
u32 unlock_dll = 0; u32 unlock_dll = 0;
unsigned long validrate, sdrcrate; u32 c;
unsigned long validrate, sdrcrate, mpurate;
struct omap_sdrc_params *sp; struct omap_sdrc_params *sp;
if (!clk || !rate) if (!clk || !rate)
...@@ -718,18 +733,15 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) ...@@ -718,18 +733,15 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
if (clk != &dpll3_m2_ck) if (clk != &dpll3_m2_ck)
return -EINVAL; return -EINVAL;
if (rate == clk->rate)
return 0;
validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
if (validrate != rate) if (validrate != rate)
return -EINVAL; return -EINVAL;
sdrcrate = sdrc_ick.rate; sdrcrate = sdrc_ick.rate;
if (rate > clk->rate) if (rate > clk->rate)
sdrcrate <<= ((rate / clk->rate) - 1); sdrcrate <<= ((rate / clk->rate) >> 1);
else else
sdrcrate >>= ((clk->rate / rate) - 1); sdrcrate >>= ((clk->rate / rate) >> 1);
sp = omap2_sdrc_get_params(sdrcrate); sp = omap2_sdrc_get_params(sdrcrate);
if (!sp) if (!sp)
...@@ -740,17 +752,25 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) ...@@ -740,17 +752,25 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
unlock_dll = 1; unlock_dll = 1;
} }
/*
* XXX This only needs to be done when the CPU frequency changes
*/
mpurate = arm_fck.rate / CYCLES_PER_MHZ;
c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
c += 1; /* for safety */
c *= SDRC_MPURATE_LOOPS;
c >>= SDRC_MPURATE_SCALE;
if (c == 0)
c = 1;
pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
validrate); validrate);
pr_debug("clock: SDRC timing params used: %08x %08x %08x\n", pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb); sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
/* REVISIT: SRAM code doesn't support other M2 divisors yet */
WARN_ON(new_div != 1 && new_div != 2);
/* REVISIT: Add SDRC_MR changing to this code also */
omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
sp->actim_ctrlb, new_div, unlock_dll); sp->actim_ctrlb, new_div, unlock_dll, c,
sp->mr, rate > clk->rate);
return 0; return 0;
} }
......
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/clk.h>
#include <asm/tlb.h> #include <asm/tlb.h>
...@@ -241,6 +242,40 @@ void __init omap2_map_common_io(void) ...@@ -241,6 +242,40 @@ void __init omap2_map_common_io(void)
omapfb_reserve_sdram(); omapfb_reserve_sdram();
} }
/*
* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
*
* Sets the CORE DPLL3 M2 divider to the same value that it's at
* currently. This has the effect of setting the SDRC SDRAM AC timing
* registers to the values currently defined by the kernel. Currently
* only defined for OMAP3; will return 0 if called on OMAP2. Returns
* -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
* or passes along the return value of clk_set_rate().
*/
static int __init _omap2_init_reprogram_sdrc(void)
{
struct clk *dpll3_m2_ck;
int v = -EINVAL;
long rate;
if (!cpu_is_omap34xx())
return 0;
dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
if (!dpll3_m2_ck)
return -EINVAL;
rate = clk_get_rate(dpll3_m2_ck);
pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
v = clk_set_rate(dpll3_m2_ck, rate);
if (v)
pr_err("dpll3_m2_clk rate change failed: %d\n", v);
clk_put(dpll3_m2_ck);
return v;
}
void __init omap2_init_common_hw(struct omap_sdrc_params *sp) void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
{ {
omap2_mux_init(); omap2_mux_init();
...@@ -249,6 +284,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sp) ...@@ -249,6 +284,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
omap2_clk_init(); omap2_clk_init();
omap2_sdrc_init(sp); omap2_sdrc_init(sp);
_omap2_init_reprogram_sdrc();
#endif #endif
gpmc_init(); gpmc_init();
} }
...@@ -1099,7 +1099,7 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm) ...@@ -1099,7 +1099,7 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
(c++ < PWRDM_TRANSITION_BAILOUT)) (c++ < PWRDM_TRANSITION_BAILOUT))
udelay(1); udelay(1);
if (c >= PWRDM_TRANSITION_BAILOUT) { if (c > PWRDM_TRANSITION_BAILOUT) {
printk(KERN_ERR "powerdomain: waited too long for " printk(KERN_ERR "powerdomain: waited too long for "
"powerdomain %s to complete transition\n", pwrdm->name); "powerdomain %s to complete transition\n", pwrdm->name);
return -EAGAIN; return -EAGAIN;
......
...@@ -3,13 +3,12 @@ ...@@ -3,13 +3,12 @@
* *
* Omap3 specific functions that need to be run in internal SRAM * Omap3 specific functions that need to be run in internal SRAM
* *
* (C) Copyright 2007 * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
* Texas Instruments Inc. * Copyright (C) 2008 Nokia Corporation
* Rajendra Nayak <rnayak@ti.com>
* *
* (C) Copyright 2004 * Rajendra Nayak <rnayak@ti.com>
* Texas Instruments, <www.ti.com>
* Richard Woodruff <r-woodruff2@ti.com> * Richard Woodruff <r-woodruff2@ti.com>
* Paul Walmsley
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as * modify it under the terms of the GNU General Public License as
...@@ -37,61 +36,112 @@ ...@@ -37,61 +36,112 @@
.text .text
/* r4 parameters */
#define SDRC_NO_UNLOCK_DLL 0x0
#define SDRC_UNLOCK_DLL 0x1
/* SDRC_DLLA_CTRL bit settings */
#define FIXEDDELAY_SHIFT 24
#define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT)
#define DLLIDLE_MASK 0x4
/*
* SDRC_DLLA_CTRL default values: TI hardware team indicates that
* FIXEDDELAY should be initialized to 0xf. This apparently was
* empirically determined during process testing, so no derivation
* was provided.
*/
#define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT)
/* SDRC_DLLA_STATUS bit settings */
#define LOCKSTATUS_MASK 0x4
/* SDRC_POWER bit settings */
#define SRFRONIDLEREQ_MASK 0x40
#define PWDENA_MASK 0x4
/* CM_IDLEST1_CORE bit settings */
#define ST_SDRC_MASK 0x2
/* CM_ICLKEN1_CORE bit settings */
#define EN_SDRC_MASK 0x2
/* CM_CLKSEL1_PLL bit settings */
#define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b
/* /*
* Change frequency of core dpll * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
* r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2 * r0 = new SDRC_RFR_CTRL register contents
* r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for * r1 = new SDRC_ACTIM_CTRLA register contents
* r2 = new SDRC_ACTIM_CTRLB register contents
* r3 = new M2 divider setting (only 1 and 2 supported right now)
* r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
* SDRC rates < 83MHz * SDRC rates < 83MHz
* r5 = number of MPU cycles to wait for SDRC to stabilize after
* reprogramming the SDRC when switching to a slower MPU speed
* r6 = new SDRC_MR_0 register value
* r7 = increasing SDRC rate? (1 = yes, 0 = no)
*
*/ */
ENTRY(omap3_sram_configure_core_dpll) ENTRY(omap3_sram_configure_core_dpll)
stmfd sp!, {r1-r12, lr} @ store regs to stack stmfd sp!, {r1-r12, lr} @ store regs to stack
ldr r4, [sp, #52] @ pull extra args off the stack ldr r4, [sp, #52] @ pull extra args off the stack
ldr r5, [sp, #56] @ load extra args from the stack
ldr r6, [sp, #60] @ load extra args from the stack
ldr r7, [sp, #64] @ load extra args from the stack
dsb @ flush buffered writes to interconnect dsb @ flush buffered writes to interconnect
cmp r3, #0x2 cmp r7, #1 @ if increasing SDRC clk rate,
blne configure_sdrc bleq configure_sdrc @ program the SDRC regs early (for RFR)
cmp r4, #0x1 cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state
bleq unlock_dll bleq unlock_dll
blne lock_dll blne lock_dll
bl sdram_in_selfrefresh @ put the SDRAM in self refresh bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
bl configure_core_dpll bl configure_core_dpll @ change the DPLL3 M2 divider
bl enable_sdrc bl enable_sdrc @ take SDRC out of idle
cmp r4, #0x1 cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change
bleq wait_dll_unlock bleq wait_dll_unlock
blne wait_dll_lock blne wait_dll_lock
cmp r3, #0x1 cmp r7, #1 @ if increasing SDRC clk rate,
blne configure_sdrc beq return_to_sdram @ return to SDRAM code, otherwise,
bl configure_sdrc @ reprogram SDRC regs now
mov r12, r5
bl wait_clk_stable @ wait for SDRC to stabilize
return_to_sdram:
isb @ prevent speculative exec past here isb @ prevent speculative exec past here
mov r0, #0 @ return value mov r0, #0 @ return value
ldmfd sp!, {r1-r12, pc} @ restore regs and return ldmfd sp!, {r1-r12, pc} @ restore regs and return
unlock_dll: unlock_dll:
ldr r11, omap3_sdrc_dlla_ctrl ldr r11, omap3_sdrc_dlla_ctrl
ldr r12, [r11] ldr r12, [r11]
orr r12, r12, #0x4 and r12, r12, #FIXEDDELAY_MASK
orr r12, r12, #FIXEDDELAY_DEFAULT
orr r12, r12, #DLLIDLE_MASK
str r12, [r11] @ (no OCP barrier needed) str r12, [r11] @ (no OCP barrier needed)
bx lr bx lr
lock_dll: lock_dll:
ldr r11, omap3_sdrc_dlla_ctrl ldr r11, omap3_sdrc_dlla_ctrl
ldr r12, [r11] ldr r12, [r11]
bic r12, r12, #0x4 bic r12, r12, #DLLIDLE_MASK
str r12, [r11] @ (no OCP barrier needed) str r12, [r11] @ (no OCP barrier needed)
bx lr bx lr
sdram_in_selfrefresh: sdram_in_selfrefresh:
ldr r11, omap3_sdrc_power @ read the SDRC_POWER register ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
ldr r12, [r11] @ read the contents of SDRC_POWER ldr r12, [r11] @ read the contents of SDRC_POWER
mov r9, r12 @ keep a copy of SDRC_POWER bits mov r9, r12 @ keep a copy of SDRC_POWER bits
orr r12, r12, #0x40 @ enable self refresh on idle req orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
bic r12, r12, #0x4 @ clear PWDENA bic r12, r12, #PWDENA_MASK @ clear PWDENA
str r12, [r11] @ write back to SDRC_POWER register str r12, [r11] @ write back to SDRC_POWER register
ldr r12, [r11] @ posted-write barrier for SDRC ldr r12, [r11] @ posted-write barrier for SDRC
idle_sdrc:
ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
ldr r12, [r11] ldr r12, [r11]
bic r12, r12, #0x2 @ disable iclk bit for SDRC bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC
str r12, [r11] str r12, [r11]
wait_sdrc_idle: wait_sdrc_idle:
ldr r11, omap3_cm_idlest1_core ldr r11, omap3_cm_idlest1_core
ldr r12, [r11] ldr r12, [r11]
and r12, r12, #0x2 @ check for SDRC idle and r12, r12, #ST_SDRC_MASK @ check for SDRC idle
cmp r12, #2 cmp r12, #ST_SDRC_MASK
bne wait_sdrc_idle bne wait_sdrc_idle
bx lr bx lr
configure_core_dpll: configure_core_dpll:
...@@ -99,36 +149,23 @@ configure_core_dpll: ...@@ -99,36 +149,23 @@ configure_core_dpll:
ldr r12, [r11] ldr r12, [r11]
ldr r10, core_m2_mask_val @ modify m2 for core dpll ldr r10, core_m2_mask_val @ modify m2 for core dpll
and r12, r12, r10 and r12, r12, r10
orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
str r12, [r11] str r12, [r11]
ldr r12, [r11] @ posted-write barrier for CM ldr r12, [r11] @ posted-write barrier for CM
mov r12, #0x800 @ wait for the clock to stabilise
cmp r3, #2
bne wait_clk_stable
bx lr bx lr
wait_clk_stable: wait_clk_stable:
subs r12, r12, #1 subs r12, r12, #1
bne wait_clk_stable bne wait_clk_stable
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
bx lr bx lr
enable_sdrc: enable_sdrc:
ldr r11, omap3_cm_iclken1_core ldr r11, omap3_cm_iclken1_core
ldr r12, [r11] ldr r12, [r11]
orr r12, r12, #0x2 @ enable iclk bit for SDRC orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC
str r12, [r11] str r12, [r11]
wait_sdrc_idle1: wait_sdrc_idle1:
ldr r11, omap3_cm_idlest1_core ldr r11, omap3_cm_idlest1_core
ldr r12, [r11] ldr r12, [r11]
and r12, r12, #0x2 and r12, r12, #ST_SDRC_MASK
cmp r12, #0 cmp r12, #0
bne wait_sdrc_idle1 bne wait_sdrc_idle1
restore_sdrc_power_val: restore_sdrc_power_val:
...@@ -138,14 +175,14 @@ restore_sdrc_power_val: ...@@ -138,14 +175,14 @@ restore_sdrc_power_val:
wait_dll_lock: wait_dll_lock:
ldr r11, omap3_sdrc_dlla_status ldr r11, omap3_sdrc_dlla_status
ldr r12, [r11] ldr r12, [r11]
and r12, r12, #0x4 and r12, r12, #LOCKSTATUS_MASK
cmp r12, #0x4 cmp r12, #LOCKSTATUS_MASK
bne wait_dll_lock bne wait_dll_lock
bx lr bx lr
wait_dll_unlock: wait_dll_unlock:
ldr r11, omap3_sdrc_dlla_status ldr r11, omap3_sdrc_dlla_status
ldr r12, [r11] ldr r12, [r11]
and r12, r12, #0x4 and r12, r12, #LOCKSTATUS_MASK
cmp r12, #0x0 cmp r12, #0x0
bne wait_dll_unlock bne wait_dll_unlock
bx lr bx lr
...@@ -156,7 +193,9 @@ configure_sdrc: ...@@ -156,7 +193,9 @@ configure_sdrc:
str r1, [r11] str r1, [r11]
ldr r11, omap3_sdrc_actim_ctrlb ldr r11, omap3_sdrc_actim_ctrlb
str r2, [r11] str r2, [r11]
ldr r2, [r11] @ posted-write barrier for SDRC ldr r11, omap3_sdrc_mr_0
str r6, [r11]
ldr r6, [r11] @ posted-write barrier for SDRC
bx lr bx lr
omap3_sdrc_power: omap3_sdrc_power:
...@@ -173,6 +212,8 @@ omap3_sdrc_actim_ctrla: ...@@ -173,6 +212,8 @@ omap3_sdrc_actim_ctrla:
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0) .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
omap3_sdrc_actim_ctrlb: omap3_sdrc_actim_ctrlb:
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0) .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
omap3_sdrc_mr_0:
.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
omap3_sdrc_dlla_status: omap3_sdrc_dlla_status:
.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
omap3_sdrc_dlla_ctrl: omap3_sdrc_dlla_ctrl:
......
...@@ -200,6 +200,6 @@ void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) ...@@ -200,6 +200,6 @@ void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
int __init orion5x_setup_sram_win(void) int __init orion5x_setup_sram_win(void)
{ {
return setup_cpu_win(win_alloc_count, ORION5X_SRAM_PHYS_BASE, return setup_cpu_win(win_alloc_count++, ORION5X_SRAM_PHYS_BASE,
ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1);
} }
...@@ -562,7 +562,7 @@ static struct platform_device orion5x_crypto_device = { ...@@ -562,7 +562,7 @@ static struct platform_device orion5x_crypto_device = {
.resource = orion5x_crypto_res, .resource = orion5x_crypto_res,
}; };
int __init orion5x_crypto_init(void) static int __init orion5x_crypto_init(void)
{ {
int ret; int ret;
...@@ -696,6 +696,14 @@ void __init orion5x_init(void) ...@@ -696,6 +696,14 @@ void __init orion5x_init(void)
disable_hlt(); disable_hlt();
} }
/*
* The 5082/5181l/5182/6082/6082l/6183 have crypto
* while 5180n/5181/5281 don't have crypto.
*/
if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
orion5x_crypto_init();
/* /*
* Register watchdog driver * Register watchdog driver
*/ */
......
...@@ -38,7 +38,6 @@ void orion5x_spi_init(void); ...@@ -38,7 +38,6 @@ void orion5x_spi_init(void);
void orion5x_uart0_init(void); void orion5x_uart0_init(void);
void orion5x_uart1_init(void); void orion5x_uart1_init(void);
void orion5x_xor_init(void); void orion5x_xor_init(void);
int orion5x_crypto_init(void);
/* /*
* PCIe/PCI functions. * PCIe/PCI functions.
......
...@@ -401,6 +401,16 @@ config MACH_PALMZ72 ...@@ -401,6 +401,16 @@ config MACH_PALMZ72
Say Y here if you intend to run this kernel on Palm Zire 72 Say Y here if you intend to run this kernel on Palm Zire 72
handheld computer. handheld computer.
config MACH_TREO680
bool "Palm Treo 680"
default y
depends on ARCH_PXA_PALM
select PXA27x
select IWMMXT
help
Say Y here if you intend to run this kernel on Palm Treo 680
smartphone.
config MACH_PALMLD config MACH_PALMLD
bool "Palm LifeDrive" bool "Palm LifeDrive"
default y default y
......
...@@ -62,6 +62,7 @@ obj-$(CONFIG_MACH_PALMT5) += palmt5.o ...@@ -62,6 +62,7 @@ obj-$(CONFIG_MACH_PALMT5) += palmt5.o
obj-$(CONFIG_MACH_PALMTX) += palmtx.o obj-$(CONFIG_MACH_PALMTX) += palmtx.o
obj-$(CONFIG_MACH_PALMLD) += palmld.o obj-$(CONFIG_MACH_PALMLD) += palmld.o
obj-$(CONFIG_MACH_PALMZ72) += palmz72.o obj-$(CONFIG_MACH_PALMZ72) += palmz72.o
obj-$(CONFIG_MACH_TREO680) += treo680.o
obj-$(CONFIG_ARCH_VIPER) += viper.o obj-$(CONFIG_ARCH_VIPER) += viper.o
ifeq ($(CONFIG_MACH_ZYLONITE),y) ifeq ($(CONFIG_MACH_ZYLONITE),y)
......
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
#include <linux/pm.h> #include <linux/pm.h>
#include <linux/gpio.h> #include <linux/gpio.h>
#include <linux/backlight.h> #include <linux/backlight.h>
#include <linux/i2c.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/spi/spi.h> #include <linux/spi/spi.h>
#include <linux/spi/ads7846.h> #include <linux/spi/ads7846.h>
...@@ -600,6 +601,10 @@ static struct platform_device *devices[] __initdata = { ...@@ -600,6 +601,10 @@ static struct platform_device *devices[] __initdata = {
&sharpsl_rom_device, &sharpsl_rom_device,
}; };
static struct i2c_board_info __initdata corgi_i2c_devices[] = {
{ I2C_BOARD_INFO("wm8731", 0x1b) },
};
static void corgi_poweroff(void) static void corgi_poweroff(void)
{ {
if (!machine_is_corgi()) if (!machine_is_corgi())
...@@ -634,6 +639,7 @@ static void __init corgi_init(void) ...@@ -634,6 +639,7 @@ static void __init corgi_init(void)
pxa_set_mci_info(&corgi_mci_platform_data); pxa_set_mci_info(&corgi_mci_platform_data);
pxa_set_ficp_info(&corgi_ficp_platform_data); pxa_set_ficp_info(&corgi_ficp_platform_data);
pxa_set_i2c_info(NULL); pxa_set_i2c_info(NULL);
i2c_register_board_info(0, ARRAY_AND_SIZE(corgi_i2c_devices));
platform_scoop_config = &corgi_pcmcia_config; platform_scoop_config = &corgi_pcmcia_config;
......
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
#include <linux/apm-emulation.h> #include <linux/apm-emulation.h>
#include <linux/i2c.h> #include <linux/i2c.h>
#include <linux/i2c/pca953x.h> #include <linux/i2c/pca953x.h>
#include <linux/regulator/userspace-consumer.h>
#include <media/soc_camera.h> #include <media/soc_camera.h>
...@@ -735,6 +736,7 @@ static struct pxa2xx_spi_chip em_x270_libertas_chip = { ...@@ -735,6 +736,7 @@ static struct pxa2xx_spi_chip em_x270_libertas_chip = {
.rx_threshold = 1, .rx_threshold = 1,
.tx_threshold = 1, .tx_threshold = 1,
.timeout = 1000, .timeout = 1000,
.gpio_cs = 14,
}; };
static unsigned long em_x270_libertas_pin_config[] = { static unsigned long em_x270_libertas_pin_config[] = {
...@@ -803,7 +805,6 @@ static int em_x270_libertas_teardown(struct spi_device *spi) ...@@ -803,7 +805,6 @@ static int em_x270_libertas_teardown(struct spi_device *spi)
struct libertas_spi_platform_data em_x270_libertas_pdata = { struct libertas_spi_platform_data em_x270_libertas_pdata = {
.use_dummy_writes = 1, .use_dummy_writes = 1,
.gpio_cs = 14,
.setup = em_x270_libertas_setup, .setup = em_x270_libertas_setup,
.teardown = em_x270_libertas_teardown, .teardown = em_x270_libertas_teardown,
}; };
...@@ -838,10 +839,14 @@ static void __init em_x270_init_spi(void) ...@@ -838,10 +839,14 @@ static void __init em_x270_init_spi(void)
static inline void em_x270_init_spi(void) {} static inline void em_x270_init_spi(void) {}
#endif #endif
#if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE) #if defined(CONFIG_SND_PXA2XX_LIB_AC97)
static pxa2xx_audio_ops_t em_x270_ac97_info = {
.reset_gpio = 113,
};
static void __init em_x270_init_ac97(void) static void __init em_x270_init_ac97(void)
{ {
pxa_set_ac97_info(NULL); pxa_set_ac97_info(&em_x270_ac97_info);
} }
#else #else
static inline void em_x270_init_ac97(void) {} static inline void em_x270_init_ac97(void) {}
...@@ -1038,6 +1043,52 @@ static void __init em_x270_init_camera(void) ...@@ -1038,6 +1043,52 @@ static void __init em_x270_init_camera(void)
static inline void em_x270_init_camera(void) {} static inline void em_x270_init_camera(void) {}
#endif #endif
static struct regulator_bulk_data em_x270_gps_consumer_supply = {
.supply = "vcc gps",
};
static struct regulator_userspace_consumer_data em_x270_gps_consumer_data = {
.name = "vcc gps",
.num_supplies = 1,
.supplies = &em_x270_gps_consumer_supply,
};
static struct platform_device em_x270_gps_userspace_consumer = {
.name = "reg-userspace-consumer",
.id = 0,
.dev = {
.platform_data = &em_x270_gps_consumer_data,
},
};
static struct regulator_bulk_data em_x270_gprs_consumer_supply = {
.supply = "vcc gprs",
};
static struct regulator_userspace_consumer_data em_x270_gprs_consumer_data = {
.name = "vcc gprs",
.num_supplies = 1,
.supplies = &em_x270_gprs_consumer_supply
};
static struct platform_device em_x270_gprs_userspace_consumer = {
.name = "reg-userspace-consumer",
.id = 1,
.dev = {
.platform_data = &em_x270_gprs_consumer_data,
}
};
static struct platform_device *em_x270_userspace_consumers[] = {
&em_x270_gps_userspace_consumer,
&em_x270_gprs_userspace_consumer,
};
static void __init em_x270_userspace_consumers_init(void)
{
platform_add_devices(ARRAY_AND_SIZE(em_x270_userspace_consumers));
}
/* DA9030 related initializations */ /* DA9030 related initializations */
#define REGULATOR_CONSUMER(_name, _dev, _supply) \ #define REGULATOR_CONSUMER(_name, _dev, _supply) \
static struct regulator_consumer_supply _name##_consumers[] = { \ static struct regulator_consumer_supply _name##_consumers[] = { \
...@@ -1047,11 +1098,11 @@ static inline void em_x270_init_camera(void) {} ...@@ -1047,11 +1098,11 @@ static inline void em_x270_init_camera(void) {}
}, \ }, \
} }
REGULATOR_CONSUMER(ldo3, NULL, "vcc gps"); REGULATOR_CONSUMER(ldo3, &em_x270_gps_userspace_consumer.dev, "vcc gps");
REGULATOR_CONSUMER(ldo5, NULL, "vcc cam"); REGULATOR_CONSUMER(ldo5, NULL, "vcc cam");
REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio"); REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio");
REGULATOR_CONSUMER(ldo12, NULL, "vcc usb"); REGULATOR_CONSUMER(ldo12, NULL, "vcc usb");
REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs"); REGULATOR_CONSUMER(ldo19, &em_x270_gprs_userspace_consumer.dev, "vcc gprs");
#define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask) \ #define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask) \
static struct regulator_init_data _ldo##_data = { \ static struct regulator_init_data _ldo##_data = { \
...@@ -1062,6 +1113,7 @@ REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs"); ...@@ -1062,6 +1113,7 @@ REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs");
.enabled = 0, \ .enabled = 0, \
}, \ }, \
.valid_ops_mask = _ops_mask, \ .valid_ops_mask = _ops_mask, \
.apply_uV = 1, \
}, \ }, \
.num_consumer_supplies = ARRAY_SIZE(_ldo##_consumers), \ .num_consumer_supplies = ARRAY_SIZE(_ldo##_consumers), \
.consumer_supplies = _ldo##_consumers, \ .consumer_supplies = _ldo##_consumers, \
...@@ -1240,6 +1292,7 @@ static void __init em_x270_init(void) ...@@ -1240,6 +1292,7 @@ static void __init em_x270_init(void)
em_x270_init_spi(); em_x270_init_spi();
em_x270_init_i2c(); em_x270_init_i2c();
em_x270_init_camera(); em_x270_init_camera();
em_x270_userspace_consumers_init();
} }
MACHINE_START(EM_X270, "Compulab EM-X270") MACHINE_START(EM_X270, "Compulab EM-X270")
......
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
#include <linux/pwm_backlight.h> #include <linux/pwm_backlight.h>
#include <linux/regulator/bq24022.h> #include <linux/regulator/bq24022.h>
#include <linux/regulator/machine.h> #include <linux/regulator/machine.h>
#include <linux/regulator/max1586.h>
#include <linux/spi/ads7846.h> #include <linux/spi/ads7846.h>
#include <linux/spi/spi.h> #include <linux/spi/spi.h>
#include <linux/usb/gpio_vbus.h> #include <linux/usb/gpio_vbus.h>
...@@ -774,6 +775,45 @@ static struct platform_device strataflash = { ...@@ -774,6 +775,45 @@ static struct platform_device strataflash = {
}, },
}; };
/*
* Maxim MAX1587A on PI2C
*/
static struct regulator_consumer_supply max1587a_consumer = {
.supply = "vcc_core",
};
static struct regulator_init_data max1587a_v3_info = {
.constraints = {
.name = "vcc_core range",
.min_uV = 900000,
.max_uV = 1705000,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = 1,
.consumer_supplies = &max1587a_consumer,
};
static struct max1586_subdev_data max1587a_subdev = {
.name = "vcc_core",
.id = MAX1586_V3,
.platform_data = &max1587a_v3_info,
};
static struct max1586_platform_data max1587a_info = {
.num_subdevs = 1,
.subdevs = &max1587a_subdev,
.v3_gain = MAX1586_GAIN_R24_3k32, /* 730..1550 mV */
};
static struct i2c_board_info __initdata pi2c_board_info[] = {
{
I2C_BOARD_INFO("max1586", 0x14),
.platform_data = &max1587a_info,
},
};
/* /*
* PCMCIA * PCMCIA
*/ */
...@@ -828,6 +868,7 @@ static void __init hx4700_init(void) ...@@ -828,6 +868,7 @@ static void __init hx4700_init(void)
pxa_set_ficp_info(&ficp_info); pxa_set_ficp_info(&ficp_info);
pxa27x_set_i2c_power_info(NULL); pxa27x_set_i2c_power_info(NULL);
pxa_set_i2c_info(NULL); pxa_set_i2c_info(NULL);
i2c_register_board_info(1, ARRAY_AND_SIZE(pi2c_board_info));
pxa2xx_set_spi_info(2, &pxa_ssp2_master_info); pxa2xx_set_spi_info(2, &pxa_ssp2_master_info);
spi_register_board_info(ARRAY_AND_SIZE(tsc2046_board_info)); spi_register_board_info(ARRAY_AND_SIZE(tsc2046_board_info));
......
...@@ -31,8 +31,7 @@ ...@@ -31,8 +31,7 @@
/* USB */ /* USB */
#define GPIO_NR_PALMZ72_USB_DETECT_N 15 #define GPIO_NR_PALMZ72_USB_DETECT_N 15
#define GPIO_NR_PALMZ72_USB_POWER 95 #define GPIO_NR_PALMZ72_USB_PULLUP 95
#define GPIO_NR_PALMZ72_USB_PULLUP 12
/* LCD/Backlight */ /* LCD/Backlight */
#define GPIO_NR_PALMZ72_BL_POWER 20 #define GPIO_NR_PALMZ72_BL_POWER 20
......
/*
* GPIOs and interrupts for Palm Treo 680 smartphone
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _INCLUDE_TREO680_H_
#define _INCLUDE_TREO680_H_
/* GPIOs */
#define GPIO_NR_TREO680_POWER_DETECT 0
#define GPIO_NR_TREO680_AMP_EN 27
#define GPIO_NR_TREO680_KEYB_BL 24
#define GPIO_NR_TREO680_VIBRATE_EN 44
#define GPIO_NR_TREO680_GREEN_LED 20
#define GPIO_NR_TREO680_RED_LED 79
#define GPIO_NR_TREO680_SD_DETECT_N 113
#define GPIO_NR_TREO680_SD_READONLY 33
#define GPIO_NR_TREO680_EP_DETECT_N 116
#define GPIO_NR_TREO680_SD_POWER 42
#define GPIO_NR_TREO680_USB_DETECT 1
#define GPIO_NR_TREO680_USB_PULLUP 114
#define GPIO_NR_TREO680_GSM_POWER 40
#define GPIO_NR_TREO680_GSM_RESET 87
#define GPIO_NR_TREO680_GSM_WAKE 57
#define GPIO_NR_TREO680_GSM_HOST_WAKE 14
#define GPIO_NR_TREO680_GSM_TRIGGER 10
#define GPIO_NR_TREO680_BT_EN 43
#define GPIO_NR_TREO680_IR_EN 115
#define GPIO_NR_TREO680_IR_TXD 47
#define GPIO_NR_TREO680_BL_POWER 38
#define GPIO_NR_TREO680_LCD_POWER 25
/* Various addresses */
#define TREO680_PHYS_RAM_START 0xa0000000
#define TREO680_PHYS_IO_START 0x40000000
#define TREO680_STR_BASE 0xa2000000
/* BACKLIGHT */
#define TREO680_MAX_INTENSITY 254
#define TREO680_DEFAULT_INTENSITY 160
#define TREO680_LIMIT_MASK 0x7F
#define TREO680_PRESCALER 63
#define TREO680_PERIOD_NS 3500
#endif
...@@ -37,6 +37,7 @@ ...@@ -37,6 +37,7 @@
#include <linux/wm97xx_batt.h> #include <linux/wm97xx_batt.h>
#include <linux/mtd/physmap.h> #include <linux/mtd/physmap.h>
#include <linux/usb/gpio_vbus.h> #include <linux/usb/gpio_vbus.h>
#include <linux/regulator/max1586.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
...@@ -716,6 +717,38 @@ static struct wm97xx_batt_info mioa701_battery_data = { ...@@ -716,6 +717,38 @@ static struct wm97xx_batt_info mioa701_battery_data = {
.batt_name = "mioa701_battery", .batt_name = "mioa701_battery",
}; };
/*
* Voltage regulation
*/
static struct regulator_consumer_supply max1586_consumers[] = {
{
.supply = "vcc_core",
}
};
static struct regulator_init_data max1586_v3_info = {
.constraints = {
.name = "vcc_core range",
.min_uV = 1000000,
.max_uV = 1705000,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(max1586_consumers),
.consumer_supplies = max1586_consumers,
};
static struct max1586_subdev_data max1586_subdevs[] = {
{ .name = "vcc_core", .id = MAX1586_V3,
.platform_data = &max1586_v3_info },
};
static struct max1586_platform_data max1586_info = {
.subdevs = max1586_subdevs,
.num_subdevs = ARRAY_SIZE(max1586_subdevs),
.v3_gain = MAX1586_GAIN_NO_R24, /* 700..1475 mV */
};
/* /*
* Camera interface * Camera interface
*/ */
...@@ -725,6 +758,13 @@ struct pxacamera_platform_data mioa701_pxacamera_platform_data = { ...@@ -725,6 +758,13 @@ struct pxacamera_platform_data mioa701_pxacamera_platform_data = {
.mclk_10khz = 5000, .mclk_10khz = 5000,
}; };
static struct i2c_board_info __initdata mioa701_pi2c_devices[] = {
{
I2C_BOARD_INFO("max1586", 0x14),
.platform_data = &max1586_info,
},
};
static struct soc_camera_link iclink = { static struct soc_camera_link iclink = {
.bus_id = 0, /* Must match id in pxa27x_device_camera in device.c */ .bus_id = 0, /* Must match id in pxa27x_device_camera in device.c */
}; };
...@@ -825,7 +865,9 @@ static void __init mioa701_machine_init(void) ...@@ -825,7 +865,9 @@ static void __init mioa701_machine_init(void)
platform_add_devices(devices, ARRAY_SIZE(devices)); platform_add_devices(devices, ARRAY_SIZE(devices));
gsm_init(); gsm_init();
i2c_register_board_info(1, ARRAY_AND_SIZE(mioa701_pi2c_devices));
pxa_set_i2c_info(&i2c_pdata); pxa_set_i2c_info(&i2c_pdata);
pxa27x_set_i2c_power_info(NULL);
pxa_set_camera_info(&mioa701_pxacamera_platform_data); pxa_set_camera_info(&mioa701_pxacamera_platform_data);
i2c_register_board_info(0, ARRAY_AND_SIZE(mioa701_i2c_devices)); i2c_register_board_info(0, ARRAY_AND_SIZE(mioa701_i2c_devices));
} }
......
...@@ -27,7 +27,9 @@ ...@@ -27,7 +27,9 @@
#include <linux/pda_power.h> #include <linux/pda_power.h>
#include <linux/pwm_backlight.h> #include <linux/pwm_backlight.h>
#include <linux/gpio.h> #include <linux/gpio.h>
#include <linux/wm97xx_batt.h>
#include <linux/power_supply.h> #include <linux/power_supply.h>
#include <linux/usb/gpio_vbus.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
...@@ -41,6 +43,8 @@ ...@@ -41,6 +43,8 @@
#include <mach/irda.h> #include <mach/irda.h>
#include <mach/pxa27x_keypad.h> #include <mach/pxa27x_keypad.h>
#include <mach/udc.h> #include <mach/udc.h>
#include <mach/palmasoc.h>
#include <mach/pm.h> #include <mach/pm.h>
#include "generic.h" #include "generic.h"
...@@ -66,6 +70,8 @@ static unsigned long palmz72_pin_config[] __initdata = { ...@@ -66,6 +70,8 @@ static unsigned long palmz72_pin_config[] __initdata = {
GPIO29_AC97_SDATA_IN_0, GPIO29_AC97_SDATA_IN_0,
GPIO30_AC97_SDATA_OUT, GPIO30_AC97_SDATA_OUT,
GPIO31_AC97_SYNC, GPIO31_AC97_SYNC,
GPIO89_AC97_SYSCLK,
GPIO113_AC97_nRESET,
/* IrDA */ /* IrDA */
GPIO49_GPIO, /* ir disable */ GPIO49_GPIO, /* ir disable */
...@@ -77,8 +83,7 @@ static unsigned long palmz72_pin_config[] __initdata = { ...@@ -77,8 +83,7 @@ static unsigned long palmz72_pin_config[] __initdata = {
/* USB */ /* USB */
GPIO15_GPIO, /* usb detect */ GPIO15_GPIO, /* usb detect */
GPIO12_GPIO, /* usb pullup */ GPIO95_GPIO, /* usb pullup */
GPIO95_GPIO, /* usb power */
/* Matrix keypad */ /* Matrix keypad */
GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
...@@ -354,6 +359,22 @@ static struct platform_device palmz72_leds = { ...@@ -354,6 +359,22 @@ static struct platform_device palmz72_leds = {
} }
}; };
/******************************************************************************
* UDC
******************************************************************************/
static struct gpio_vbus_mach_info palmz72_udc_info = {
.gpio_vbus = GPIO_NR_PALMZ72_USB_DETECT_N,
.gpio_pullup = GPIO_NR_PALMZ72_USB_PULLUP,
};
static struct platform_device palmz72_gpio_vbus = {
.name = "gpio-vbus",
.id = -1,
.dev = {
.platform_data = &palmz72_udc_info,
},
};
/****************************************************************************** /******************************************************************************
* Power supply * Power supply
******************************************************************************/ ******************************************************************************/
...@@ -421,6 +442,31 @@ static struct platform_device power_supply = { ...@@ -421,6 +442,31 @@ static struct platform_device power_supply = {
}, },
}; };
/******************************************************************************
* WM97xx battery
******************************************************************************/
static struct wm97xx_batt_info wm97xx_batt_pdata = {
.batt_aux = WM97XX_AUX_ID3,
.temp_aux = WM97XX_AUX_ID2,
.charge_gpio = -1,
.max_voltage = PALMZ72_BAT_MAX_VOLTAGE,
.min_voltage = PALMZ72_BAT_MIN_VOLTAGE,
.batt_mult = 1000,
.batt_div = 414,
.temp_mult = 1,
.temp_div = 1,
.batt_tech = POWER_SUPPLY_TECHNOLOGY_LIPO,
.batt_name = "main-batt",
};
/******************************************************************************
* aSoC audio
******************************************************************************/
static struct platform_device palmz72_asoc = {
.name = "palm27x-asoc",
.id = -1,
};
/****************************************************************************** /******************************************************************************
* Framebuffer * Framebuffer
******************************************************************************/ ******************************************************************************/
...@@ -527,17 +573,32 @@ device_initcall(palmz72_pm_init); ...@@ -527,17 +573,32 @@ device_initcall(palmz72_pm_init);
static struct platform_device *devices[] __initdata = { static struct platform_device *devices[] __initdata = {
&palmz72_backlight, &palmz72_backlight,
&palmz72_leds, &palmz72_leds,
&palmz72_asoc,
&power_supply, &power_supply,
&palmz72_gpio_vbus,
}; };
/* setup udc GPIOs initial state */
static void __init palmz72_udc_init(void)
{
if (!gpio_request(GPIO_NR_PALMZ72_USB_PULLUP, "USB Pullup")) {
gpio_direction_output(GPIO_NR_PALMZ72_USB_PULLUP, 0);
gpio_free(GPIO_NR_PALMZ72_USB_PULLUP);
}
}
static void __init palmz72_init(void) static void __init palmz72_init(void)
{ {
pxa2xx_mfp_config(ARRAY_AND_SIZE(palmz72_pin_config)); pxa2xx_mfp_config(ARRAY_AND_SIZE(palmz72_pin_config));
set_pxa_fb_info(&palmz72_lcd_screen); set_pxa_fb_info(&palmz72_lcd_screen);
pxa_set_mci_info(&palmz72_mci_platform_data); pxa_set_mci_info(&palmz72_mci_platform_data);
palmz72_udc_init();
pxa_set_ac97_info(NULL); pxa_set_ac97_info(NULL);
pxa_set_ficp_info(&palmz72_ficp_platform_data); pxa_set_ficp_info(&palmz72_ficp_platform_data);
pxa_set_keypad_info(&palmz72_keypad_platform_data); pxa_set_keypad_info(&palmz72_keypad_platform_data);
wm97xx_bat_set_pdata(&wm97xx_batt_pdata);
platform_add_devices(devices, ARRAY_SIZE(devices)); platform_add_devices(devices, ARRAY_SIZE(devices));
} }
......
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/mtd/physmap.h> #include <linux/mtd/physmap.h>
#include <linux/gpio.h> #include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/spi/spi.h> #include <linux/spi/spi.h>
#include <linux/spi/ads7846.h> #include <linux/spi/ads7846.h>
#include <linux/mtd/sharpsl.h> #include <linux/mtd/sharpsl.h>
...@@ -486,6 +487,10 @@ static struct platform_device *devices[] __initdata = { ...@@ -486,6 +487,10 @@ static struct platform_device *devices[] __initdata = {
&sharpsl_rom_device, &sharpsl_rom_device,
}; };
static struct i2c_board_info __initdata poodle_i2c_devices[] = {
{ I2C_BOARD_INFO("wm8731", 0x1b) },
};
static void poodle_poweroff(void) static void poodle_poweroff(void)
{ {
arm_machine_restart('h', NULL); arm_machine_restart('h', NULL);
...@@ -519,6 +524,7 @@ static void __init poodle_init(void) ...@@ -519,6 +524,7 @@ static void __init poodle_init(void)
pxa_set_mci_info(&poodle_mci_platform_data); pxa_set_mci_info(&poodle_mci_platform_data);
pxa_set_ficp_info(&poodle_ficp_platform_data); pxa_set_ficp_info(&poodle_ficp_platform_data);
pxa_set_i2c_info(NULL); pxa_set_i2c_info(NULL);
i2c_register_board_info(0, ARRAY_AND_SIZE(poodle_i2c_devices));
poodle_init_spi(); poodle_init_spi();
} }
......
This diff is collapsed.
...@@ -27,6 +27,7 @@ ...@@ -27,6 +27,7 @@
#include <asm/irq.h> #include <asm/irq.h>
#include <asm/leds.h> #include <asm/leds.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/smp_twd.h>
#include <asm/hardware/gic.h> #include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h> #include <asm/hardware/cache-l2x0.h>
......
...@@ -22,7 +22,6 @@ ...@@ -22,7 +22,6 @@
#include <linux/timer.h> #include <linux/timer.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/device.h> #include <linux/device.h>
#include <linux/gpio.h>
#include <linux/io.h> #include <linux/io.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
......
...@@ -84,5 +84,15 @@ config MACH_AT2440EVB ...@@ -84,5 +84,15 @@ config MACH_AT2440EVB
help help
Say Y here if you are using the AT2440EVB development board Say Y here if you are using the AT2440EVB development board
config MACH_MINI2440
bool "MINI2440 development board"
select CPU_S3C2440
select EEPROM_AT24
select LEDS_TRIGGER_BACKLIGHT
select SND_S3C24XX_SOC_S3C24XX_UDA134X
help
Say Y here to select support for the MINI2440. Is a 10cm x 10cm board
available via various sources. It can come with a 3.5" or 7" touch LCD.
endmenu endmenu
...@@ -22,3 +22,4 @@ obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o ...@@ -22,3 +22,4 @@ obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o
obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o
obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o
This diff is collapsed.
...@@ -24,6 +24,18 @@ config SMDK2440_CPU2442 ...@@ -24,6 +24,18 @@ config SMDK2440_CPU2442
depends on ARCH_S3C2440 depends on ARCH_S3C2440
select CPU_S3C2442 select CPU_S3C2442
config MACH_NEO1973_GTA02
bool "Openmoko GTA02 / Freerunner phone"
select CPU_S3C2442
select MFD_PCF50633
select PCF50633_GPIO
select I2C
select POWER_SUPPLY
select MACH_NEO1973
select S3C2410_PWM
help
Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone
endmenu endmenu
...@@ -12,5 +12,7 @@ obj- := ...@@ -12,5 +12,7 @@ obj- :=
obj-$(CONFIG_CPU_S3C2442) += s3c2442.o obj-$(CONFIG_CPU_S3C2442) += s3c2442.o
obj-$(CONFIG_CPU_S3C2442) += clock.o obj-$(CONFIG_CPU_S3C2442) += clock.o
obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o
# Machine support # Machine support
#ifndef _GTA02_H
#define _GTA02_H
#include <mach/regs-gpio.h>
/* Different hardware revisions, passed in ATAG_REVISION by u-boot */
#define GTA02v1_SYSTEM_REV 0x00000310
#define GTA02v2_SYSTEM_REV 0x00000320
#define GTA02v3_SYSTEM_REV 0x00000330
#define GTA02v4_SYSTEM_REV 0x00000340
#define GTA02v5_SYSTEM_REV 0x00000350
/* since A7 is basically same as A6, we use A6 PCB ID */
#define GTA02v6_SYSTEM_REV 0x00000360
#define GTA02_GPIO_n3DL_GSM S3C2410_GPA(13) /* v1 + v2 + v3 only */
#define GTA02_GPIO_PWR_LED1 S3C2410_GPB(0)
#define GTA02_GPIO_PWR_LED2 S3C2410_GPB(1)
#define GTA02_GPIO_AUX_LED S3C2410_GPB(2)
#define GTA02_GPIO_VIBRATOR_ON S3C2410_GPB(3)
#define GTA02_GPIO_MODEM_RST S3C2410_GPB(5)
#define GTA02_GPIO_BT_EN S3C2410_GPB(6)
#define GTA02_GPIO_MODEM_ON S3C2410_GPB(7)
#define GTA02_GPIO_EXTINT8 S3C2410_GPB(8)
#define GTA02_GPIO_USB_PULLUP S3C2410_GPB(9)
#define GTA02_GPIO_PIO5 S3C2410_GPC(5) /* v3 + v4 only */
#define GTA02v3_GPIO_nG1_CS S3C2410_GPD(12) /* v3 + v4 only */
#define GTA02v3_GPIO_nG2_CS S3C2410_GPD(13) /* v3 + v4 only */
#define GTA02v5_GPIO_HDQ S3C2410_GPD(14) /* v5 + */
#define GTA02_GPIO_nG1_INT S3C2410_GPF(0)
#define GTA02_GPIO_IO1 S3C2410_GPF(1)
#define GTA02_GPIO_PIO_2 S3C2410_GPF(2) /* v2 + v3 + v4 only */
#define GTA02_GPIO_JACK_INSERT S3C2410_GPF(4)
#define GTA02_GPIO_WLAN_GPIO1 S3C2410_GPF(5) /* v2 + v3 + v4 only */
#define GTA02_GPIO_AUX_KEY S3C2410_GPF(6)
#define GTA02_GPIO_HOLD_KEY S3C2410_GPF(7)
#define GTA02_GPIO_3D_IRQ S3C2410_GPG(4)
#define GTA02v2_GPIO_nG2_INT S3C2410_GPG(8) /* v2 + v3 + v4 only */
#define GTA02v3_GPIO_nUSB_OC S3C2410_GPG(9) /* v3 + v4 only */
#define GTA02v3_GPIO_nUSB_FLT S3C2410_GPG(10) /* v3 + v4 only */
#define GTA02v3_GPIO_nGSM_OC S3C2410_GPG(11) /* v3 + v4 only */
#define GTA02_GPIO_AMP_SHUT S3C2440_GPJ1 /* v2 + v3 + v4 only */
#define GTA02v1_GPIO_WLAN_GPIO10 S3C2440_GPJ2
#define GTA02_GPIO_HP_IN S3C2440_GPJ2 /* v2 + v3 + v4 only */
#define GTA02_GPIO_INT0 S3C2440_GPJ3 /* v2 + v3 + v4 only */
#define GTA02_GPIO_nGSM_EN S3C2440_GPJ4
#define GTA02_GPIO_3D_RESET S3C2440_GPJ5
#define GTA02_GPIO_nDL_GSM S3C2440_GPJ6 /* v4 + v5 only */
#define GTA02_GPIO_WLAN_GPIO0 S3C2440_GPJ7
#define GTA02v1_GPIO_BAT_ID S3C2440_GPJ8
#define GTA02_GPIO_KEEPACT S3C2440_GPJ8
#define GTA02v1_GPIO_HP_IN S3C2440_GPJ10
#define GTA02_CHIP_PWD S3C2440_GPJ11 /* v2 + v3 + v4 only */
#define GTA02_GPIO_nWLAN_RESET S3C2440_GPJ12 /* v2 + v3 + v4 only */
#define GTA02_IRQ_GSENSOR_1 IRQ_EINT0
#define GTA02_IRQ_MODEM IRQ_EINT1
#define GTA02_IRQ_PIO_2 IRQ_EINT2 /* v2 + v3 + v4 only */
#define GTA02_IRQ_nJACK_INSERT IRQ_EINT4
#define GTA02_IRQ_WLAN_GPIO1 IRQ_EINT5
#define GTA02_IRQ_AUX IRQ_EINT6
#define GTA02_IRQ_nHOLD IRQ_EINT7
#define GTA02_IRQ_PCF50633 IRQ_EINT9
#define GTA02_IRQ_3D IRQ_EINT12
#define GTA02_IRQ_GSENSOR_2 IRQ_EINT16 /* v2 + v3 + v4 only */
#define GTA02v3_IRQ_nUSB_OC IRQ_EINT17 /* v3 + v4 only */
#define GTA02v3_IRQ_nUSB_FLT IRQ_EINT18 /* v3 + v4 only */
#define GTA02v3_IRQ_nGSM_OC IRQ_EINT19 /* v3 + v4 only */
/* returns 00 000 on GTA02 A5 and earlier, A6 returns 01 001 */
#define GTA02_PCB_ID1_0 S3C2410_GPC(13)
#define GTA02_PCB_ID1_1 S3C2410_GPC(15)
#define GTA02_PCB_ID1_2 S3C2410_GPD(0)
#define GTA02_PCB_ID2_0 S3C2410_GPD(3)
#define GTA02_PCB_ID2_1 S3C2410_GPD(4)
int gta02_get_pcb_revision(void);
#endif /* _GTA02_H */
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...@@ -836,6 +836,13 @@ void __init reserve_node_zero(pg_data_t *pgdat) ...@@ -836,6 +836,13 @@ void __init reserve_node_zero(pg_data_t *pgdat)
BOOTMEM_EXCLUSIVE); BOOTMEM_EXCLUSIVE);
} }
if (machine_is_treo680()) {
reserve_bootmem_node(pgdat, 0xa0000000, 0x1000,
BOOTMEM_EXCLUSIVE);
reserve_bootmem_node(pgdat, 0xa2000000, 0x1000,
BOOTMEM_EXCLUSIVE);
}
if (machine_is_palmt5()) if (machine_is_palmt5())
reserve_bootmem_node(pgdat, 0xa0200000, 0x1000, reserve_bootmem_node(pgdat, 0xa0200000, 0x1000,
BOOTMEM_EXCLUSIVE); BOOTMEM_EXCLUSIVE);
......
...@@ -24,7 +24,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); ...@@ -24,7 +24,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2, u32 sdrc_actim_ctrlb, u32 m2,
u32 unlock_dll); u32 unlock_dll, u32 f, u32 sdrc_mr,
u32 inc);
/* Do not use these */ /* Do not use these */
extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
...@@ -62,7 +63,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz; ...@@ -62,7 +63,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2, u32 sdrc_actim_ctrlb, u32 m2,
u32 unlock_dll); u32 unlock_dll, u32 f, u32 sdrc_mr,
u32 inc);
extern unsigned long omap3_sram_configure_core_dpll_sz; extern unsigned long omap3_sram_configure_core_dpll_sz;
#endif #endif
...@@ -371,15 +371,17 @@ static inline int omap243x_sram_init(void) ...@@ -371,15 +371,17 @@ static inline int omap243x_sram_init(void)
static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 sdrc_actim_ctrlb,
u32 m2, u32 unlock_dll); u32 m2, u32 unlock_dll,
u32 f, u32 sdrc_mr, u32 inc);
u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll) u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
u32 f, u32 sdrc_mr, u32 inc)
{ {
BUG_ON(!_omap3_sram_configure_core_dpll); BUG_ON(!_omap3_sram_configure_core_dpll);
return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
sdrc_actim_ctrla, sdrc_actim_ctrla,
sdrc_actim_ctrlb, m2, sdrc_actim_ctrlb, m2,
unlock_dll); unlock_dll, f, sdrc_mr, inc);
} }
/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
......
...@@ -34,6 +34,7 @@ obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o ...@@ -34,6 +34,7 @@ obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o
obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o
obj-y += dev-i2c0.o obj-y += dev-i2c0.o
obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o
obj-$(CONFIG_SND_S3C24XX_SOC) += dev-audio.o
obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o
obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o
obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o
/* linux/arch/arm/plat-s3c/dev-audio.c
*
* Copyright 2009 Wolfson Microelectronics
* Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <mach/irqs.h>
#include <mach/map.h>
#include <plat/devs.h>
static struct resource s3c64xx_iis0_resource[] = {
[0] = {
.start = S3C64XX_PA_IIS0,
.end = S3C64XX_PA_IIS0 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device s3c64xx_device_iis0 = {
.name = "s3c64xx-iis",
.id = 0,
.num_resources = ARRAY_SIZE(s3c64xx_iis0_resource),
.resource = s3c64xx_iis0_resource,
};
EXPORT_SYMBOL(s3c64xx_device_iis0);
static struct resource s3c64xx_iis1_resource[] = {
[0] = {
.start = S3C64XX_PA_IIS1,
.end = S3C64XX_PA_IIS1 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device s3c64xx_device_iis1 = {
.name = "s3c64xx-iis",
.id = 1,
.num_resources = ARRAY_SIZE(s3c64xx_iis1_resource),
.resource = s3c64xx_iis1_resource,
};
EXPORT_SYMBOL(s3c64xx_device_iis1);
static struct resource s3c64xx_iisv4_resource[] = {
[0] = {
.start = S3C64XX_PA_IISV4,
.end = S3C64XX_PA_IISV4 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device s3c64xx_device_iisv4 = {
.name = "s3c64xx-iis-v4",
.id = -1,
.num_resources = ARRAY_SIZE(s3c64xx_iisv4_resource),
.resource = s3c64xx_iisv4_resource,
};
EXPORT_SYMBOL(s3c64xx_device_iisv4);
...@@ -119,7 +119,7 @@ int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, ...@@ -119,7 +119,7 @@ int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
unsigned int shift = (off & 7) * 4; unsigned int shift = (off & 7) * 4;
u32 con; u32 con;
if (off < 8 && chip->chip.ngpio >= 8) if (off < 8 && chip->chip.ngpio > 8)
reg -= 4; reg -= 4;
if (s3c_gpio_is_cfg_special(cfg)) { if (s3c_gpio_is_cfg_special(cfg)) {
......
...@@ -24,13 +24,16 @@ extern struct platform_device *s3c24xx_uart_src[]; ...@@ -24,13 +24,16 @@ extern struct platform_device *s3c24xx_uart_src[];
extern struct platform_device s3c_device_timer[]; extern struct platform_device s3c_device_timer[];
extern struct platform_device s3c64xx_device_iis0;
extern struct platform_device s3c64xx_device_iis1;
extern struct platform_device s3c64xx_device_iisv4;
extern struct platform_device s3c_device_fb; extern struct platform_device s3c_device_fb;
extern struct platform_device s3c_device_usb; extern struct platform_device s3c_device_usb;
extern struct platform_device s3c_device_lcd; extern struct platform_device s3c_device_lcd;
extern struct platform_device s3c_device_wdt; extern struct platform_device s3c_device_wdt;
extern struct platform_device s3c_device_i2c0; extern struct platform_device s3c_device_i2c0;
extern struct platform_device s3c_device_i2c1; extern struct platform_device s3c_device_i2c1;
extern struct platform_device s3c_device_iis;
extern struct platform_device s3c_device_rtc; extern struct platform_device s3c_device_rtc;
extern struct platform_device s3c_device_adc; extern struct platform_device s3c_device_adc;
extern struct platform_device s3c_device_sdi; extern struct platform_device s3c_device_sdi;
......
...@@ -23,6 +23,7 @@ obj-y += gpiolib.o ...@@ -23,6 +23,7 @@ obj-y += gpiolib.o
obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o
obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o
obj-$(CONFIG_CPU_FREQ_S3C64XX) += cpufreq.o
# PM support # PM support
......
...@@ -191,7 +191,7 @@ static struct clk init_clocks[] = { ...@@ -191,7 +191,7 @@ static struct clk init_clocks[] = {
.id = -1, .id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_UHOST, .ctrlbit = S3C_CLKCON_HCLK_UHOST,
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 0, .id = 0,
......
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...@@ -321,6 +321,11 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = { ...@@ -321,6 +321,11 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
.get_pull = s3c_gpio_getpull_updown, .get_pull = s3c_gpio_getpull_updown,
}; };
int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin)
{
return IRQ_EINT(0) + pin;
}
static struct s3c_gpio_chip gpio_2bit[] = { static struct s3c_gpio_chip gpio_2bit[] = {
{ {
.base = S3C64XX_GPF_BASE, .base = S3C64XX_GPF_BASE,
...@@ -353,6 +358,7 @@ static struct s3c_gpio_chip gpio_2bit[] = { ...@@ -353,6 +358,7 @@ static struct s3c_gpio_chip gpio_2bit[] = {
.base = S3C64XX_GPN(0), .base = S3C64XX_GPN(0),
.ngpio = S3C64XX_GPIO_N_NR, .ngpio = S3C64XX_GPIO_N_NR,
.label = "GPN", .label = "GPN",
.to_irq = s3c64xx_gpio2int_gpn,
}, },
}, { }, {
.base = S3C64XX_GPO_BASE, .base = S3C64XX_GPO_BASE,
......
...@@ -88,11 +88,11 @@ ...@@ -88,11 +88,11 @@
#define S3C6400_CLKDIV2_SPI0_SHIFT (0) #define S3C6400_CLKDIV2_SPI0_SHIFT (0)
/* HCLK GATE Registers */ /* HCLK GATE Registers */
#define S3C_CLKCON_HCLK_BUS (1<<30) #define S3C_CLKCON_HCLK_3DSE (1<<31)
#define S3C_CLKCON_HCLK_SECUR (1<<29) #define S3C_CLKCON_HCLK_UHOST (1<<29)
#define S3C_CLKCON_HCLK_SDMA1 (1<<28) #define S3C_CLKCON_HCLK_SECUR (1<<28)
#define S3C_CLKCON_HCLK_SDMA2 (1<<27) #define S3C_CLKCON_HCLK_SDMA1 (1<<27)
#define S3C_CLKCON_HCLK_UHOST (1<<26) #define S3C_CLKCON_HCLK_SDMA0 (1<<26)
#define S3C_CLKCON_HCLK_IROM (1<<25) #define S3C_CLKCON_HCLK_IROM (1<<25)
#define S3C_CLKCON_HCLK_DDR1 (1<<24) #define S3C_CLKCON_HCLK_DDR1 (1<<24)
#define S3C_CLKCON_HCLK_DDR0 (1<<23) #define S3C_CLKCON_HCLK_DDR0 (1<<23)
......
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