Commit 9fe2420d authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam Committed by Olof Johansson

ARM: dts: Add RDA8810PL GPIO controllers

Add GPIO controllers for RDA8810PL SoC. There are 4 GPIO controllers
in this SoC with maximum of 32 gpios. Except GPIOC, all controllers
are capable of generating edge/level interrupts from first 8 lines.

Link: https://lore.kernel.org/r/20191030101154.6312-2-manivannan.sadhasivam@linaro.orgSigned-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 32f714d3
......@@ -33,6 +33,21 @@ sram@100000 {
ranges;
};
modem@10000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10000000 0xfffffff>;
gpioc@1a08000 {
compatible = "rda,8810pl-gpio";
reg = <0x1a08000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
};
};
apb@20800000 {
compatible = "simple-bus";
#address-cells = <1>;
......@@ -60,6 +75,39 @@ timer@10000 {
<17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hwtimer", "ostimer";
};
gpioa@30000 {
compatible = "rda,8810pl-gpio";
reg = <0x30000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
};
gpiob@31000 {
compatible = "rda,8810pl-gpio";
reg = <0x31000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
};
gpiod@32000 {
compatible = "rda,8810pl-gpio";
reg = <0x32000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
};
};
apb@20a00000 {
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment