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Commit a2769608 authored by Linus Torvalds's avatar Linus Torvalds
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Merge bk://linux-mtd.bkbits.net/mtd-2.6 

into ppc970.osdl.org:/home/torvalds/v2.6/linux
parents 6909f28b a731692e
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Showing with 545 additions and 1318 deletions
Documentation/crypto/api-intro.txt
View file @ a2769608
...@@ -215,7 +215,6 @@ AES algorithm contributors: ...@@ -215,7 +215,6 @@ AES algorithm contributors:
Herbert Valerio Riedel Herbert Valerio Riedel
Kyle McMartin Kyle McMartin
Adam J. Richter Adam J. Richter
Fruhwirth Clemens (i586)
CAST5 algorithm contributors: CAST5 algorithm contributors:
Kartikey Mahendra Bhatt (original developers unknown, FSF copyright). Kartikey Mahendra Bhatt (original developers unknown, FSF copyright).
......
arch/arm/boot/compressed/head-clps7500.S
View file @ a2769608
...@@ -34,7 +34,7 @@ ...@@ -34,7 +34,7 @@
mov r0, #0x30 mov r0, #0x30
mcr p15, 0, r0, c1, c0, 0 mcr p15, 0, r0, c1, c0, 0
mov r0, #0x13 mov r0, #0x13
msr cpsr, r0 msr cpsr_cxsf, r0
mov r12, #0x03000000 @ point to LEDs mov r12, #0x03000000 @ point to LEDs
orr r12, r12, #0x00020000 orr r12, r12, #0x00020000
orr r12, r12, #0xba00 orr r12, r12, #0xba00
...@@ -71,7 +71,7 @@ ...@@ -71,7 +71,7 @@
/* Ensure all interrupts are off and MMU disabled */ /* Ensure all interrupts are off and MMU disabled */
mrs r0, cpsr mrs r0, cpsr
orr r0, r0, #0xc0 orr r0, r0, #0xc0
msr cpsr, r0 msr cpsr_cxsf, r0
adr lr, 1b adr lr, 1b
orr lr, lr, #0x10000000 orr lr, lr, #0x10000000
......
arch/arm/configs/bast_defconfig
View file @ a2769608
...@@ -20,17 +20,24 @@ CONFIG_BROKEN_ON_SMP=y ...@@ -20,17 +20,24 @@ CONFIG_BROKEN_ON_SMP=y
# #
CONFIG_SWAP=y CONFIG_SWAP=y
CONFIG_SYSVIPC=y CONFIG_SYSVIPC=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y CONFIG_SYSCTL=y
CONFIG_LOG_BUF_SHIFT=16 # CONFIG_AUDIT is not set
CONFIG_LOG_BUF_SHIFT=17
# CONFIG_HOTPLUG is not set
# CONFIG_IKCONFIG is not set # CONFIG_IKCONFIG is not set
# CONFIG_EMBEDDED is not set # CONFIG_EMBEDDED is not set
CONFIG_KALLSYMS=y CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_FUTEX=y CONFIG_FUTEX=y
CONFIG_EPOLL=y CONFIG_EPOLL=y
CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# #
# Loadable module support # Loadable module support
...@@ -44,57 +51,32 @@ CONFIG_KMOD=y ...@@ -44,57 +51,32 @@ CONFIG_KMOD=y
# #
# System Type # System Type
# #
# CONFIG_ARCH_ADIFCC is not set
# CONFIG_ARCH_ANAKIN is not set
# CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set # CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_CAMELOT is not set # CONFIG_ARCH_CAMELOT is not set
# CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_IOP3XX is not set # CONFIG_ARCH_IOP3XX is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set # CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set # CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_SHARK is not set
CONFIG_ARCH_S3C2410=y CONFIG_ARCH_S3C2410=y
# CONFIG_ARCH_SHARK is not set
# # CONFIG_ARCH_LH7A40X is not set
# CLPS711X/EP721X Implementations # CONFIG_ARCH_OMAP is not set
# # CONFIG_ARCH_VERSATILE_PB is not set
#
# Epxa10db
#
#
# Footbridge Implementations
#
#
# IOP3xx Implementation Options
#
# CONFIG_ARCH_IOP310 is not set
# CONFIG_ARCH_IOP321 is not set
#
# IOP3xx Chipset Features
#
#
# Intel PXA250/210 Implementations
#
#
# SA11x0 Implementations
#
# #
# S3C2410 Implementations # S3C2410 Implementations
# #
CONFIG_ARCH_BAST=y CONFIG_ARCH_BAST=y
# CONFIG_ARCH_H1940 is not set
# CONFIG_ARCH_SMDK2410 is not set
CONFIG_MACH_VR1000=y
# #
# Processor Type # Processor Type
...@@ -119,9 +101,8 @@ CONFIG_CPU_TLB_V4WBI=y ...@@ -119,9 +101,8 @@ CONFIG_CPU_TLB_V4WBI=y
# General setup # General setup
# #
# CONFIG_ZBOOT_ROM is not set # CONFIG_ZBOOT_ROM is not set
CONFIG_ZBOOT_ROM_TEXT=0 CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0 CONFIG_ZBOOT_ROM_BSS=0x0
# CONFIG_HOTPLUG is not set
# #
# At least one math emulation must be selected # At least one math emulation must be selected
...@@ -129,6 +110,7 @@ CONFIG_ZBOOT_ROM_BSS=0 ...@@ -129,6 +110,7 @@ CONFIG_ZBOOT_ROM_BSS=0
CONFIG_FPE_NWFPE=y CONFIG_FPE_NWFPE=y
CONFIG_FPE_NWFPE_XP=y CONFIG_FPE_NWFPE_XP=y
# CONFIG_FPE_FASTFPE is not set # CONFIG_FPE_FASTFPE is not set
# CONFIG_VFP is not set
CONFIG_BINFMT_ELF=y CONFIG_BINFMT_ELF=y
CONFIG_BINFMT_AOUT=y CONFIG_BINFMT_AOUT=y
# CONFIG_BINFMT_MISC is not set # CONFIG_BINFMT_MISC is not set
...@@ -136,9 +118,13 @@ CONFIG_BINFMT_AOUT=y ...@@ -136,9 +118,13 @@ CONFIG_BINFMT_AOUT=y
# #
# Generic Driver Options # Generic Driver Options
# #
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_PM is not set # CONFIG_PM is not set
# CONFIG_PREEMPT is not set # CONFIG_PREEMPT is not set
# CONFIG_ARTHUR is not set # CONFIG_ARTHUR is not set
CONFIG_S3C2410_DMA=y
# CONFIG_S3C2410_DMA_DEBUG is not set
CONFIG_CMDLINE="root=/dev/hda1 ro init=/bin/bash console=ttySAC0" CONFIG_CMDLINE="root=/dev/hda1 ro init=/bin/bash console=ttySAC0"
CONFIG_ALIGNMENT_TRAP=y CONFIG_ALIGNMENT_TRAP=y
...@@ -148,7 +134,6 @@ CONFIG_ALIGNMENT_TRAP=y ...@@ -148,7 +134,6 @@ CONFIG_ALIGNMENT_TRAP=y
CONFIG_PARPORT=y CONFIG_PARPORT=y
CONFIG_PARPORT_PC=y CONFIG_PARPORT_PC=y
CONFIG_PARPORT_PC_CML1=y CONFIG_PARPORT_PC_CML1=y
# CONFIG_PARPORT_SERIAL is not set
CONFIG_PARPORT_PC_FIFO=y CONFIG_PARPORT_PC_FIFO=y
CONFIG_PARPORT_PC_SUPERIO=y CONFIG_PARPORT_PC_SUPERIO=y
# CONFIG_PARPORT_ARC is not set # CONFIG_PARPORT_ARC is not set
...@@ -217,7 +202,6 @@ CONFIG_MTD_CFI_INTELEXT=y ...@@ -217,7 +202,6 @@ CONFIG_MTD_CFI_INTELEXT=y
# #
# Plug and Play support # Plug and Play support
# #
# CONFIG_PNP is not set
# #
# Block devices # Block devices
...@@ -258,23 +242,21 @@ CONFIG_IP_PNP_BOOTP=y ...@@ -258,23 +242,21 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_NET_IPIP is not set # CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set # CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set # CONFIG_ARPD is not set
# CONFIG_INET_ECN is not set
# CONFIG_SYN_COOKIES is not set # CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set # CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set # CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set # CONFIG_INET_IPCOMP is not set
# CONFIG_IPV6 is not set # CONFIG_IPV6 is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_NETFILTER is not set # CONFIG_NETFILTER is not set
# #
# SCTP Configuration (EXPERIMENTAL) # SCTP Configuration (EXPERIMENTAL)
# #
CONFIG_IPV6_SCTP__=y
# CONFIG_IP_SCTP is not set # CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set # CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set # CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set # CONFIG_LLC2 is not set
# CONFIG_IPX is not set # CONFIG_IPX is not set
# CONFIG_ATALK is not set # CONFIG_ATALK is not set
...@@ -290,11 +272,17 @@ CONFIG_IPV6_SCTP__=y ...@@ -290,11 +272,17 @@ CONFIG_IPV6_SCTP__=y
# QoS and/or fair queueing # QoS and/or fair queueing
# #
# CONFIG_NET_SCHED is not set # CONFIG_NET_SCHED is not set
# CONFIG_NET_CLS_ROUTE is not set
# #
# Network testing # Network testing
# #
# CONFIG_NET_PKTGEN is not set # CONFIG_NET_PKTGEN is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set # CONFIG_DUMMY is not set
# CONFIG_BONDING is not set # CONFIG_BONDING is not set
...@@ -315,40 +303,25 @@ CONFIG_NET_ETHERNET=y ...@@ -315,40 +303,25 @@ CONFIG_NET_ETHERNET=y
# #
# Ethernet (10000 Mbit) # Ethernet (10000 Mbit)
# #
# CONFIG_PLIP is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# #
# Wireless LAN (non-hamradio) # Token Ring devices
# #
# CONFIG_NET_RADIO is not set
# CONFIG_HOSTAP is not set
# #
# Token Ring devices # Wireless LAN (non-hamradio)
# #
# CONFIG_SHAPER is not set # CONFIG_NET_RADIO is not set
# #
# Wan interfaces # Wan interfaces
# #
# CONFIG_WAN is not set # CONFIG_WAN is not set
# CONFIG_PLIP is not set
# # CONFIG_PPP is not set
# Amateur Radio support # CONFIG_SLIP is not set
# # CONFIG_SHAPER is not set
# CONFIG_HAMRADIO is not set # CONFIG_NETCONSOLE is not set
#
# IrDA (infrared) support
#
# CONFIG_IRDA is not set
#
# Bluetooth support
#
# CONFIG_BT is not set
# #
# ATA/ATAPI/MFM/RLL support # ATA/ATAPI/MFM/RLL support
...@@ -359,9 +332,9 @@ CONFIG_BLK_DEV_IDE=y ...@@ -359,9 +332,9 @@ CONFIG_BLK_DEV_IDE=y
# #
# Please see Documentation/ide.txt for help/info on IDE drives # Please see Documentation/ide.txt for help/info on IDE drives
# #
# CONFIG_BLK_DEV_IDE_SATA is not set
CONFIG_BLK_DEV_IDEDISK=y CONFIG_BLK_DEV_IDEDISK=y
# CONFIG_IDEDISK_MULTI_MODE is not set # CONFIG_IDEDISK_MULTI_MODE is not set
# CONFIG_IDEDISK_STROKE is not set
CONFIG_BLK_DEV_IDECD=y CONFIG_BLK_DEV_IDECD=y
CONFIG_BLK_DEV_IDETAPE=m CONFIG_BLK_DEV_IDETAPE=m
CONFIG_BLK_DEV_IDEFLOPPY=m CONFIG_BLK_DEV_IDEFLOPPY=m
...@@ -371,10 +344,10 @@ CONFIG_BLK_DEV_IDEFLOPPY=m ...@@ -371,10 +344,10 @@ CONFIG_BLK_DEV_IDEFLOPPY=m
# #
# IDE chipset support/bugfixes # IDE chipset support/bugfixes
# #
CONFIG_BLK_DEV_IDE_BAST=y CONFIG_IDE_GENERIC=y
# CONFIG_IDE_ARM is not set
# CONFIG_BLK_DEV_IDEDMA is not set # CONFIG_BLK_DEV_IDEDMA is not set
# CONFIG_IDEDMA_AUTO is not set # CONFIG_IDEDMA_AUTO is not set
# CONFIG_DMA_NONPCI is not set
# CONFIG_BLK_DEV_HD is not set # CONFIG_BLK_DEV_HD is not set
# #
...@@ -382,6 +355,15 @@ CONFIG_BLK_DEV_IDE_BAST=y ...@@ -382,6 +355,15 @@ CONFIG_BLK_DEV_IDE_BAST=y
# #
# CONFIG_SCSI is not set # CONFIG_SCSI is not set
#
# Fusion MPT device support
#
#
# IEEE 1394 (FireWire) support
#
# CONFIG_IEEE1394 is not set
# #
# I2O device support # I2O device support
# #
...@@ -389,7 +371,7 @@ CONFIG_BLK_DEV_IDE_BAST=y ...@@ -389,7 +371,7 @@ CONFIG_BLK_DEV_IDE_BAST=y
# #
# ISDN subsystem # ISDN subsystem
# #
# CONFIG_ISDN_BOOL is not set # CONFIG_ISDN is not set
# #
# Input device support # Input device support
...@@ -405,7 +387,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ...@@ -405,7 +387,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_TSLIBDEV is not set
# CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set # CONFIG_INPUT_EVBUG is not set
...@@ -415,7 +396,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ...@@ -415,7 +396,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_GAMEPORT is not set # CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y CONFIG_SOUND_GAMEPORT=y
CONFIG_SERIO=y CONFIG_SERIO=y
CONFIG_SERIO_I8042=y # CONFIG_SERIO_I8042 is not set
CONFIG_SERIO_SERPORT=y CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set # CONFIG_SERIO_CT82C710 is not set
# CONFIG_SERIO_PARKBD is not set # CONFIG_SERIO_PARKBD is not set
...@@ -424,14 +405,15 @@ CONFIG_SERIO_SERPORT=y ...@@ -424,14 +405,15 @@ CONFIG_SERIO_SERPORT=y
# Input Device Drivers # Input Device Drivers
# #
CONFIG_INPUT_KEYBOARD=y CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ATKBD=y # CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set # CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_NEWTON is not set
CONFIG_INPUT_MOUSE=y CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y CONFIG_MOUSE_PS2=y
# CONFIG_MOUSE_PS2_SYNAPTICS is not set
# CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set # CONFIG_INPUT_MISC is not set
...@@ -478,15 +460,40 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y ...@@ -478,15 +460,40 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
# #
CONFIG_SERIAL_S3C2410=y CONFIG_SERIAL_S3C2410=y
CONFIG_SERIAL_S3C2410_CONSOLE=y CONFIG_SERIAL_S3C2410_CONSOLE=y
# CONFIG_SERIAL_DZ is not set # CONFIG_SERIAL_BAST_SIO is not set
CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256 CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
CONFIG_PRINTER=y CONFIG_PRINTER=y
# CONFIG_LP_CONSOLE is not set # CONFIG_LP_CONSOLE is not set
CONFIG_PPDEV=y CONFIG_PPDEV=y
# CONFIG_TIPAR is not set # CONFIG_TIPAR is not set
# CONFIG_QIC02_TAPE is not set
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_NVRAM is not set
CONFIG_RTC=y
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# #
# I2C support # I2C support
...@@ -505,55 +512,44 @@ CONFIG_I2C_ALGOBIT=m ...@@ -505,55 +512,44 @@ CONFIG_I2C_ALGOBIT=m
# #
# CONFIG_I2C_AMD756 is not set # CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set # CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_PHILIPSPAR is not set # CONFIG_I2C_ISA is not set
# CONFIG_I2C_PARPORT is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_SCx200_ACB is not set # CONFIG_SCx200_ACB is not set
# #
# I2C Hardware Sensors Chip support # Hardware Sensors Chip support
# #
CONFIG_I2C_SENSOR=m CONFIG_I2C_SENSOR=m
# CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1021 is not set
CONFIG_SENSORS_EEPROM=m # CONFIG_SENSORS_ASB100 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_FSCHER is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_IT87 is not set
CONFIG_SENSORS_LM75=m CONFIG_SENSORS_LM75=m
CONFIG_SENSORS_LM78=m CONFIG_SENSORS_LM78=m
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
CONFIG_SENSORS_LM85=m CONFIG_SENSORS_LM85=m
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83627HF is not set
# #
# L3 serial bus support # Other I2C Chip support
#
# CONFIG_L3 is not set
#
# Mice
#
# CONFIG_BUSMOUSE is not set
# CONFIG_QIC02_TAPE is not set
#
# IPMI
# #
# CONFIG_IPMI_HANDLER is not set CONFIG_SENSORS_EEPROM=m
# CONFIG_SENSORS_PCF8574 is not set
# # CONFIG_SENSORS_PCF8591 is not set
# Watchdog Cards # CONFIG_SENSORS_RTC8564 is not set
# # CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_WATCHDOG is not set # CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_NVRAM is not set # CONFIG_I2C_DEBUG_BUS is not set
CONFIG_RTC=y # CONFIG_I2C_DEBUG_CHIP is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# #
# Multimedia devices # Multimedia devices
...@@ -565,11 +561,6 @@ CONFIG_RTC=y ...@@ -565,11 +561,6 @@ CONFIG_RTC=y
# #
# CONFIG_DVB is not set # CONFIG_DVB is not set
#
# MMC/SD Card support
#
# CONFIG_MMC is not set
# #
# File systems # File systems
# #
...@@ -603,14 +594,16 @@ CONFIG_ROMFS_FS=y ...@@ -603,14 +594,16 @@ CONFIG_ROMFS_FS=y
CONFIG_FAT_FS=y CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_NTFS_FS is not set # CONFIG_NTFS_FS is not set
# #
# Pseudo filesystems # Pseudo filesystems
# #
CONFIG_PROC_FS=y CONFIG_PROC_FS=y
CONFIG_SYSFS=y
# CONFIG_DEVFS_FS is not set # CONFIG_DEVFS_FS is not set
CONFIG_DEVPTS_FS=y
# CONFIG_DEVPTS_FS_XATTR is not set # CONFIG_DEVPTS_FS_XATTR is not set
# CONFIG_TMPFS is not set # CONFIG_TMPFS is not set
# CONFIG_HUGETLBFS is not set # CONFIG_HUGETLBFS is not set
...@@ -623,6 +616,7 @@ CONFIG_RAMFS=y ...@@ -623,6 +616,7 @@ CONFIG_RAMFS=y
# CONFIG_ADFS_FS is not set # CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set # CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set # CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set # CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set # CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set # CONFIG_EFS_FS is not set
...@@ -650,12 +644,11 @@ CONFIG_ROOT_NFS=y ...@@ -650,12 +644,11 @@ CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y CONFIG_LOCKD=y
# CONFIG_EXPORTFS is not set # CONFIG_EXPORTFS is not set
CONFIG_SUNRPC=y CONFIG_SUNRPC=y
# CONFIG_SUNRPC_GSS is not set # CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_SMB_FS is not set # CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set # CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set # CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set # CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
# CONFIG_AFS_FS is not set # CONFIG_AFS_FS is not set
# #
...@@ -679,16 +672,15 @@ CONFIG_BSD_DISKLABEL=y ...@@ -679,16 +672,15 @@ CONFIG_BSD_DISKLABEL=y
CONFIG_SOLARIS_X86_PARTITION=y CONFIG_SOLARIS_X86_PARTITION=y
# CONFIG_UNIXWARE_DISKLABEL is not set # CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set # CONFIG_LDM_PARTITION is not set
# CONFIG_NEC98_PARTITION is not set
# CONFIG_SGI_PARTITION is not set # CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set # CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set # CONFIG_SUN_PARTITION is not set
# CONFIG_EFI_PARTITION is not set # CONFIG_EFI_PARTITION is not set
CONFIG_NLS=y
# #
# Native Language Support # Native Language Support
# #
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_CODEPAGE_437 is not set # CONFIG_NLS_CODEPAGE_437 is not set
# CONFIG_NLS_CODEPAGE_737 is not set # CONFIG_NLS_CODEPAGE_737 is not set
...@@ -713,6 +705,7 @@ CONFIG_NLS_DEFAULT="iso8859-1" ...@@ -713,6 +705,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_ISO8859_8 is not set # CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set # CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set # CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
# CONFIG_NLS_ISO8859_1 is not set # CONFIG_NLS_ISO8859_1 is not set
# CONFIG_NLS_ISO8859_2 is not set # CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set # CONFIG_NLS_ISO8859_3 is not set
...@@ -728,6 +721,11 @@ CONFIG_NLS_DEFAULT="iso8859-1" ...@@ -728,6 +721,11 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set # CONFIG_NLS_UTF8 is not set
#
# Profiling support
#
# CONFIG_PROFILING is not set
# #
# Graphics support # Graphics support
# #
...@@ -748,21 +746,20 @@ CONFIG_DUMMY_CONSOLE=y ...@@ -748,21 +746,20 @@ CONFIG_DUMMY_CONSOLE=y
# CONFIG_LOGO is not set # CONFIG_LOGO is not set
# #
# Misc devices # Sound
# #
# CONFIG_SOUND is not set
# #
# Multimedia Capabilities Port drivers # Misc devices
# #
# CONFIG_MCP is not set
# #
# Console Switches # USB support
# #
# CONFIG_SWITCHES is not set
# #
# USB support # USB Gadget Support
# #
# CONFIG_USB_GADGET is not set # CONFIG_USB_GADGET is not set
...@@ -780,7 +777,7 @@ CONFIG_DEBUG_KERNEL=y ...@@ -780,7 +777,7 @@ CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_DEBUG_ERRORS is not set # CONFIG_DEBUG_ERRORS is not set
CONFIG_DEBUG_LL=y CONFIG_DEBUG_LL=y
CONFIG_DEBUG_LL_PRINTK=y # CONFIG_DEBUG_ICEDCC is not set
CONFIG_DEBUG_S3C2410_PORT=y CONFIG_DEBUG_S3C2410_PORT=y
CONFIG_DEBUG_S3C2410_UART=0 CONFIG_DEBUG_S3C2410_UART=0
...@@ -797,6 +794,8 @@ CONFIG_DEBUG_S3C2410_UART=0 ...@@ -797,6 +794,8 @@ CONFIG_DEBUG_S3C2410_UART=0
# #
# Library routines # Library routines
# #
# CONFIG_CRC_CCITT is not set
CONFIG_CRC32=y CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y CONFIG_ZLIB_DEFLATE=y
arch/arm/kernel/entry-armv.S
View file @ a2769608
...@@ -952,7 +952,7 @@ __dabt_svc: sub sp, sp, #S_FRAME_SIZE ...@@ -952,7 +952,7 @@ __dabt_svc: sub sp, sp, #S_FRAME_SIZE
bl do_DataAbort bl do_DataAbort
disable_irq r0 disable_irq r0
ldr r0, [sp, #S_PSR] ldr r0, [sp, #S_PSR]
msr spsr, r0 msr spsr_cxsf, r0
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
.align 5 .align 5
...@@ -988,7 +988,7 @@ preempt_return: ...@@ -988,7 +988,7 @@ preempt_return:
strne r0, [r0, -r0] @ bug() strne r0, [r0, -r0] @ bug()
#endif #endif
ldr r0, [sp, #S_PSR] @ irqs are already disabled ldr r0, [sp, #S_PSR] @ irqs are already disabled
msr spsr, r0 msr spsr_cxsf, r0
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
.ltorg .ltorg
...@@ -1031,7 +1031,7 @@ __und_svc: sub sp, sp, #S_FRAME_SIZE ...@@ -1031,7 +1031,7 @@ __und_svc: sub sp, sp, #S_FRAME_SIZE
1: disable_irq r0 1: disable_irq r0
ldr lr, [sp, #S_PSR] @ Get SVC cpsr ldr lr, [sp, #S_PSR] @ Get SVC cpsr
msr spsr, lr msr spsr_cxsf, lr
ldmia sp, {r0 - pc}^ @ Restore SVC registers ldmia sp, {r0 - pc}^ @ Restore SVC registers
.align 5 .align 5
...@@ -1052,7 +1052,7 @@ __pabt_svc: sub sp, sp, #S_FRAME_SIZE ...@@ -1052,7 +1052,7 @@ __pabt_svc: sub sp, sp, #S_FRAME_SIZE
bl do_PrefetchAbort @ call abort handler bl do_PrefetchAbort @ call abort handler
disable_irq r0 disable_irq r0
ldr r0, [sp, #S_PSR] ldr r0, [sp, #S_PSR]
msr spsr, r0 msr spsr_cxsf, r0
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
.align 5 .align 5
...@@ -1303,7 +1303,7 @@ vector_IRQ: @ ...@@ -1303,7 +1303,7 @@ vector_IRQ: @
mrs r13, cpsr mrs r13, cpsr
bic r13, r13, #MODE_MASK bic r13, r13, #MODE_MASK
orr r13, r13, #MODE_SVC orr r13, r13, #MODE_SVC
msr spsr, r13 @ switch to SVC_32 mode msr spsr_cxsf, r13 @ switch to SVC_32 mode
and lr, lr, #15 and lr, lr, #15
ldr lr, [pc, lr, lsl #2] ldr lr, [pc, lr, lsl #2]
...@@ -1346,7 +1346,7 @@ vector_data: @ ...@@ -1346,7 +1346,7 @@ vector_data: @
mrs r13, cpsr mrs r13, cpsr
bic r13, r13, #MODE_MASK bic r13, r13, #MODE_MASK
orr r13, r13, #MODE_SVC orr r13, r13, #MODE_SVC
msr spsr, r13 @ switch to SVC_32 mode msr spsr_cxsf, r13 @ switch to SVC_32 mode
and lr, lr, #15 and lr, lr, #15
ldr lr, [pc, lr, lsl #2] ldr lr, [pc, lr, lsl #2]
...@@ -1390,7 +1390,7 @@ vector_prefetch: ...@@ -1390,7 +1390,7 @@ vector_prefetch:
mrs r13, cpsr mrs r13, cpsr
bic r13, r13, #MODE_MASK bic r13, r13, #MODE_MASK
orr r13, r13, #MODE_SVC orr r13, r13, #MODE_SVC
msr spsr, r13 @ switch to SVC_32 mode msr spsr_cxsf, r13 @ switch to SVC_32 mode
ands lr, lr, #15 ands lr, lr, #15
ldr lr, [pc, lr, lsl #2] ldr lr, [pc, lr, lsl #2]
...@@ -1433,7 +1433,7 @@ vector_undefinstr: ...@@ -1433,7 +1433,7 @@ vector_undefinstr:
mrs r13, cpsr mrs r13, cpsr
bic r13, r13, #MODE_MASK bic r13, r13, #MODE_MASK
orr r13, r13, #MODE_SVC orr r13, r13, #MODE_SVC
msr spsr, r13 @ switch to SVC_32 mode msr spsr_cxsf, r13 @ switch to SVC_32 mode
and lr, lr, #15 and lr, lr, #15
ldr lr, [pc, lr, lsl #2] ldr lr, [pc, lr, lsl #2]
......
arch/arm/kernel/entry-common.S
View file @ a2769608
...@@ -102,7 +102,7 @@ ENTRY(ret_from_fork) ...@@ -102,7 +102,7 @@ ENTRY(ret_from_fork)
ldr r0, [sp, #S_PSR] @ Get calling cpsr ldr r0, [sp, #S_PSR] @ Get calling cpsr
sub lr, lr, #4 sub lr, lr, #4
str lr, [r8] str lr, [r8]
msr spsr, r0 msr spsr_cxsf, r0
ldmia sp, {r0 - lr}^ @ Get calling r0 - lr ldmia sp, {r0 - lr}^ @ Get calling r0 - lr
mov r0, r0 mov r0, r0
ldr lr, [sp, #S_PC] @ Get PC ldr lr, [sp, #S_PC] @ Get PC
......
arch/arm/kernel/entry-header.S
View file @ a2769608
...@@ -99,7 +99,7 @@ ...@@ -99,7 +99,7 @@
ldr r1, [sp, #S_PSR] @ Get calling cpsr ldr r1, [sp, #S_PSR] @ Get calling cpsr
disable_irq ip @ disable IRQs disable_irq ip @ disable IRQs
ldr lr, [sp, #S_PC]! @ Get PC ldr lr, [sp, #S_PC]! @ Get PC
msr spsr, r1 @ save in spsr_svc msr spsr_cxsf, r1 @ save in spsr_svc
ldmdb sp, {r0 - lr}^ @ Get calling r0 - lr ldmdb sp, {r0 - lr}^ @ Get calling r0 - lr
mov r0, r0 mov r0, r0
add sp, sp, #S_FRAME_SIZE - S_PC add sp, sp, #S_FRAME_SIZE - S_PC
...@@ -112,7 +112,7 @@ ...@@ -112,7 +112,7 @@
.macro fast_restore_user_regs .macro fast_restore_user_regs
ldr r1, [sp, #S_OFF + S_PSR] @ get calling cpsr ldr r1, [sp, #S_OFF + S_PSR] @ get calling cpsr
ldr lr, [sp, #S_OFF + S_PC]! @ get pc ldr lr, [sp, #S_OFF + S_PC]! @ get pc
msr spsr, r1 @ save in spsr_svc msr spsr_cxsf, r1 @ save in spsr_svc
ldmdb sp, {r1 - lr}^ @ get calling r1 - lr ldmdb sp, {r1 - lr}^ @ get calling r1 - lr
mov r0, r0 mov r0, r0
add sp, sp, #S_FRAME_SIZE - S_PC add sp, sp, #S_FRAME_SIZE - S_PC
...@@ -125,7 +125,7 @@ ...@@ -125,7 +125,7 @@
.macro slow_restore_user_regs .macro slow_restore_user_regs
ldr r1, [sp, #S_PSR] @ get calling cpsr ldr r1, [sp, #S_PSR] @ get calling cpsr
ldr lr, [sp, #S_PC]! @ get pc ldr lr, [sp, #S_PC]! @ get pc
msr spsr, r1 @ save in spsr_svc msr spsr_cxsf, r1 @ save in spsr_svc
ldmdb sp, {r0 - lr}^ @ get calling r1 - lr ldmdb sp, {r0 - lr}^ @ get calling r1 - lr
mov r0, r0 mov r0, r0
add sp, sp, #S_FRAME_SIZE - S_PC add sp, sp, #S_FRAME_SIZE - S_PC
......
arch/arm/lib/ecard.S
View file @ a2769608
...@@ -16,7 +16,7 @@ ...@@ -16,7 +16,7 @@
#define CPSR2SPSR(rt) \ #define CPSR2SPSR(rt) \
mrs rt, cpsr; \ mrs rt, cpsr; \
msr spsr, rt msr spsr_cxsf, rt
@ Purpose: call an expansion card loader to read bytes. @ Purpose: call an expansion card loader to read bytes.
@ Proto : char read_loader(int offset, char *card_base, char *loader); @ Proto : char read_loader(int offset, char *card_base, char *loader);
......
arch/arm/mach-s3c2410/Makefile
View file @ a2769608
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
# Object file lists. # Object file lists.
obj-y := s3c2410.o irq.o time.o obj-y := s3c2410.o irq.o time.o gpio.o
obj-m := obj-m :=
obj-n := obj-n :=
obj- := obj- :=
......
arch/arm/mach-s3c2410/gpio.c 0 → 100644
View file @ a2769608
/* linux/arch/arm/mach-s3c2410/gpio.c
*
* Copyright (c) 2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 GPIO support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/arch/regs-gpio.h>
void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
{
unsigned long base = S3C2410_GPIO_BASE(pin);
unsigned long shift = 1;
unsigned long mask = 3;
unsigned long con;
unsigned long flags;
if (pin < S3C2410_GPIO_BANKB) {
shift = 0;
mask = 1;
}
mask <<= S3C2410_GPIO_OFFSET(pin);
local_irq_save(flags);
con = __raw_readl(base + 0x00);
con &= mask << shift;
con |= function;
__raw_writel(con, base + 0x00);
local_irq_restore(flags);
}
void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
{
unsigned long base = S3C2410_GPIO_BASE(pin);
unsigned long offs = S3C2410_GPIO_OFFSET(pin);
unsigned long flags;
unsigned long up;
if (pin < S3C2410_GPIO_BANKB)
return;
local_irq_save(flags);
up = __raw_readl(base + 0x08);
up &= 1 << offs;
up |= to << offs;
__raw_writel(up, base + 0x08);
local_irq_restore(flags);
}
void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
{
unsigned long base = S3C2410_GPIO_BASE(pin);
unsigned long offs = S3C2410_GPIO_OFFSET(pin);
unsigned long flags;
unsigned long dat;
local_irq_save(flags);
dat = __raw_readl(base + 0x04);
dat &= 1 << offs;
dat |= to << offs;
__raw_writel(dat, base + 0x04);
local_irq_restore(flags);
}
arch/arm/mach-s3c2410/mach-h1940.c
View file @ a2769608
...@@ -52,7 +52,7 @@ static struct s3c2410_uartcfg ipaq_uartcfgs[] = { ...@@ -52,7 +52,7 @@ static struct s3c2410_uartcfg ipaq_uartcfgs[] = {
[0] = { [0] = {
.hwport = 0, .hwport = 0,
.flags = 0, .flags = 0,
.clock = &s3c2410_hclk, .clock = &s3c2410_pclk,
.ucon = 0x3c5, .ucon = 0x3c5,
.ulcon = 0x03, .ulcon = 0x03,
.ufcon = 0x51, .ufcon = 0x51,
...@@ -60,7 +60,7 @@ static struct s3c2410_uartcfg ipaq_uartcfgs[] = { ...@@ -60,7 +60,7 @@ static struct s3c2410_uartcfg ipaq_uartcfgs[] = {
[1] = { [1] = {
.hwport = 1, .hwport = 1,
.flags = 0, .flags = 0,
.clock = &s3c2410_hclk, .clock = &s3c2410_pclk,
.ucon = 0x245, .ucon = 0x245,
.ulcon = 0x03, .ulcon = 0x03,
.ufcon = 0x00, .ufcon = 0x00,
...@@ -69,7 +69,7 @@ static struct s3c2410_uartcfg ipaq_uartcfgs[] = { ...@@ -69,7 +69,7 @@ static struct s3c2410_uartcfg ipaq_uartcfgs[] = {
[2] = { [2] = {
.hwport = 2, .hwport = 2,
.flags = 0, .flags = 0,
.clock = &s3c2410_hclk, .clock = &s3c2410_pclk,
.ucon = 0x3c5, .ucon = 0x3c5,
.ulcon = 0x43, .ulcon = 0x43,
.ufcon = 0x51, .ufcon = 0x51,
......
arch/arm/mach-s3c2410/s3c2410.h
View file @ a2769608
...@@ -4,5 +4,5 @@ extern void s3c2410_map_io(struct map_desc *, int count); ...@@ -4,5 +4,5 @@ extern void s3c2410_map_io(struct map_desc *, int count);
extern void s3c2410_init_irq(void); extern void s3c2410_init_irq(void);
extern s3c2410_init_time(void); extern void s3c2410_init_time(void);
arch/arm/mach-sa1100/collie.c
View file @ a2769608
...@@ -141,4 +141,5 @@ MACHINE_START(COLLIE, "Sharp-Collie") ...@@ -141,4 +141,5 @@ MACHINE_START(COLLIE, "Sharp-Collie")
MAPIO(collie_map_io) MAPIO(collie_map_io)
INITIRQ(sa1100_init_irq) INITIRQ(sa1100_init_irq)
INIT_MACHINE(collie_init) INIT_MACHINE(collie_init)
INITTIME(sa1100_init_time)
MACHINE_END MACHINE_END
arch/arm/mm/blockops.c
View file @ a2769608
...@@ -130,6 +130,7 @@ static struct undef_hook blockops_hook __initdata = { ...@@ -130,6 +130,7 @@ static struct undef_hook blockops_hook __initdata = {
static int __init blockops_check(void) static int __init blockops_check(void)
{ {
register unsigned int err asm("r4") = 0; register unsigned int err asm("r4") = 0;
unsigned int err_pos = 1;
unsigned int cache_type; unsigned int cache_type;
int i; int i;
...@@ -156,8 +157,8 @@ static int __init blockops_check(void) ...@@ -156,8 +157,8 @@ static int __init blockops_check(void)
unregister_undef_hook(&blockops_hook); unregister_undef_hook(&blockops_hook);
for (i = 0; i < ARRAY_SIZE(func); i++, err >>= 1) for (i = 0; i < ARRAY_SIZE(func); i++, err_pos <<= 1)
printk("%30s: %ssupported\n", func[i], err & 1 ? "not " : ""); printk("%30s: %ssupported\n", func[i], err & err_pos ? "not " : "");
if ((err & 8) == 0) { if ((err & 8) == 0) {
printk(" --> Using %s block cache invalidate\n", printk(" --> Using %s block cache invalidate\n",
......
arch/i386/Makefile
View file @ a2769608
...@@ -104,8 +104,7 @@ head-y := arch/i386/kernel/head.o arch/i386/kernel/init_task.o ...@@ -104,8 +104,7 @@ head-y := arch/i386/kernel/head.o arch/i386/kernel/init_task.o
libs-y += arch/i386/lib/ libs-y += arch/i386/lib/
core-y += arch/i386/kernel/ \ core-y += arch/i386/kernel/ \
arch/i386/mm/ \ arch/i386/mm/ \
arch/i386/$(mcore-y)/ \ arch/i386/$(mcore-y)/
arch/i386/crypto/
drivers-$(CONFIG_MATH_EMULATION) += arch/i386/math-emu/ drivers-$(CONFIG_MATH_EMULATION) += arch/i386/math-emu/
drivers-$(CONFIG_PCI) += arch/i386/pci/ drivers-$(CONFIG_PCI) += arch/i386/pci/
# must be linked after kernel/ # must be linked after kernel/
......
arch/i386/crypto/Makefile deleted 100644 → 0
View file @ 6909f28b
#
# i386/crypto/Makefile
#
# Arch-specific CryptoAPI modules.
#
obj-$(CONFIG_CRYPTO_AES_586) += aes-i586.o
aes-i586-y := aes-i586-asm.o aes-i586-glue.o
arch/i386/crypto/aes-i586-asm.S deleted 100644 → 0
View file @ 6909f28b
// Copyright (c) 2001, Dr Brian Gladman <brg@gladman.uk.net>, Worcester, UK.
// All rights reserved.
//
// TERMS
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted subject to the following conditions:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. The copyright holder's name must not be used to endorse or promote
// any products derived from this software without his specific prior
// written permission.
//
// ALTERNATIVELY, provided that this notice is retained in full, this product
// may be distributed under the terms of the GNU General Public License (GPL),
// in which case the provisions of the GPL apply INSTEAD OF those given above.
//
// This software is provided 'as is' with no express or implied warranties
// of correctness or fitness for purpose.
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
// Modified by Jari Ruusu, December 24 2001
// - Converted syntax to GNU CPP/assembler syntax
// - C programming interface converted back to "old" API
// - Minor portability cleanups and speed optimizations
// Modified by Jari Ruusu, April 11 2002
// - Added above copyright and terms to resulting object code so that
// binary distributions can avoid legal trouble
// Modified by Clemens Fruhwirth, Feb 04 2003
// - Switched in/out to fit CryptoAPI calls.
// Modified by James Morris, July 31 2004
// - Added alternate GPL licensing clause with permission from Dr Gladman.
// An AES (Rijndael) implementation for the Pentium. This version only
// implements the standard AES block length (128 bits, 16 bytes). This code
// does not preserve the eax, ecx or edx registers or the artihmetic status
// flags. However, the ebx, esi, edi, and ebp registers are preserved across
// calls.
// void aes_set_key(aes_context *cx, const unsigned char key[], const int key_len, const int f)
// void aes_encrypt(const aes_context *cx, unsigned char out_blk[], const unsigned char in_blk[])
// void aes_decrypt(const aes_context *cx, unsigned char out_blk[], const unsigned char in_blk[])
# define ALIGN32BYTES 32
.file "aes-i586.S"
.globl aes_set_key
.globl aes_encrypt
.globl aes_decrypt
#define tlen 1024 // length of each of 4 'xor' arrays (256 32-bit words)
// offsets to parameters with one register pushed onto stack
#define ctx 8 // AES context structure
#define out_blk 12 // output byte array address parameter
#define in_blk 16 // input byte array address parameter
// offsets in context structure
#define nkey 0 // key length, size 4
#define nrnd 4 // number of rounds, size 4
#define ekey 8 // encryption key schedule base address, size 256
#define dkey 264 // decryption key schedule base address, size 256
// This macro performs a forward encryption cycle. It is entered with
// the first previous round column values in %eax, %ebx, %esi and %edi and
// exits with the final values in the same registers.
#define fwd_rnd(p1,p2) \
mov %ebx,(%esp) ;\
movzbl %al,%edx ;\
mov %eax,%ecx ;\
mov p2(%ebp),%eax ;\
mov %edi,4(%esp) ;\
mov p2+12(%ebp),%edi ;\
xor p1(,%edx,4),%eax ;\
movzbl %ch,%edx ;\
shr $16,%ecx ;\
mov p2+4(%ebp),%ebx ;\
xor p1+tlen(,%edx,4),%edi ;\
movzbl %cl,%edx ;\
movzbl %ch,%ecx ;\
xor p1+3*tlen(,%ecx,4),%ebx ;\
mov %esi,%ecx ;\
mov p1+2*tlen(,%edx,4),%esi ;\
movzbl %cl,%edx ;\
xor p1(,%edx,4),%esi ;\
movzbl %ch,%edx ;\
shr $16,%ecx ;\
xor p1+tlen(,%edx,4),%ebx ;\
movzbl %cl,%edx ;\
movzbl %ch,%ecx ;\
xor p1+2*tlen(,%edx,4),%eax ;\
mov (%esp),%edx ;\
xor p1+3*tlen(,%ecx,4),%edi ;\
movzbl %dl,%ecx ;\
xor p2+8(%ebp),%esi ;\
xor p1(,%ecx,4),%ebx ;\
movzbl %dh,%ecx ;\
shr $16,%edx ;\
xor p1+tlen(,%ecx,4),%eax ;\
movzbl %dl,%ecx ;\
movzbl %dh,%edx ;\
xor p1+2*tlen(,%ecx,4),%edi ;\
mov 4(%esp),%ecx ;\
xor p1+3*tlen(,%edx,4),%esi ;\
movzbl %cl,%edx ;\
xor p1(,%edx,4),%edi ;\
movzbl %ch,%edx ;\
shr $16,%ecx ;\
xor p1+tlen(,%edx,4),%esi ;\
movzbl %cl,%edx ;\
movzbl %ch,%ecx ;\
xor p1+2*tlen(,%edx,4),%ebx ;\
xor p1+3*tlen(,%ecx,4),%eax
// This macro performs an inverse encryption cycle. It is entered with
// the first previous round column values in %eax, %ebx, %esi and %edi and
// exits with the final values in the same registers.
#define inv_rnd(p1,p2) \
movzbl %al,%edx ;\
mov %ebx,(%esp) ;\
mov %eax,%ecx ;\
mov p2(%ebp),%eax ;\
mov %edi,4(%esp) ;\
mov p2+4(%ebp),%ebx ;\
xor p1(,%edx,4),%eax ;\
movzbl %ch,%edx ;\
shr $16,%ecx ;\
mov p2+12(%ebp),%edi ;\
xor p1+tlen(,%edx,4),%ebx ;\
movzbl %cl,%edx ;\
movzbl %ch,%ecx ;\
xor p1+3*tlen(,%ecx,4),%edi ;\
mov %esi,%ecx ;\
mov p1+2*tlen(,%edx,4),%esi ;\
movzbl %cl,%edx ;\
xor p1(,%edx,4),%esi ;\
movzbl %ch,%edx ;\
shr $16,%ecx ;\
xor p1+tlen(,%edx,4),%edi ;\
movzbl %cl,%edx ;\
movzbl %ch,%ecx ;\
xor p1+2*tlen(,%edx,4),%eax ;\
mov (%esp),%edx ;\
xor p1+3*tlen(,%ecx,4),%ebx ;\
movzbl %dl,%ecx ;\
xor p2+8(%ebp),%esi ;\
xor p1(,%ecx,4),%ebx ;\
movzbl %dh,%ecx ;\
shr $16,%edx ;\
xor p1+tlen(,%ecx,4),%esi ;\
movzbl %dl,%ecx ;\
movzbl %dh,%edx ;\
xor p1+2*tlen(,%ecx,4),%edi ;\
mov 4(%esp),%ecx ;\
xor p1+3*tlen(,%edx,4),%eax ;\
movzbl %cl,%edx ;\
xor p1(,%edx,4),%edi ;\
movzbl %ch,%edx ;\
shr $16,%ecx ;\
xor p1+tlen(,%edx,4),%eax ;\
movzbl %cl,%edx ;\
movzbl %ch,%ecx ;\
xor p1+2*tlen(,%edx,4),%ebx ;\
xor p1+3*tlen(,%ecx,4),%esi
// AES (Rijndael) Encryption Subroutine
.text
.align ALIGN32BYTES
aes_encrypt:
push %ebp
mov ctx(%esp),%ebp // pointer to context
mov in_blk(%esp),%ecx
push %ebx
push %esi
push %edi
mov nrnd(%ebp),%edx // number of rounds
lea ekey+16(%ebp),%ebp // key pointer
// input four columns and xor in first round key
mov (%ecx),%eax
mov 4(%ecx),%ebx
mov 8(%ecx),%esi
mov 12(%ecx),%edi
xor -16(%ebp),%eax
xor -12(%ebp),%ebx
xor -8(%ebp),%esi
xor -4(%ebp),%edi
sub $8,%esp // space for register saves on stack
sub $10,%edx
je aes_15
add $32,%ebp
sub $2,%edx
je aes_13
add $32,%ebp
fwd_rnd(aes_ft_tab,-64) // 14 rounds for 256-bit key
fwd_rnd(aes_ft_tab,-48)
aes_13: fwd_rnd(aes_ft_tab,-32) // 12 rounds for 192-bit key
fwd_rnd(aes_ft_tab,-16)
aes_15: fwd_rnd(aes_ft_tab,0) // 10 rounds for 128-bit key
fwd_rnd(aes_ft_tab,16)
fwd_rnd(aes_ft_tab,32)
fwd_rnd(aes_ft_tab,48)
fwd_rnd(aes_ft_tab,64)
fwd_rnd(aes_ft_tab,80)
fwd_rnd(aes_ft_tab,96)
fwd_rnd(aes_ft_tab,112)
fwd_rnd(aes_ft_tab,128)
fwd_rnd(aes_fl_tab,144) // last round uses a different table
// move final values to the output array.
mov out_blk+20(%esp),%ebp
add $8,%esp
mov %eax,(%ebp)
mov %ebx,4(%ebp)
mov %esi,8(%ebp)
mov %edi,12(%ebp)
pop %edi
pop %esi
pop %ebx
pop %ebp
ret
// AES (Rijndael) Decryption Subroutine
.align ALIGN32BYTES
aes_decrypt:
push %ebp
mov ctx(%esp),%ebp // pointer to context
mov in_blk(%esp),%ecx
push %ebx
push %esi
push %edi
mov nrnd(%ebp),%edx // number of rounds
lea dkey+16(%ebp),%ebp // key pointer
// input four columns and xor in first round key
mov (%ecx),%eax
mov 4(%ecx),%ebx
mov 8(%ecx),%esi
mov 12(%ecx),%edi
xor -16(%ebp),%eax
xor -12(%ebp),%ebx
xor -8(%ebp),%esi
xor -4(%ebp),%edi
sub $8,%esp // space for register saves on stack
sub $10,%edx
je aes_25
add $32,%ebp
sub $2,%edx
je aes_23
add $32,%ebp
inv_rnd(aes_it_tab,-64) // 14 rounds for 256-bit key
inv_rnd(aes_it_tab,-48)
aes_23: inv_rnd(aes_it_tab,-32) // 12 rounds for 192-bit key
inv_rnd(aes_it_tab,-16)
aes_25: inv_rnd(aes_it_tab,0) // 10 rounds for 128-bit key
inv_rnd(aes_it_tab,16)
inv_rnd(aes_it_tab,32)
inv_rnd(aes_it_tab,48)
inv_rnd(aes_it_tab,64)
inv_rnd(aes_it_tab,80)
inv_rnd(aes_it_tab,96)
inv_rnd(aes_it_tab,112)
inv_rnd(aes_it_tab,128)
inv_rnd(aes_il_tab,144) // last round uses a different table
// move final values to the output array.
mov out_blk+20(%esp),%ebp
add $8,%esp
mov %eax,(%ebp)
mov %ebx,4(%ebp)
mov %esi,8(%ebp)
mov %edi,12(%ebp)
pop %edi
pop %esi
pop %ebx
pop %ebp
ret
// AES (Rijndael) Key Schedule Subroutine
// input/output parameters
#define aes_cx 12 // AES context
#define in_key 16 // key input array address
#define key_ln 20 // key length, bytes (16,24,32) or bits (128,192,256)
#define ed_flg 24 // 0=create both encr/decr keys, 1=create encr key only
// offsets for locals
#define cnt -4
#define kpf -8
#define slen 8
// This macro performs a column mixing operation on an input 32-bit
// word to give a 32-bit result. It uses each of the 4 bytes in the
// the input column to index 4 different tables of 256 32-bit words
// that are xored together to form the output value.
#define mix_col(p1) \
movzbl %bl,%ecx ;\
mov p1(,%ecx,4),%eax ;\
movzbl %bh,%ecx ;\
ror $16,%ebx ;\
xor p1+tlen(,%ecx,4),%eax ;\
movzbl %bl,%ecx ;\
xor p1+2*tlen(,%ecx,4),%eax ;\
movzbl %bh,%ecx ;\
xor p1+3*tlen(,%ecx,4),%eax
// Key Schedule Macros
#define ksc4(p1) \
rol $24,%ebx ;\
mix_col(aes_fl_tab) ;\
ror $8,%ebx ;\
xor 4*p1+aes_rcon_tab,%eax ;\
xor %eax,%esi ;\
xor %esi,%ebp ;\
mov %esi,16*p1(%edi) ;\
mov %ebp,16*p1+4(%edi) ;\
xor %ebp,%edx ;\
xor %edx,%ebx ;\
mov %edx,16*p1+8(%edi) ;\
mov %ebx,16*p1+12(%edi)
#define ksc6(p1) \
rol $24,%ebx ;\
mix_col(aes_fl_tab) ;\
ror $8,%ebx ;\
xor 4*p1+aes_rcon_tab,%eax ;\
xor 24*p1-24(%edi),%eax ;\
mov %eax,24*p1(%edi) ;\
xor 24*p1-20(%edi),%eax ;\
mov %eax,24*p1+4(%edi) ;\
xor %eax,%esi ;\
xor %esi,%ebp ;\
mov %esi,24*p1+8(%edi) ;\
mov %ebp,24*p1+12(%edi) ;\
xor %ebp,%edx ;\
xor %edx,%ebx ;\
mov %edx,24*p1+16(%edi) ;\
mov %ebx,24*p1+20(%edi)
#define ksc8(p1) \
rol $24,%ebx ;\
mix_col(aes_fl_tab) ;\
ror $8,%ebx ;\
xor 4*p1+aes_rcon_tab,%eax ;\
xor 32*p1-32(%edi),%eax ;\
mov %eax,32*p1(%edi) ;\
xor 32*p1-28(%edi),%eax ;\
mov %eax,32*p1+4(%edi) ;\
xor 32*p1-24(%edi),%eax ;\
mov %eax,32*p1+8(%edi) ;\
xor 32*p1-20(%edi),%eax ;\
mov %eax,32*p1+12(%edi) ;\
push %ebx ;\
mov %eax,%ebx ;\
mix_col(aes_fl_tab) ;\
pop %ebx ;\
xor %eax,%esi ;\
xor %esi,%ebp ;\
mov %esi,32*p1+16(%edi) ;\
mov %ebp,32*p1+20(%edi) ;\
xor %ebp,%edx ;\
xor %edx,%ebx ;\
mov %edx,32*p1+24(%edi) ;\
mov %ebx,32*p1+28(%edi)
.align ALIGN32BYTES
aes_set_key:
pushfl
push %ebp
mov %esp,%ebp
sub $slen,%esp
push %ebx
push %esi
push %edi
mov aes_cx(%ebp),%edx // edx -> AES context
mov key_ln(%ebp),%ecx // key length
cmpl $128,%ecx
jb aes_30
shr $3,%ecx
aes_30: cmpl $32,%ecx
je aes_32
cmpl $24,%ecx
je aes_32
mov $16,%ecx
aes_32: shr $2,%ecx
mov %ecx,nkey(%edx)
lea 6(%ecx),%eax // 10/12/14 for 4/6/8 32-bit key length
mov %eax,nrnd(%edx)
mov in_key(%ebp),%esi // key input array
lea ekey(%edx),%edi // key position in AES context
cld
push %ebp
mov %ecx,%eax // save key length in eax
rep ; movsl // words in the key schedule
mov -4(%esi),%ebx // put some values in registers
mov -8(%esi),%edx // to allow faster code
mov -12(%esi),%ebp
mov -16(%esi),%esi
cmpl $4,%eax // jump on key size
je aes_36
cmpl $6,%eax
je aes_35
ksc8(0)
ksc8(1)
ksc8(2)
ksc8(3)
ksc8(4)
ksc8(5)
ksc8(6)
jmp aes_37
aes_35: ksc6(0)
ksc6(1)
ksc6(2)
ksc6(3)
ksc6(4)
ksc6(5)
ksc6(6)
ksc6(7)
jmp aes_37
aes_36: ksc4(0)
ksc4(1)
ksc4(2)
ksc4(3)
ksc4(4)
ksc4(5)
ksc4(6)
ksc4(7)
ksc4(8)
ksc4(9)
aes_37: pop %ebp
mov aes_cx(%ebp),%edx // edx -> AES context
cmpl $0,ed_flg(%ebp)
jne aes_39
// compile decryption key schedule from encryption schedule - reverse
// order and do mix_column operation on round keys except first and last
mov nrnd(%edx),%eax // kt = cx->d_key + nc * cx->Nrnd
shl $2,%eax
lea dkey(%edx,%eax,4),%edi
lea ekey(%edx),%esi // kf = cx->e_key
movsl // copy first round key (unmodified)
movsl
movsl
movsl
sub $32,%edi
movl $1,cnt(%ebp)
aes_38: // do mix column on each column of
lodsl // each round key
mov %eax,%ebx
mix_col(aes_im_tab)
stosl
lodsl
mov %eax,%ebx
mix_col(aes_im_tab)
stosl
lodsl
mov %eax,%ebx
mix_col(aes_im_tab)
stosl
lodsl
mov %eax,%ebx
mix_col(aes_im_tab)
stosl
sub $32,%edi
incl cnt(%ebp)
mov cnt(%ebp),%eax
cmp nrnd(%edx),%eax
jb aes_38
movsl // copy last round key (unmodified)
movsl
movsl
movsl
aes_39: pop %edi
pop %esi
pop %ebx
mov %ebp,%esp
pop %ebp
popfl
ret
// finite field multiplies by {02}, {04} and {08}
#define f2(x) ((x<<1)^(((x>>7)&1)*0x11b))
#define f4(x) ((x<<2)^(((x>>6)&1)*0x11b)^(((x>>6)&2)*0x11b))
#define f8(x) ((x<<3)^(((x>>5)&1)*0x11b)^(((x>>5)&2)*0x11b)^(((x>>5)&4)*0x11b))
// finite field multiplies required in table generation
#define f3(x) (f2(x) ^ x)
#define f9(x) (f8(x) ^ x)
#define fb(x) (f8(x) ^ f2(x) ^ x)
#define fd(x) (f8(x) ^ f4(x) ^ x)
#define fe(x) (f8(x) ^ f4(x) ^ f2(x))
// These defines generate the forward table entries
#define u0(x) ((f3(x) << 24) | (x << 16) | (x << 8) | f2(x))
#define u1(x) ((x << 24) | (x << 16) | (f2(x) << 8) | f3(x))
#define u2(x) ((x << 24) | (f2(x) << 16) | (f3(x) << 8) | x)
#define u3(x) ((f2(x) << 24) | (f3(x) << 16) | (x << 8) | x)
// These defines generate the inverse table entries
#define v0(x) ((fb(x) << 24) | (fd(x) << 16) | (f9(x) << 8) | fe(x))
#define v1(x) ((fd(x) << 24) | (f9(x) << 16) | (fe(x) << 8) | fb(x))
#define v2(x) ((f9(x) << 24) | (fe(x) << 16) | (fb(x) << 8) | fd(x))
#define v3(x) ((fe(x) << 24) | (fb(x) << 16) | (fd(x) << 8) | f9(x))
// These defines generate entries for the last round tables
#define w0(x) (x)
#define w1(x) (x << 8)
#define w2(x) (x << 16)
#define w3(x) (x << 24)
// macro to generate inverse mix column tables (needed for the key schedule)
#define im_data0(p1) \
.long p1(0x00),p1(0x01),p1(0x02),p1(0x03),p1(0x04),p1(0x05),p1(0x06),p1(0x07) ;\
.long p1(0x08),p1(0x09),p1(0x0a),p1(0x0b),p1(0x0c),p1(0x0d),p1(0x0e),p1(0x0f) ;\
.long p1(0x10),p1(0x11),p1(0x12),p1(0x13),p1(0x14),p1(0x15),p1(0x16),p1(0x17) ;\
.long p1(0x18),p1(0x19),p1(0x1a),p1(0x1b),p1(0x1c),p1(0x1d),p1(0x1e),p1(0x1f)
#define im_data1(p1) \
.long p1(0x20),p1(0x21),p1(0x22),p1(0x23),p1(0x24),p1(0x25),p1(0x26),p1(0x27) ;\
.long p1(0x28),p1(0x29),p1(0x2a),p1(0x2b),p1(0x2c),p1(0x2d),p1(0x2e),p1(0x2f) ;\
.long p1(0x30),p1(0x31),p1(0x32),p1(0x33),p1(0x34),p1(0x35),p1(0x36),p1(0x37) ;\
.long p1(0x38),p1(0x39),p1(0x3a),p1(0x3b),p1(0x3c),p1(0x3d),p1(0x3e),p1(0x3f)
#define im_data2(p1) \
.long p1(0x40),p1(0x41),p1(0x42),p1(0x43),p1(0x44),p1(0x45),p1(0x46),p1(0x47) ;\
.long p1(0x48),p1(0x49),p1(0x4a),p1(0x4b),p1(0x4c),p1(0x4d),p1(0x4e),p1(0x4f) ;\
.long p1(0x50),p1(0x51),p1(0x52),p1(0x53),p1(0x54),p1(0x55),p1(0x56),p1(0x57) ;\
.long p1(0x58),p1(0x59),p1(0x5a),p1(0x5b),p1(0x5c),p1(0x5d),p1(0x5e),p1(0x5f)
#define im_data3(p1) \
.long p1(0x60),p1(0x61),p1(0x62),p1(0x63),p1(0x64),p1(0x65),p1(0x66),p1(0x67) ;\
.long p1(0x68),p1(0x69),p1(0x6a),p1(0x6b),p1(0x6c),p1(0x6d),p1(0x6e),p1(0x6f) ;\
.long p1(0x70),p1(0x71),p1(0x72),p1(0x73),p1(0x74),p1(0x75),p1(0x76),p1(0x77) ;\
.long p1(0x78),p1(0x79),p1(0x7a),p1(0x7b),p1(0x7c),p1(0x7d),p1(0x7e),p1(0x7f)
#define im_data4(p1) \
.long p1(0x80),p1(0x81),p1(0x82),p1(0x83),p1(0x84),p1(0x85),p1(0x86),p1(0x87) ;\
.long p1(0x88),p1(0x89),p1(0x8a),p1(0x8b),p1(0x8c),p1(0x8d),p1(0x8e),p1(0x8f) ;\
.long p1(0x90),p1(0x91),p1(0x92),p1(0x93),p1(0x94),p1(0x95),p1(0x96),p1(0x97) ;\
.long p1(0x98),p1(0x99),p1(0x9a),p1(0x9b),p1(0x9c),p1(0x9d),p1(0x9e),p1(0x9f)
#define im_data5(p1) \
.long p1(0xa0),p1(0xa1),p1(0xa2),p1(0xa3),p1(0xa4),p1(0xa5),p1(0xa6),p1(0xa7) ;\
.long p1(0xa8),p1(0xa9),p1(0xaa),p1(0xab),p1(0xac),p1(0xad),p1(0xae),p1(0xaf) ;\
.long p1(0xb0),p1(0xb1),p1(0xb2),p1(0xb3),p1(0xb4),p1(0xb5),p1(0xb6),p1(0xb7) ;\
.long p1(0xb8),p1(0xb9),p1(0xba),p1(0xbb),p1(0xbc),p1(0xbd),p1(0xbe),p1(0xbf)
#define im_data6(p1) \
.long p1(0xc0),p1(0xc1),p1(0xc2),p1(0xc3),p1(0xc4),p1(0xc5),p1(0xc6),p1(0xc7) ;\
.long p1(0xc8),p1(0xc9),p1(0xca),p1(0xcb),p1(0xcc),p1(0xcd),p1(0xce),p1(0xcf) ;\
.long p1(0xd0),p1(0xd1),p1(0xd2),p1(0xd3),p1(0xd4),p1(0xd5),p1(0xd6),p1(0xd7) ;\
.long p1(0xd8),p1(0xd9),p1(0xda),p1(0xdb),p1(0xdc),p1(0xdd),p1(0xde),p1(0xdf)
#define im_data7(p1) \
.long p1(0xe0),p1(0xe1),p1(0xe2),p1(0xe3),p1(0xe4),p1(0xe5),p1(0xe6),p1(0xe7) ;\
.long p1(0xe8),p1(0xe9),p1(0xea),p1(0xeb),p1(0xec),p1(0xed),p1(0xee),p1(0xef) ;\
.long p1(0xf0),p1(0xf1),p1(0xf2),p1(0xf3),p1(0xf4),p1(0xf5),p1(0xf6),p1(0xf7) ;\
.long p1(0xf8),p1(0xf9),p1(0xfa),p1(0xfb),p1(0xfc),p1(0xfd),p1(0xfe),p1(0xff)
// S-box data - 256 entries
#define sb_data0(p1) \
.long p1(0x63),p1(0x7c),p1(0x77),p1(0x7b),p1(0xf2),p1(0x6b),p1(0x6f),p1(0xc5) ;\
.long p1(0x30),p1(0x01),p1(0x67),p1(0x2b),p1(0xfe),p1(0xd7),p1(0xab),p1(0x76) ;\
.long p1(0xca),p1(0x82),p1(0xc9),p1(0x7d),p1(0xfa),p1(0x59),p1(0x47),p1(0xf0) ;\
.long p1(0xad),p1(0xd4),p1(0xa2),p1(0xaf),p1(0x9c),p1(0xa4),p1(0x72),p1(0xc0)
#define sb_data1(p1) \
.long p1(0xb7),p1(0xfd),p1(0x93),p1(0x26),p1(0x36),p1(0x3f),p1(0xf7),p1(0xcc) ;\
.long p1(0x34),p1(0xa5),p1(0xe5),p1(0xf1),p1(0x71),p1(0xd8),p1(0x31),p1(0x15) ;\
.long p1(0x04),p1(0xc7),p1(0x23),p1(0xc3),p1(0x18),p1(0x96),p1(0x05),p1(0x9a) ;\
.long p1(0x07),p1(0x12),p1(0x80),p1(0xe2),p1(0xeb),p1(0x27),p1(0xb2),p1(0x75)
#define sb_data2(p1) \
.long p1(0x09),p1(0x83),p1(0x2c),p1(0x1a),p1(0x1b),p1(0x6e),p1(0x5a),p1(0xa0) ;\
.long p1(0x52),p1(0x3b),p1(0xd6),p1(0xb3),p1(0x29),p1(0xe3),p1(0x2f),p1(0x84) ;\
.long p1(0x53),p1(0xd1),p1(0x00),p1(0xed),p1(0x20),p1(0xfc),p1(0xb1),p1(0x5b) ;\
.long p1(0x6a),p1(0xcb),p1(0xbe),p1(0x39),p1(0x4a),p1(0x4c),p1(0x58),p1(0xcf)
#define sb_data3(p1) \
.long p1(0xd0),p1(0xef),p1(0xaa),p1(0xfb),p1(0x43),p1(0x4d),p1(0x33),p1(0x85) ;\
.long p1(0x45),p1(0xf9),p1(0x02),p1(0x7f),p1(0x50),p1(0x3c),p1(0x9f),p1(0xa8) ;\
.long p1(0x51),p1(0xa3),p1(0x40),p1(0x8f),p1(0x92),p1(0x9d),p1(0x38),p1(0xf5) ;\
.long p1(0xbc),p1(0xb6),p1(0xda),p1(0x21),p1(0x10),p1(0xff),p1(0xf3),p1(0xd2)
#define sb_data4(p1) \
.long p1(0xcd),p1(0x0c),p1(0x13),p1(0xec),p1(0x5f),p1(0x97),p1(0x44),p1(0x17) ;\
.long p1(0xc4),p1(0xa7),p1(0x7e),p1(0x3d),p1(0x64),p1(0x5d),p1(0x19),p1(0x73) ;\
.long p1(0x60),p1(0x81),p1(0x4f),p1(0xdc),p1(0x22),p1(0x2a),p1(0x90),p1(0x88) ;\
.long p1(0x46),p1(0xee),p1(0xb8),p1(0x14),p1(0xde),p1(0x5e),p1(0x0b),p1(0xdb)
#define sb_data5(p1) \
.long p1(0xe0),p1(0x32),p1(0x3a),p1(0x0a),p1(0x49),p1(0x06),p1(0x24),p1(0x5c) ;\
.long p1(0xc2),p1(0xd3),p1(0xac),p1(0x62),p1(0x91),p1(0x95),p1(0xe4),p1(0x79) ;\
.long p1(0xe7),p1(0xc8),p1(0x37),p1(0x6d),p1(0x8d),p1(0xd5),p1(0x4e),p1(0xa9) ;\
.long p1(0x6c),p1(0x56),p1(0xf4),p1(0xea),p1(0x65),p1(0x7a),p1(0xae),p1(0x08)
#define sb_data6(p1) \
.long p1(0xba),p1(0x78),p1(0x25),p1(0x2e),p1(0x1c),p1(0xa6),p1(0xb4),p1(0xc6) ;\
.long p1(0xe8),p1(0xdd),p1(0x74),p1(0x1f),p1(0x4b),p1(0xbd),p1(0x8b),p1(0x8a) ;\
.long p1(0x70),p1(0x3e),p1(0xb5),p1(0x66),p1(0x48),p1(0x03),p1(0xf6),p1(0x0e) ;\
.long p1(0x61),p1(0x35),p1(0x57),p1(0xb9),p1(0x86),p1(0xc1),p1(0x1d),p1(0x9e)
#define sb_data7(p1) \
.long p1(0xe1),p1(0xf8),p1(0x98),p1(0x11),p1(0x69),p1(0xd9),p1(0x8e),p1(0x94) ;\
.long p1(0x9b),p1(0x1e),p1(0x87),p1(0xe9),p1(0xce),p1(0x55),p1(0x28),p1(0xdf) ;\
.long p1(0x8c),p1(0xa1),p1(0x89),p1(0x0d),p1(0xbf),p1(0xe6),p1(0x42),p1(0x68) ;\
.long p1(0x41),p1(0x99),p1(0x2d),p1(0x0f),p1(0xb0),p1(0x54),p1(0xbb),p1(0x16)
// Inverse S-box data - 256 entries
#define ib_data0(p1) \
.long p1(0x52),p1(0x09),p1(0x6a),p1(0xd5),p1(0x30),p1(0x36),p1(0xa5),p1(0x38) ;\
.long p1(0xbf),p1(0x40),p1(0xa3),p1(0x9e),p1(0x81),p1(0xf3),p1(0xd7),p1(0xfb) ;\
.long p1(0x7c),p1(0xe3),p1(0x39),p1(0x82),p1(0x9b),p1(0x2f),p1(0xff),p1(0x87) ;\
.long p1(0x34),p1(0x8e),p1(0x43),p1(0x44),p1(0xc4),p1(0xde),p1(0xe9),p1(0xcb)
#define ib_data1(p1) \
.long p1(0x54),p1(0x7b),p1(0x94),p1(0x32),p1(0xa6),p1(0xc2),p1(0x23),p1(0x3d) ;\
.long p1(0xee),p1(0x4c),p1(0x95),p1(0x0b),p1(0x42),p1(0xfa),p1(0xc3),p1(0x4e) ;\
.long p1(0x08),p1(0x2e),p1(0xa1),p1(0x66),p1(0x28),p1(0xd9),p1(0x24),p1(0xb2) ;\
.long p1(0x76),p1(0x5b),p1(0xa2),p1(0x49),p1(0x6d),p1(0x8b),p1(0xd1),p1(0x25)
#define ib_data2(p1) \
.long p1(0x72),p1(0xf8),p1(0xf6),p1(0x64),p1(0x86),p1(0x68),p1(0x98),p1(0x16) ;\
.long p1(0xd4),p1(0xa4),p1(0x5c),p1(0xcc),p1(0x5d),p1(0x65),p1(0xb6),p1(0x92) ;\
.long p1(0x6c),p1(0x70),p1(0x48),p1(0x50),p1(0xfd),p1(0xed),p1(0xb9),p1(0xda) ;\
.long p1(0x5e),p1(0x15),p1(0x46),p1(0x57),p1(0xa7),p1(0x8d),p1(0x9d),p1(0x84)
#define ib_data3(p1) \
.long p1(0x90),p1(0xd8),p1(0xab),p1(0x00),p1(0x8c),p1(0xbc),p1(0xd3),p1(0x0a) ;\
.long p1(0xf7),p1(0xe4),p1(0x58),p1(0x05),p1(0xb8),p1(0xb3),p1(0x45),p1(0x06) ;\
.long p1(0xd0),p1(0x2c),p1(0x1e),p1(0x8f),p1(0xca),p1(0x3f),p1(0x0f),p1(0x02) ;\
.long p1(0xc1),p1(0xaf),p1(0xbd),p1(0x03),p1(0x01),p1(0x13),p1(0x8a),p1(0x6b)
#define ib_data4(p1) \
.long p1(0x3a),p1(0x91),p1(0x11),p1(0x41),p1(0x4f),p1(0x67),p1(0xdc),p1(0xea) ;\
.long p1(0x97),p1(0xf2),p1(0xcf),p1(0xce),p1(0xf0),p1(0xb4),p1(0xe6),p1(0x73) ;\
.long p1(0x96),p1(0xac),p1(0x74),p1(0x22),p1(0xe7),p1(0xad),p1(0x35),p1(0x85) ;\
.long p1(0xe2),p1(0xf9),p1(0x37),p1(0xe8),p1(0x1c),p1(0x75),p1(0xdf),p1(0x6e)
#define ib_data5(p1) \
.long p1(0x47),p1(0xf1),p1(0x1a),p1(0x71),p1(0x1d),p1(0x29),p1(0xc5),p1(0x89) ;\
.long p1(0x6f),p1(0xb7),p1(0x62),p1(0x0e),p1(0xaa),p1(0x18),p1(0xbe),p1(0x1b) ;\
.long p1(0xfc),p1(0x56),p1(0x3e),p1(0x4b),p1(0xc6),p1(0xd2),p1(0x79),p1(0x20) ;\
.long p1(0x9a),p1(0xdb),p1(0xc0),p1(0xfe),p1(0x78),p1(0xcd),p1(0x5a),p1(0xf4)
#define ib_data6(p1) \
.long p1(0x1f),p1(0xdd),p1(0xa8),p1(0x33),p1(0x88),p1(0x07),p1(0xc7),p1(0x31) ;\
.long p1(0xb1),p1(0x12),p1(0x10),p1(0x59),p1(0x27),p1(0x80),p1(0xec),p1(0x5f) ;\
.long p1(0x60),p1(0x51),p1(0x7f),p1(0xa9),p1(0x19),p1(0xb5),p1(0x4a),p1(0x0d) ;\
.long p1(0x2d),p1(0xe5),p1(0x7a),p1(0x9f),p1(0x93),p1(0xc9),p1(0x9c),p1(0xef)
#define ib_data7(p1) \
.long p1(0xa0),p1(0xe0),p1(0x3b),p1(0x4d),p1(0xae),p1(0x2a),p1(0xf5),p1(0xb0) ;\
.long p1(0xc8),p1(0xeb),p1(0xbb),p1(0x3c),p1(0x83),p1(0x53),p1(0x99),p1(0x61) ;\
.long p1(0x17),p1(0x2b),p1(0x04),p1(0x7e),p1(0xba),p1(0x77),p1(0xd6),p1(0x26) ;\
.long p1(0xe1),p1(0x69),p1(0x14),p1(0x63),p1(0x55),p1(0x21),p1(0x0c),p1(0x7d)
// The rcon_table (needed for the key schedule)
//
// Here is original Dr Brian Gladman's source code:
// _rcon_tab:
// %assign x 1
// %rep 29
// dd x
// %assign x f2(x)
// %endrep
//
// Here is precomputed output (it's more portable this way):
.align ALIGN32BYTES
aes_rcon_tab:
.long 0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80
.long 0x1b,0x36,0x6c,0xd8,0xab,0x4d,0x9a,0x2f
.long 0x5e,0xbc,0x63,0xc6,0x97,0x35,0x6a,0xd4
.long 0xb3,0x7d,0xfa,0xef,0xc5
// The forward xor tables
.align ALIGN32BYTES
aes_ft_tab:
sb_data0(u0)
sb_data1(u0)
sb_data2(u0)
sb_data3(u0)
sb_data4(u0)
sb_data5(u0)
sb_data6(u0)
sb_data7(u0)
sb_data0(u1)
sb_data1(u1)
sb_data2(u1)
sb_data3(u1)
sb_data4(u1)
sb_data5(u1)
sb_data6(u1)
sb_data7(u1)
sb_data0(u2)
sb_data1(u2)
sb_data2(u2)
sb_data3(u2)
sb_data4(u2)
sb_data5(u2)
sb_data6(u2)
sb_data7(u2)
sb_data0(u3)
sb_data1(u3)
sb_data2(u3)
sb_data3(u3)
sb_data4(u3)
sb_data5(u3)
sb_data6(u3)
sb_data7(u3)
.align ALIGN32BYTES
aes_fl_tab:
sb_data0(w0)
sb_data1(w0)
sb_data2(w0)
sb_data3(w0)
sb_data4(w0)
sb_data5(w0)
sb_data6(w0)
sb_data7(w0)
sb_data0(w1)
sb_data1(w1)
sb_data2(w1)
sb_data3(w1)
sb_data4(w1)
sb_data5(w1)
sb_data6(w1)
sb_data7(w1)
sb_data0(w2)
sb_data1(w2)
sb_data2(w2)
sb_data3(w2)
sb_data4(w2)
sb_data5(w2)
sb_data6(w2)
sb_data7(w2)
sb_data0(w3)
sb_data1(w3)
sb_data2(w3)
sb_data3(w3)
sb_data4(w3)
sb_data5(w3)
sb_data6(w3)
sb_data7(w3)
// The inverse xor tables
.align ALIGN32BYTES
aes_it_tab:
ib_data0(v0)
ib_data1(v0)
ib_data2(v0)
ib_data3(v0)
ib_data4(v0)
ib_data5(v0)
ib_data6(v0)
ib_data7(v0)
ib_data0(v1)
ib_data1(v1)
ib_data2(v1)
ib_data3(v1)
ib_data4(v1)
ib_data5(v1)
ib_data6(v1)
ib_data7(v1)
ib_data0(v2)
ib_data1(v2)
ib_data2(v2)
ib_data3(v2)
ib_data4(v2)
ib_data5(v2)
ib_data6(v2)
ib_data7(v2)
ib_data0(v3)
ib_data1(v3)
ib_data2(v3)
ib_data3(v3)
ib_data4(v3)
ib_data5(v3)
ib_data6(v3)
ib_data7(v3)
.align ALIGN32BYTES
aes_il_tab:
ib_data0(w0)
ib_data1(w0)
ib_data2(w0)
ib_data3(w0)
ib_data4(w0)
ib_data5(w0)
ib_data6(w0)
ib_data7(w0)
ib_data0(w1)
ib_data1(w1)
ib_data2(w1)
ib_data3(w1)
ib_data4(w1)
ib_data5(w1)
ib_data6(w1)
ib_data7(w1)
ib_data0(w2)
ib_data1(w2)
ib_data2(w2)
ib_data3(w2)
ib_data4(w2)
ib_data5(w2)
ib_data6(w2)
ib_data7(w2)
ib_data0(w3)
ib_data1(w3)
ib_data2(w3)
ib_data3(w3)
ib_data4(w3)
ib_data5(w3)
ib_data6(w3)
ib_data7(w3)
// The inverse mix column tables
.align ALIGN32BYTES
aes_im_tab:
im_data0(v0)
im_data1(v0)
im_data2(v0)
im_data3(v0)
im_data4(v0)
im_data5(v0)
im_data6(v0)
im_data7(v0)
im_data0(v1)
im_data1(v1)
im_data2(v1)
im_data3(v1)
im_data4(v1)
im_data5(v1)
im_data6(v1)
im_data7(v1)
im_data0(v2)
im_data1(v2)
im_data2(v2)
im_data3(v2)
im_data4(v2)
im_data5(v2)
im_data6(v2)
im_data7(v2)
im_data0(v3)
im_data1(v3)
im_data2(v3)
im_data3(v3)
im_data4(v3)
im_data5(v3)
im_data6(v3)
im_data7(v3)
arch/i386/crypto/aes-i586-glue.c deleted 100644 → 0
View file @ 6909f28b
/*
*
* Glue Code for optimized 586 assembler version of AES
*
* Copyright (c) 2001, Dr Brian Gladman <brg@gladman.uk.net>, Worcester, UK.
* Copyright (c) 2003, Adam J. Richter <adam@yggdrasil.com> (conversion to
* 2.5 API).
* Copyright (c) 2003, 2004 Fruhwirth Clemens <clemens@endorphin.org>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/crypto.h>
#include <linux/linkage.h>
#define AES_MIN_KEY_SIZE 16
#define AES_MAX_KEY_SIZE 32
#define AES_BLOCK_SIZE 16
#define AES_KS_LENGTH 4 * AES_BLOCK_SIZE
#define AES_RC_LENGTH (9 * AES_BLOCK_SIZE) / 8 - 8
typedef struct
{
u_int32_t aes_Nkey; // the number of words in the key input block
u_int32_t aes_Nrnd; // the number of cipher rounds
u_int32_t aes_e_key[AES_KS_LENGTH]; // the encryption key schedule
u_int32_t aes_d_key[AES_KS_LENGTH]; // the decryption key schedule
u_int32_t aes_Ncol; // the number of columns in the cipher state
} aes_context;
/*
* The Cipher Interface
*/
asmlinkage void aes_set_key(void *, const unsigned char [], const int, const int);
/* Actually:
* extern void aes_encrypt(const aes_context *, unsigned char [], const unsigned char []);
* extern void aes_decrypt(const aes_context *, unsigned char [], const unsigned char []);
*/
asmlinkage void aes_encrypt(void*, unsigned char [], const unsigned char []);
asmlinkage void aes_decrypt(void*, unsigned char [], const unsigned char []);
static int aes_set_key_glue(void *cx, const u8 *key,unsigned int key_length, u32 *flags)
{
if(key_length != 16 && key_length != 24 && key_length != 32)
{
*flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
return -EINVAL;
}
aes_set_key(cx, key,key_length,0);
return 0;
}
#ifdef CONFIG_REGPARM
static void aes_encrypt_glue(void* a, unsigned char b[], const unsigned char c[]) {
aes_encrypt(a,b,c);
}
static void aes_decrypt_glue(void* a, unsigned char b[], const unsigned char c[]) {
aes_decrypt(a,b,c);
}
#else
#define aes_encrypt_glue aes_encrypt
#define aes_decrypt_glue aes_decrypt
#endif /* CONFIG_REGPARM */
static struct crypto_alg aes_alg = {
.cra_name = "aes",
.cra_flags = CRYPTO_ALG_TYPE_CIPHER,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(aes_context),
.cra_module = THIS_MODULE,
.cra_list = LIST_HEAD_INIT(aes_alg.cra_list),
.cra_u = {
.cipher = {
.cia_min_keysize = AES_MIN_KEY_SIZE,
.cia_max_keysize = AES_MAX_KEY_SIZE,
.cia_setkey = aes_set_key_glue,
.cia_encrypt = aes_encrypt_glue,
.cia_decrypt = aes_decrypt_glue
}
}
};
static int __init aes_init(void)
{
return crypto_register_alg(&aes_alg);
}
static void __exit aes_fini(void)
{
crypto_unregister_alg(&aes_alg);
}
module_init(aes_init);
module_exit(aes_fini);
MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm, i586 asm optimized");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Fruhwirth Clemens");
MODULE_ALIAS("aes");
arch/ia64/kernel/salinfo.c
View file @ a2769608
...@@ -426,8 +426,6 @@ salinfo_log_read(struct file *file, char *buffer, size_t count, loff_t *ppos) ...@@ -426,8 +426,6 @@ salinfo_log_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
struct inode *inode = file->f_dentry->d_inode; struct inode *inode = file->f_dentry->d_inode;
struct proc_dir_entry *entry = PDE(inode); struct proc_dir_entry *entry = PDE(inode);
struct salinfo_data *data = entry->data; struct salinfo_data *data = entry->data;
void *saldata;
size_t size;
u8 *buf; u8 *buf;
u64 bufsize; u64 bufsize;
...@@ -441,18 +439,7 @@ salinfo_log_read(struct file *file, char *buffer, size_t count, loff_t *ppos) ...@@ -441,18 +439,7 @@ salinfo_log_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
buf = NULL; buf = NULL;
bufsize = 0; bufsize = 0;
} }
if (*ppos >= bufsize) return simple_read_from_buffer(buffer, count, ppos, buf, bufsize);
return 0;
saldata = buf + file->f_pos;
size = bufsize - file->f_pos;
if (size > count)
size = count;
if (copy_to_user(buffer, saldata, size))
return -EFAULT;
*ppos += size;
return size;
} }
static void static void
......
arch/ppc64/kernel/proc_ppc64.c
View file @ a2769608
...@@ -161,21 +161,10 @@ static loff_t page_map_seek( struct file *file, loff_t off, int whence) ...@@ -161,21 +161,10 @@ static loff_t page_map_seek( struct file *file, loff_t off, int whence)
return (file->f_pos = new); return (file->f_pos = new);
} }
static ssize_t page_map_read( struct file *file, char *buf, size_t nbytes, loff_t *ppos) static ssize_t page_map_read( struct file *file, char __user *buf, size_t nbytes, loff_t *ppos)
{ {
unsigned pos = *ppos;
struct proc_dir_entry *dp = PDE(file->f_dentry->d_inode); struct proc_dir_entry *dp = PDE(file->f_dentry->d_inode);
return simple_read_from_buffer(buf, nbytes, ppos, dp->data, dp->size);
if ( pos >= dp->size )
return 0;
if ( nbytes >= dp->size )
nbytes = dp->size;
if ( pos + nbytes > dp->size )
nbytes = dp->size - pos;
copy_to_user( buf, (char *)dp->data + pos, nbytes );
*ppos = pos + nbytes;
return nbytes;
} }
static int page_map_mmap( struct file *file, struct vm_area_struct *vma ) static int page_map_mmap( struct file *file, struct vm_area_struct *vma )
......
crypto/Kconfig
View file @ a2769608
...@@ -118,9 +118,9 @@ config CRYPTO_SERPENT ...@@ -118,9 +118,9 @@ config CRYPTO_SERPENT
See also: See also:
http://www.cl.cam.ac.uk/~rja14/serpent.html http://www.cl.cam.ac.uk/~rja14/serpent.html
config CRYPTO_AES_GENERIC config CRYPTO_AES
tristate "AES cipher algorithms" tristate "AES cipher algorithms"
depends on CRYPTO && !(X86 && !X86_64) depends on CRYPTO
help help
AES cipher algorithms (FIPS-197). AES uses the Rijndael AES cipher algorithms (FIPS-197). AES uses the Rijndael
algorithm. algorithm.
...@@ -138,26 +138,6 @@ config CRYPTO_AES_GENERIC ...@@ -138,26 +138,6 @@ config CRYPTO_AES_GENERIC
See http://csrc.nist.gov/CryptoToolkit/aes/ for more information. See http://csrc.nist.gov/CryptoToolkit/aes/ for more information.
config CRYPTO_AES_586
tristate "AES cipher algorithms (i586)"
depends on CRYPTO && (X86 && !X86_64)
help
AES cipher algorithms (FIPS-197). AES uses the Rijndael
algorithm.
Rijndael appears to be consistently a very good performer in
both hardware and software across a wide range of computing
environments regardless of its use in feedback or non-feedback
modes. Its key setup time is excellent, and its key agility is
good. Rijndael's very low memory requirements make it very well
suited for restricted-space environments, in which it also
demonstrates excellent performance. Rijndael's operations are
among the easiest to defend against power and timing attacks.
The AES specifies three key sizes: 128, 192 and 256 bits
See http://csrc.nist.gov/encryption/aes/ for more information.
config CRYPTO_CAST5 config CRYPTO_CAST5
tristate "CAST5 (CAST-128) cipher algorithm" tristate "CAST5 (CAST-128) cipher algorithm"
depends on CRYPTO depends on CRYPTO
......
drivers/acpi/system.c
View file @ a2769608
...@@ -92,8 +92,7 @@ acpi_system_read_dsdt ( ...@@ -92,8 +92,7 @@ acpi_system_read_dsdt (
{ {
acpi_status status = AE_OK; acpi_status status = AE_OK;
struct acpi_buffer dsdt = {ACPI_ALLOCATE_BUFFER, NULL}; struct acpi_buffer dsdt = {ACPI_ALLOCATE_BUFFER, NULL};
void *data = NULL; ssize_t res;
size_t size = 0;
ACPI_FUNCTION_TRACE("acpi_system_read_dsdt"); ACPI_FUNCTION_TRACE("acpi_system_read_dsdt");
...@@ -101,22 +100,11 @@ acpi_system_read_dsdt ( ...@@ -101,22 +100,11 @@ acpi_system_read_dsdt (
if (ACPI_FAILURE(status)) if (ACPI_FAILURE(status))
return_VALUE(-ENODEV); return_VALUE(-ENODEV);
if (*ppos < dsdt.length) { res = simple_read_from_buffer(buffer, count, ppos,
data = dsdt.pointer + file->f_pos; dsdt.pointer, dsdt.length);
size = dsdt.length - file->f_pos;
if (size > count)
size = count;
if (copy_to_user(buffer, data, size)) {
acpi_os_free(dsdt.pointer);
return_VALUE(-EFAULT);
}
}
acpi_os_free(dsdt.pointer); acpi_os_free(dsdt.pointer);
*ppos += size; return_VALUE(res);
return_VALUE(size);
} }
...@@ -135,8 +123,7 @@ acpi_system_read_fadt ( ...@@ -135,8 +123,7 @@ acpi_system_read_fadt (
{ {
acpi_status status = AE_OK; acpi_status status = AE_OK;
struct acpi_buffer fadt = {ACPI_ALLOCATE_BUFFER, NULL}; struct acpi_buffer fadt = {ACPI_ALLOCATE_BUFFER, NULL};
void *data = NULL; ssize_t res;
size_t size = 0;
ACPI_FUNCTION_TRACE("acpi_system_read_fadt"); ACPI_FUNCTION_TRACE("acpi_system_read_fadt");
...@@ -144,22 +131,11 @@ acpi_system_read_fadt ( ...@@ -144,22 +131,11 @@ acpi_system_read_fadt (
if (ACPI_FAILURE(status)) if (ACPI_FAILURE(status))
return_VALUE(-ENODEV); return_VALUE(-ENODEV);
if (*ppos < fadt.length) { res = simple_read_from_buffer(buffer, count, ppos,
data = fadt.pointer + file->f_pos; fadt.pointer, fadt.length);
size = fadt.length - file->f_pos;
if (size > count)
size = count;
if (copy_to_user(buffer, data, size)) {
acpi_os_free(fadt.pointer);
return_VALUE(-EFAULT);
}
}
acpi_os_free(fadt.pointer); acpi_os_free(fadt.pointer);
*ppos += size; return_VALUE(res);
return_VALUE(size);
} }
......
drivers/md/multipath.c
View file @ a2769608
...@@ -120,7 +120,7 @@ int multipath_end_request(struct bio *bio, unsigned int bytes_done, int error) ...@@ -120,7 +120,7 @@ int multipath_end_request(struct bio *bio, unsigned int bytes_done, int error)
if (uptodate) if (uptodate)
multipath_end_bh_io(mp_bh, uptodate); multipath_end_bh_io(mp_bh, uptodate);
else { else if ((bio->bi_rw & (1 << BIO_RW_AHEAD)) == 0) {
/* /*
* oops, IO error: * oops, IO error:
*/ */
...@@ -130,7 +130,8 @@ int multipath_end_request(struct bio *bio, unsigned int bytes_done, int error) ...@@ -130,7 +130,8 @@ int multipath_end_request(struct bio *bio, unsigned int bytes_done, int error)
bdevname(rdev->bdev,b), bdevname(rdev->bdev,b),
(unsigned long long)bio->bi_sector); (unsigned long long)bio->bi_sector);
multipath_reschedule_retry(mp_bh); multipath_reschedule_retry(mp_bh);
} } else
multipath_end_bh_io(mp_bh, 0);
rdev_dec_pending(rdev, conf->mddev); rdev_dec_pending(rdev, conf->mddev);
return 0; return 0;
} }
...@@ -382,7 +383,11 @@ static void multipathd (mddev_t *mddev) ...@@ -382,7 +383,11 @@ static void multipathd (mddev_t *mddev)
" to another IO path\n", " to another IO path\n",
bdevname(bio->bi_bdev,b), bdevname(bio->bi_bdev,b),
(unsigned long long)bio->bi_sector); (unsigned long long)bio->bi_sector);
*bio = *(mp_bh->master_bio);
bio->bi_bdev = conf->multipaths[mp_bh->path].rdev->bdev; bio->bi_bdev = conf->multipaths[mp_bh->path].rdev->bdev;
bio->bi_rw |= (1 << BIO_RW_FAILFAST);
bio->bi_end_io = multipath_end_request;
bio->bi_private = mp_bh;
generic_make_request(bio); generic_make_request(bio);
} }
} }
......
drivers/oprofile/oprofilefs.c
View file @ a2769608
...@@ -47,23 +47,7 @@ static struct super_operations s_ops = { ...@@ -47,23 +47,7 @@ static struct super_operations s_ops = {
ssize_t oprofilefs_str_to_user(char const * str, char __user * buf, size_t count, loff_t * offset) ssize_t oprofilefs_str_to_user(char const * str, char __user * buf, size_t count, loff_t * offset)
{ {
size_t len = strlen(str); return simple_read_from_buffer(buf, count, offset, str, strlen(str));
if (!count)
return 0;
if (*offset > len)
return 0;
if (count > len - *offset)
count = len - *offset;
if (copy_to_user(buf, str + *offset, count))
return -EFAULT;
*offset += count;
return count;
} }
...@@ -72,29 +56,10 @@ ssize_t oprofilefs_str_to_user(char const * str, char __user * buf, size_t count ...@@ -72,29 +56,10 @@ ssize_t oprofilefs_str_to_user(char const * str, char __user * buf, size_t count
ssize_t oprofilefs_ulong_to_user(unsigned long val, char __user * buf, size_t count, loff_t * offset) ssize_t oprofilefs_ulong_to_user(unsigned long val, char __user * buf, size_t count, loff_t * offset)
{ {
char tmpbuf[TMPBUFSIZE]; char tmpbuf[TMPBUFSIZE];
size_t maxlen; size_t maxlen = snprintf(tmpbuf, TMPBUFSIZE, "%lu\n", val);
if (!count)
return 0;
spin_lock(&oprofilefs_lock);
maxlen = snprintf(tmpbuf, TMPBUFSIZE, "%lu\n", val);
spin_unlock(&oprofilefs_lock);
if (maxlen > TMPBUFSIZE) if (maxlen > TMPBUFSIZE)
maxlen = TMPBUFSIZE; maxlen = TMPBUFSIZE;
return simple_read_from_buffer(buf, count, offset, tmpbuf, maxlen);
if (*offset > maxlen)
return 0;
if (count > maxlen - *offset)
count = maxlen - *offset;
if (copy_to_user(buf, tmpbuf + *offset, count))
return -EFAULT;
*offset += count;
return count;
} }
......
drivers/usb/host/uhci-debug.c
View file @ a2769608
...@@ -571,22 +571,7 @@ static ssize_t uhci_proc_read(struct file *file, char __user *buf, ...@@ -571,22 +571,7 @@ static ssize_t uhci_proc_read(struct file *file, char __user *buf,
size_t nbytes, loff_t *ppos) size_t nbytes, loff_t *ppos)
{ {
struct uhci_proc *up = file->private_data; struct uhci_proc *up = file->private_data;
unsigned int pos; return simple_read_from_buffer(buf, nbytes, ppos, up->data, up->size);
unsigned int size;
pos = *ppos;
size = up->size;
if (pos >= size)
return 0;
if (nbytes > size - pos)
nbytes = size - pos;
if (copy_to_user(buf, up->data + pos, nbytes))
return -EFAULT;
*ppos += nbytes;
return nbytes;
} }
static int uhci_proc_release(struct inode *inode, struct file *file) static int uhci_proc_release(struct inode *inode, struct file *file)
......
fs/libfs.c
View file @ a2769608
...@@ -7,6 +7,7 @@ ...@@ -7,6 +7,7 @@
#include <linux/pagemap.h> #include <linux/pagemap.h>
#include <linux/mount.h> #include <linux/mount.h>
#include <linux/vfs.h> #include <linux/vfs.h>
#include <asm/uaccess.h>
int simple_getattr(struct vfsmount *mnt, struct dentry *dentry, int simple_getattr(struct vfsmount *mnt, struct dentry *dentry,
struct kstat *stat) struct kstat *stat)
...@@ -439,6 +440,22 @@ void simple_release_fs(struct vfsmount **mount, int *count) ...@@ -439,6 +440,22 @@ void simple_release_fs(struct vfsmount **mount, int *count)
mntput(mnt); mntput(mnt);
} }
ssize_t simple_read_from_buffer(void __user *to, size_t count, loff_t *ppos,
void *from, size_t available)
{
loff_t pos = *ppos;
if (pos < 0)
return -EINVAL;
if (pos >= available)
return 0;
if (count > available - pos)
count = available - pos;
if (copy_to_user(to, from + pos, count))
return -EFAULT;
*ppos = pos + count;
return count;
}
EXPORT_SYMBOL(dcache_dir_close); EXPORT_SYMBOL(dcache_dir_close);
EXPORT_SYMBOL(dcache_dir_lseek); EXPORT_SYMBOL(dcache_dir_lseek);
EXPORT_SYMBOL(dcache_dir_open); EXPORT_SYMBOL(dcache_dir_open);
...@@ -461,3 +478,4 @@ EXPORT_SYMBOL(simple_rmdir); ...@@ -461,3 +478,4 @@ EXPORT_SYMBOL(simple_rmdir);
EXPORT_SYMBOL(simple_statfs); EXPORT_SYMBOL(simple_statfs);
EXPORT_SYMBOL(simple_sync_file); EXPORT_SYMBOL(simple_sync_file);
EXPORT_SYMBOL(simple_unlink); EXPORT_SYMBOL(simple_unlink);
EXPORT_SYMBOL(simple_read_from_buffer);
fs/proc/array.c
View file @ a2769608
...@@ -137,6 +137,7 @@ static inline const char * get_task_state(struct task_struct *tsk) ...@@ -137,6 +137,7 @@ static inline const char * get_task_state(struct task_struct *tsk)
TASK_INTERRUPTIBLE | TASK_INTERRUPTIBLE |
TASK_UNINTERRUPTIBLE | TASK_UNINTERRUPTIBLE |
TASK_ZOMBIE | TASK_ZOMBIE |
TASK_DEAD |
TASK_STOPPED); TASK_STOPPED);
const char **p = &task_state_array[0]; const char **p = &task_state_array[0];
......
include/asm-arm/arch-s3c2410/hardware.h
View file @ a2769608
...@@ -26,6 +26,41 @@ extern unsigned long s3c2410_pclk; ...@@ -26,6 +26,41 @@ extern unsigned long s3c2410_pclk;
extern unsigned long s3c2410_hclk; extern unsigned long s3c2410_hclk;
extern unsigned long s3c2410_fclk; extern unsigned long s3c2410_fclk;
/* external functions for GPIO support
*
* These allow various different clients to access the same GPIO
* registers without conflicting. If your driver only owns the entire
* GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
*/
/* s3c2410_gpio_cfgpin
*
* set the configuration of the given pin to the value passed.
*
* eg:
* s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0);
* s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
*/
extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
/* s3c2410_gpio_pullup
*
* configure the pull-up control on the given pin
*
* to = 1 => disable the pull-up
* 0 => enable the pull-up
*
* eg;
*
* s3c2410_gpio_pullup(S3C2410_GPB0, 0);
* s3c2410_gpio_pullup(S3C2410_GPE8, 0);
*/
extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
#include <asm/sizes.h> #include <asm/sizes.h>
......
include/asm-arm/arch-s3c2410/regs-gpio.h
View file @ a2769608
/* linux/include/asm/hardware/s3c2410/ /* linux/include/asm/hardware/s3c2410/
* *
* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/ * http://www.simtec.co.uk/products/SWLINUX/
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
...@@ -13,12 +13,31 @@ ...@@ -13,12 +13,31 @@
* 19-06-2003 BJD Created file * 19-06-2003 BJD Created file
* 23-06-2003 BJD Updated GSTATUS registers * 23-06-2003 BJD Updated GSTATUS registers
* 12-03-2004 BJD Updated include protection * 12-03-2004 BJD Updated include protection
* 20-07-2004 BJD Added GPIO pin numbers, added Port A definitions
*/ */
#ifndef __ASM_ARCH_REGS_GPIO_H #ifndef __ASM_ARCH_REGS_GPIO_H
#define __ASM_ARCH_REGS_GPIO_H "$Id: gpio.h,v 1.5 2003/05/19 12:51:08 ben Exp $" #define __ASM_ARCH_REGS_GPIO_H "$Id: gpio.h,v 1.5 2003/05/19 12:51:08 ben Exp $"
#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
#define S3C2410_GPIO_BANKA (32*0)
#define S3C2410_GPIO_BANKB (32*1)
#define S3C2410_GPIO_BANKC (32*2)
#define S3C2410_GPIO_BANKD (32*3)
#define S3C2410_GPIO_BANKE (32*4)
#define S3C2410_GPIO_BANKF (32*5)
#define S3C2410_GPIO_BANKG (32*6)
#define S3C2410_GPIO_BANKH (32*7)
#define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C2410_VA_GPIO)
#define S3C2410_GPIO_OFFSET(pin) ((pin) & 31)
/* general configuration options */
#define S3C2410_GPIO_LEAVE (0xFFFFFFFF)
/* configure GPIO ports A..G */ /* configure GPIO ports A..G */
#define S3C2410_GPIOREG(x) ((x) + S3C2410_VA_GPIO) #define S3C2410_GPIOREG(x) ((x) + S3C2410_VA_GPIO)
...@@ -29,6 +48,98 @@ ...@@ -29,6 +48,98 @@
#define S3C2410_GPACON S3C2410_GPIOREG(0x00) #define S3C2410_GPACON S3C2410_GPIOREG(0x00)
#define S3C2410_GPADAT S3C2410_GPIOREG(0x04) #define S3C2410_GPADAT S3C2410_GPIOREG(0x04)
#define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
#define S3C2410_GPA0_OUT (0<<0)
#define S3C2410_GPA0_ADDR0 (1<<0)
#define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1)
#define S3C2410_GPA1_OUT (0<<1)
#define S3C2410_GPA1_ADDR16 (1<<1)
#define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2)
#define S3C2410_GPA2_OUT (0<<2)
#define S3C2410_GPA2_ADDR17 (1<<2)
#define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3)
#define S3C2410_GPA3_OUT (0<<3)
#define S3C2410_GPA3_ADDR18 (1<<3)
#define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4)
#define S3C2410_GPA4_OUT (0<<4)
#define S3C2410_GPA4_ADDR19 (1<<4)
#define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5)
#define S3C2410_GPA5_OUT (0<<5)
#define S3C2410_GPA5_ADDR20 (1<<5)
#define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6)
#define S3C2410_GPA6_OUT (0<<6)
#define S3C2410_GPA6_ADDR21 (1<<6)
#define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7)
#define S3C2410_GPA7_OUT (0<<7)
#define S3C2410_GPA7_ADDR22 (1<<7)
#define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8)
#define S3C2410_GPA8_OUT (0<<8)
#define S3C2410_GPA8_ADDR23 (1<<8)
#define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9)
#define S3C2410_GPA9_OUT (0<<9)
#define S3C2410_GPA9_ADDR24 (1<<9)
#define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
#define S3C2410_GPA10_OUT (0<<10)
#define S3C2410_GPA10_ADDR25 (1<<10)
#define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
#define S3C2410_GPA11_OUT (0<<11)
#define S3C2410_GPA11_ADDR26 (1<<11)
#define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
#define S3C2410_GPA12_OUT (0<<12)
#define S3C2410_GPA12_nGCS1 (1<<12)
#define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
#define S3C2410_GPA13_OUT (0<<13)
#define S3C2410_GPA13_nGCS2 (1<<13)
#define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
#define S3C2410_GPA14_OUT (0<<14)
#define S3C2410_GPA14_nGCS3 (1<<14)
#define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
#define S3C2410_GPA15_OUT (0<<15)
#define S3C2410_GPA15_nGCS4 (1<<15)
#define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
#define S3C2410_GPA16_OUT (0<<16)
#define S3C2410_GPA16_nGCS5 (1<<16)
#define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
#define S3C2410_GPA17_OUT (0<<17)
#define S3C2410_GPA17_CLE (1<<17)
#define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
#define S3C2410_GPA18_OUT (0<<18)
#define S3C2410_GPA18_ALE (1<<18)
#define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19)
#define S3C2410_GPA19_OUT (0<<19)
#define S3C2410_GPA19_nFWE (1<<19)
#define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20)
#define S3C2410_GPA20_OUT (0<<20)
#define S3C2410_GPA20_nFRE (1<<20)
#define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21)
#define S3C2410_GPA21_OUT (0<<21)
#define S3C2410_GPA21_nRSTOUT (1<<21)
#define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22)
#define S3C2410_GPA22_OUT (0<<22)
#define S3C2410_GPA22_nFCE (1<<22)
/* 0x08 and 0x0c are reserved */ /* 0x08 and 0x0c are reserved */
/* GPB is 10 IO pins, each configured by 2 bits each in GPBCON. /* GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
...@@ -44,49 +155,60 @@ ...@@ -44,49 +155,60 @@
/* no i/o pin in port b can have value 3! */ /* no i/o pin in port b can have value 3! */
#define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
#define S3C2410_GPB0_INP (0x00 << 0) #define S3C2410_GPB0_INP (0x00 << 0)
#define S3C2410_GPB0_OUTP (0x01 << 0) #define S3C2410_GPB0_OUTP (0x01 << 0)
#define S3C2410_GPB0_TOUT0 (0x02 << 0) #define S3C2410_GPB0_TOUT0 (0x02 << 0)
#define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
#define S3C2410_GPB1_INP (0x00 << 2) #define S3C2410_GPB1_INP (0x00 << 2)
#define S3C2410_GPB1_OUTP (0x01 << 2) #define S3C2410_GPB1_OUTP (0x01 << 2)
#define S3C2410_GPB1_TOUT1 (0x02 << 2) #define S3C2410_GPB1_TOUT1 (0x02 << 2)
#define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
#define S3C2410_GPB2_INP (0x00 << 4) #define S3C2410_GPB2_INP (0x00 << 4)
#define S3C2410_GPB2_OUTP (0x01 << 4) #define S3C2410_GPB2_OUTP (0x01 << 4)
#define S3C2410_GPB2_TOUT2 (0x02 << 4) #define S3C2410_GPB2_TOUT2 (0x02 << 4)
#define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
#define S3C2410_GPB3_INP (0x00 << 6) #define S3C2410_GPB3_INP (0x00 << 6)
#define S3C2410_GPB3_OUTP (0x01 << 6) #define S3C2410_GPB3_OUTP (0x01 << 6)
#define S3C2410_GPB3_TOUT3 (0x02 << 6) #define S3C2410_GPB3_TOUT3 (0x02 << 6)
#define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
#define S3C2410_GPB4_INP (0x00 << 8) #define S3C2410_GPB4_INP (0x00 << 8)
#define S3C2410_GPB4_OUTP (0x01 << 8) #define S3C2410_GPB4_OUTP (0x01 << 8)
#define S3C2410_GPB4_TCLK0 (0x02 << 8) #define S3C2410_GPB4_TCLK0 (0x02 << 8)
#define S3C2410_GPB4_MASK (0x03 << 8) #define S3C2410_GPB4_MASK (0x03 << 8)
#define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
#define S3C2410_GPB5_INP (0x00 << 10) #define S3C2410_GPB5_INP (0x00 << 10)
#define S3C2410_GPB5_OUTP (0x01 << 10) #define S3C2410_GPB5_OUTP (0x01 << 10)
#define S3C2410_GPB5_nXBACK (0x02 << 10) #define S3C2410_GPB5_nXBACK (0x02 << 10)
#define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
#define S3C2410_GPB6_INP (0x00 << 12) #define S3C2410_GPB6_INP (0x00 << 12)
#define S3C2410_GPB6_OUTP (0x01 << 12) #define S3C2410_GPB6_OUTP (0x01 << 12)
#define S3C2410_GPB6_nXBREQ (0x02 << 12) #define S3C2410_GPB6_nXBREQ (0x02 << 12)
#define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
#define S3C2410_GPB7_INP (0x00 << 14) #define S3C2410_GPB7_INP (0x00 << 14)
#define S3C2410_GPB7_OUTP (0x01 << 14) #define S3C2410_GPB7_OUTP (0x01 << 14)
#define S3C2410_GPB7_nXDACK1 (0x02 << 14) #define S3C2410_GPB7_nXDACK1 (0x02 << 14)
#define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
#define S3C2410_GPB8_INP (0x00 << 16) #define S3C2410_GPB8_INP (0x00 << 16)
#define S3C2410_GPB8_OUTP (0x01 << 16) #define S3C2410_GPB8_OUTP (0x01 << 16)
#define S3C2410_GPB8_nXDREQ1 (0x02 << 16) #define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
#define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
#define S3C2410_GPB9_INP (0x00 << 18) #define S3C2410_GPB9_INP (0x00 << 18)
#define S3C2410_GPB9_OUTP (0x01 << 18) #define S3C2410_GPB9_OUTP (0x01 << 18)
#define S3C2410_GPB9_nXDACK0 (0x02 << 18) #define S3C2410_GPB9_nXDACK0 (0x02 << 18)
#define S3C2410_GPB10_INP (0x00 << 18) #define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
#define S3C2410_GPB10_OUTP (0x01 << 18) #define S3C2410_GPB10_INP (0x00 << 18)
#define S3C2410_GPB10_OUTP (0x01 << 18)
#define S3C2410_GPB10_nXDRE0 (0x02 << 18) #define S3C2410_GPB10_nXDRE0 (0x02 << 18)
/* Port C consits of 16 GPIO/Special function /* Port C consits of 16 GPIO/Special function
...@@ -99,66 +221,82 @@ ...@@ -99,66 +221,82 @@
#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) #define S3C2410_GPCDAT S3C2410_GPIOREG(0x24)
#define S3C2410_GPCUP S3C2410_GPIOREG(0x28) #define S3C2410_GPCUP S3C2410_GPIOREG(0x28)
#define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
#define S3C2410_GPC0_INP (0x00 << 0) #define S3C2410_GPC0_INP (0x00 << 0)
#define S3C2410_GPC0_OUTP (0x01 << 0) #define S3C2410_GPC0_OUTP (0x01 << 0)
#define S3C2410_GPC0_LEND (0x02 << 0) #define S3C2410_GPC0_LEND (0x02 << 0)
#define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
#define S3C2410_GPC1_INP (0x00 << 2) #define S3C2410_GPC1_INP (0x00 << 2)
#define S3C2410_GPC1_OUTP (0x01 << 2) #define S3C2410_GPC1_OUTP (0x01 << 2)
#define S3C2410_GPC1_VCLK (0x02 << 2) #define S3C2410_GPC1_VCLK (0x02 << 2)
#define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
#define S3C2410_GPC2_INP (0x00 << 4) #define S3C2410_GPC2_INP (0x00 << 4)
#define S3C2410_GPC2_OUTP (0x01 << 4) #define S3C2410_GPC2_OUTP (0x01 << 4)
#define S3C2410_GPC2_VLINE (0x02 << 4) #define S3C2410_GPC2_VLINE (0x02 << 4)
#define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
#define S3C2410_GPC3_INP (0x00 << 6) #define S3C2410_GPC3_INP (0x00 << 6)
#define S3C2410_GPC3_OUTP (0x01 << 6) #define S3C2410_GPC3_OUTP (0x01 << 6)
#define S3C2410_GPC3_VFRAME (0x02 << 6) #define S3C2410_GPC3_VFRAME (0x02 << 6)
#define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
#define S3C2410_GPC4_INP (0x00 << 8) #define S3C2410_GPC4_INP (0x00 << 8)
#define S3C2410_GPC4_OUTP (0x01 << 8) #define S3C2410_GPC4_OUTP (0x01 << 8)
#define S3C2410_GPC4_VM (0x02 << 8) #define S3C2410_GPC4_VM (0x02 << 8)
#define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
#define S3C2410_GPC5_INP (0x00 << 10) #define S3C2410_GPC5_INP (0x00 << 10)
#define S3C2410_GPC5_OUTP (0x01 << 10) #define S3C2410_GPC5_OUTP (0x01 << 10)
#define S3C2410_GPC5_LCDVF0 (0x02 << 10) #define S3C2410_GPC5_LCDVF0 (0x02 << 10)
#define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
#define S3C2410_GPC6_INP (0x00 << 12) #define S3C2410_GPC6_INP (0x00 << 12)
#define S3C2410_GPC6_OUTP (0x01 << 12) #define S3C2410_GPC6_OUTP (0x01 << 12)
#define S3C2410_GPC6_LCDVF1 (0x02 << 12) #define S3C2410_GPC6_LCDVF1 (0x02 << 12)
#define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
#define S3C2410_GPC7_INP (0x00 << 14) #define S3C2410_GPC7_INP (0x00 << 14)
#define S3C2410_GPC7_OUTP (0x01 << 14) #define S3C2410_GPC7_OUTP (0x01 << 14)
#define S3C2410_GPC7_LCDVF2 (0x02 << 14) #define S3C2410_GPC7_LCDVF2 (0x02 << 14)
#define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
#define S3C2410_GPC8_INP (0x00 << 16) #define S3C2410_GPC8_INP (0x00 << 16)
#define S3C2410_GPC8_OUTP (0x01 << 16) #define S3C2410_GPC8_OUTP (0x01 << 16)
#define S3C2410_GPC8_VD0 (0x02 << 16) #define S3C2410_GPC8_VD0 (0x02 << 16)
#define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
#define S3C2410_GPC9_INP (0x00 << 18) #define S3C2410_GPC9_INP (0x00 << 18)
#define S3C2410_GPC9_OUTP (0x01 << 18) #define S3C2410_GPC9_OUTP (0x01 << 18)
#define S3C2410_GPC9_VD1 (0x02 << 18) #define S3C2410_GPC9_VD1 (0x02 << 18)
#define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
#define S3C2410_GPC10_INP (0x00 << 20) #define S3C2410_GPC10_INP (0x00 << 20)
#define S3C2410_GPC10_OUTP (0x01 << 20) #define S3C2410_GPC10_OUTP (0x01 << 20)
#define S3C2410_GPC10_VD2 (0x02 << 20) #define S3C2410_GPC10_VD2 (0x02 << 20)
#define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
#define S3C2410_GPC11_INP (0x00 << 22) #define S3C2410_GPC11_INP (0x00 << 22)
#define S3C2410_GPC11_OUTP (0x01 << 22) #define S3C2410_GPC11_OUTP (0x01 << 22)
#define S3C2410_GPC11_VD3 (0x02 << 22) #define S3C2410_GPC11_VD3 (0x02 << 22)
#define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
#define S3C2410_GPC12_INP (0x00 << 24) #define S3C2410_GPC12_INP (0x00 << 24)
#define S3C2410_GPC12_OUTP (0x01 << 24) #define S3C2410_GPC12_OUTP (0x01 << 24)
#define S3C2410_GPC12_VD4 (0x02 << 24) #define S3C2410_GPC12_VD4 (0x02 << 24)
#define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
#define S3C2410_GPC13_INP (0x00 << 26) #define S3C2410_GPC13_INP (0x00 << 26)
#define S3C2410_GPC13_OUTP (0x01 << 26) #define S3C2410_GPC13_OUTP (0x01 << 26)
#define S3C2410_GPC13_VD5 (0x02 << 26) #define S3C2410_GPC13_VD5 (0x02 << 26)
#define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
#define S3C2410_GPC14_INP (0x00 << 28) #define S3C2410_GPC14_INP (0x00 << 28)
#define S3C2410_GPC14_OUTP (0x01 << 28) #define S3C2410_GPC14_OUTP (0x01 << 28)
#define S3C2410_GPC14_VD6 (0x02 << 28) #define S3C2410_GPC14_VD6 (0x02 << 28)
#define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
#define S3C2410_GPC15_INP (0x00 << 30) #define S3C2410_GPC15_INP (0x00 << 30)
#define S3C2410_GPC15_OUTP (0x01 << 30) #define S3C2410_GPC15_OUTP (0x01 << 30)
#define S3C2410_GPC15_VD7 (0x02 << 30) #define S3C2410_GPC15_VD7 (0x02 << 30)
...@@ -173,66 +311,82 @@ ...@@ -173,66 +311,82 @@
#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) #define S3C2410_GPDDAT S3C2410_GPIOREG(0x34)
#define S3C2410_GPDUP S3C2410_GPIOREG(0x38) #define S3C2410_GPDUP S3C2410_GPIOREG(0x38)
#define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
#define S3C2410_GPD0_INP (0x00 << 0) #define S3C2410_GPD0_INP (0x00 << 0)
#define S3C2410_GPD0_OUTP (0x01 << 0) #define S3C2410_GPD0_OUTP (0x01 << 0)
#define S3C2410_GPD0_VD8 (0x02 << 0) #define S3C2410_GPD0_VD8 (0x02 << 0)
#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
#define S3C2410_GPD1_INP (0x00 << 2) #define S3C2410_GPD1_INP (0x00 << 2)
#define S3C2410_GPD1_OUTP (0x01 << 2) #define S3C2410_GPD1_OUTP (0x01 << 2)
#define S3C2410_GPD1_VD9 (0x02 << 2) #define S3C2410_GPD1_VD9 (0x02 << 2)
#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
#define S3C2410_GPD2_INP (0x00 << 4) #define S3C2410_GPD2_INP (0x00 << 4)
#define S3C2410_GPD2_OUTP (0x01 << 4) #define S3C2410_GPD2_OUTP (0x01 << 4)
#define S3C2410_GPD2_VD10 (0x02 << 4) #define S3C2410_GPD2_VD10 (0x02 << 4)
#define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
#define S3C2410_GPD3_INP (0x00 << 6) #define S3C2410_GPD3_INP (0x00 << 6)
#define S3C2410_GPD3_OUTP (0x01 << 6) #define S3C2410_GPD3_OUTP (0x01 << 6)
#define S3C2410_GPD3_VD11 (0x02 << 6) #define S3C2410_GPD3_VD11 (0x02 << 6)
#define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
#define S3C2410_GPD4_INP (0x00 << 8) #define S3C2410_GPD4_INP (0x00 << 8)
#define S3C2410_GPD4_OUTP (0x01 << 8) #define S3C2410_GPD4_OUTP (0x01 << 8)
#define S3C2410_GPD4_VD12 (0x02 << 8) #define S3C2410_GPD4_VD12 (0x02 << 8)
#define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
#define S3C2410_GPD5_INP (0x00 << 10) #define S3C2410_GPD5_INP (0x00 << 10)
#define S3C2410_GPD5_OUTP (0x01 << 10) #define S3C2410_GPD5_OUTP (0x01 << 10)
#define S3C2410_GPD5_VD13 (0x02 << 10) #define S3C2410_GPD5_VD13 (0x02 << 10)
#define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
#define S3C2410_GPD6_INP (0x00 << 12) #define S3C2410_GPD6_INP (0x00 << 12)
#define S3C2410_GPD6_OUTP (0x01 << 12) #define S3C2410_GPD6_OUTP (0x01 << 12)
#define S3C2410_GPD6_VD14 (0x02 << 12) #define S3C2410_GPD6_VD14 (0x02 << 12)
#define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
#define S3C2410_GPD7_INP (0x00 << 14) #define S3C2410_GPD7_INP (0x00 << 14)
#define S3C2410_GPD7_OUTP (0x01 << 14) #define S3C2410_GPD7_OUTP (0x01 << 14)
#define S3C2410_GPD7_VD15 (0x02 << 14) #define S3C2410_GPD7_VD15 (0x02 << 14)
#define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
#define S3C2410_GPD8_INP (0x00 << 16) #define S3C2410_GPD8_INP (0x00 << 16)
#define S3C2410_GPD8_OUTP (0x01 << 16) #define S3C2410_GPD8_OUTP (0x01 << 16)
#define S3C2410_GPD8_VD16 (0x02 << 16) #define S3C2410_GPD8_VD16 (0x02 << 16)
#define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
#define S3C2410_GPD9_INP (0x00 << 18) #define S3C2410_GPD9_INP (0x00 << 18)
#define S3C2410_GPD9_OUTP (0x01 << 18) #define S3C2410_GPD9_OUTP (0x01 << 18)
#define S3C2410_GPD9_VD17 (0x02 << 18) #define S3C2410_GPD9_VD17 (0x02 << 18)
#define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
#define S3C2410_GPD10_INP (0x00 << 20) #define S3C2410_GPD10_INP (0x00 << 20)
#define S3C2410_GPD10_OUTP (0x01 << 20) #define S3C2410_GPD10_OUTP (0x01 << 20)
#define S3C2410_GPD10_VD18 (0x02 << 20) #define S3C2410_GPD10_VD18 (0x02 << 20)
#define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
#define S3C2410_GPD11_INP (0x00 << 22) #define S3C2410_GPD11_INP (0x00 << 22)
#define S3C2410_GPD11_OUTP (0x01 << 22) #define S3C2410_GPD11_OUTP (0x01 << 22)
#define S3C2410_GPD11_VD19 (0x02 << 22) #define S3C2410_GPD11_VD19 (0x02 << 22)
#define S3C2410_GPD12 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12)
#define S3C2410_GPD12_INP (0x00 << 24) #define S3C2410_GPD12_INP (0x00 << 24)
#define S3C2410_GPD12_OUTP (0x01 << 24) #define S3C2410_GPD12_OUTP (0x01 << 24)
#define S3C2410_GPD12_VD20 (0x02 << 24) #define S3C2410_GPD12_VD20 (0x02 << 24)
#define S3C2410_GPD13 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13)
#define S3C2410_GPD13_INP (0x00 << 26) #define S3C2410_GPD13_INP (0x00 << 26)
#define S3C2410_GPD13_OUTP (0x01 << 26) #define S3C2410_GPD13_OUTP (0x01 << 26)
#define S3C2410_GPD13_VD21 (0x02 << 26) #define S3C2410_GPD13_VD21 (0x02 << 26)
#define S3C2410_GPD14 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14)
#define S3C2410_GPD14_INP (0x00 << 28) #define S3C2410_GPD14_INP (0x00 << 28)
#define S3C2410_GPD14_OUTP (0x01 << 28) #define S3C2410_GPD14_OUTP (0x01 << 28)
#define S3C2410_GPD14_VD22 (0x02 << 28) #define S3C2410_GPD14_VD22 (0x02 << 28)
#define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
#define S3C2410_GPD15_INP (0x00 << 30) #define S3C2410_GPD15_INP (0x00 << 30)
#define S3C2410_GPD15_OUTP (0x01 << 30) #define S3C2410_GPD15_OUTP (0x01 << 30)
#define S3C2410_GPD15_VD23 (0x02 << 30) #define S3C2410_GPD15_VD23 (0x02 << 30)
...@@ -247,71 +401,87 @@ ...@@ -247,71 +401,87 @@
#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) #define S3C2410_GPEDAT S3C2410_GPIOREG(0x44)
#define S3C2410_GPEUP S3C2410_GPIOREG(0x48) #define S3C2410_GPEUP S3C2410_GPIOREG(0x48)
#define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
#define S3C2410_GPE0_INP (0x00 << 0) #define S3C2410_GPE0_INP (0x00 << 0)
#define S3C2410_GPE0_OUTP (0x01 << 0) #define S3C2410_GPE0_OUTP (0x01 << 0)
#define S3C2410_GPE0_I2SLRCK (0x02 << 0) #define S3C2410_GPE0_I2SLRCK (0x02 << 0)
#define S3C2410_GPE0_MASK (0x03 << 0) #define S3C2410_GPE0_MASK (0x03 << 0)
#define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
#define S3C2410_GPE1_INP (0x00 << 2) #define S3C2410_GPE1_INP (0x00 << 2)
#define S3C2410_GPE1_OUTP (0x01 << 2) #define S3C2410_GPE1_OUTP (0x01 << 2)
#define S3C2410_GPE1_I2SSCLK (0x02 << 2) #define S3C2410_GPE1_I2SSCLK (0x02 << 2)
#define S3C2410_GPE1_MASK (0x03 << 2) #define S3C2410_GPE1_MASK (0x03 << 2)
#define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
#define S3C2410_GPE2_INP (0x00 << 4) #define S3C2410_GPE2_INP (0x00 << 4)
#define S3C2410_GPE2_OUTP (0x01 << 4) #define S3C2410_GPE2_OUTP (0x01 << 4)
#define S3C2410_GPE2_CDCLK (0x02 << 4) #define S3C2410_GPE2_CDCLK (0x02 << 4)
#define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
#define S3C2410_GPE3_INP (0x00 << 6) #define S3C2410_GPE3_INP (0x00 << 6)
#define S3C2410_GPE3_OUTP (0x01 << 6) #define S3C2410_GPE3_OUTP (0x01 << 6)
#define S3C2410_GPE3_I2SSDI (0x02 << 6) #define S3C2410_GPE3_I2SSDI (0x02 << 6)
#define S3C2410_GPE3_MASK (0x03 << 6) #define S3C2410_GPE3_MASK (0x03 << 6)
#define S3C2410_GPE4 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)
#define S3C2410_GPE4_INP (0x00 << 8) #define S3C2410_GPE4_INP (0x00 << 8)
#define S3C2410_GPE4_OUTP (0x01 << 8) #define S3C2410_GPE4_OUTP (0x01 << 8)
#define S3C2410_GPE4_I2SSDO (0x02 << 8) #define S3C2410_GPE4_I2SSDO (0x02 << 8)
#define S3C2410_GPE4_MASK (0x03 << 8) #define S3C2410_GPE4_MASK (0x03 << 8)
#define S3C2410_GPE5 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)
#define S3C2410_GPE5_INP (0x00 << 10) #define S3C2410_GPE5_INP (0x00 << 10)
#define S3C2410_GPE5_OUTP (0x01 << 10) #define S3C2410_GPE5_OUTP (0x01 << 10)
#define S3C2410_GPE5_SDCLK (0x02 << 10) #define S3C2410_GPE5_SDCLK (0x02 << 10)
#define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
#define S3C2410_GPE6_INP (0x00 << 12) #define S3C2410_GPE6_INP (0x00 << 12)
#define S3C2410_GPE6_OUTP (0x01 << 12) #define S3C2410_GPE6_OUTP (0x01 << 12)
#define S3C2410_GPE6_SDCLK (0x02 << 12) #define S3C2410_GPE6_SDCLK (0x02 << 12)
#define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
#define S3C2410_GPE7_INP (0x00 << 14) #define S3C2410_GPE7_INP (0x00 << 14)
#define S3C2410_GPE7_OUTP (0x01 << 14) #define S3C2410_GPE7_OUTP (0x01 << 14)
#define S3C2410_GPE7_SDCMD (0x02 << 14) #define S3C2410_GPE7_SDCMD (0x02 << 14)
#define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
#define S3C2410_GPE8_INP (0x00 << 16) #define S3C2410_GPE8_INP (0x00 << 16)
#define S3C2410_GPE8_OUTP (0x01 << 16) #define S3C2410_GPE8_OUTP (0x01 << 16)
#define S3C2410_GPE8_SDDAT1 (0x02 << 16) #define S3C2410_GPE8_SDDAT1 (0x02 << 16)
#define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
#define S3C2410_GPE9_INP (0x00 << 18) #define S3C2410_GPE9_INP (0x00 << 18)
#define S3C2410_GPE9_OUTP (0x01 << 18) #define S3C2410_GPE9_OUTP (0x01 << 18)
#define S3C2410_GPE9_SDDAT2 (0x02 << 18) #define S3C2410_GPE9_SDDAT2 (0x02 << 18)
#define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
#define S3C2410_GPE10_INP (0x00 << 20) #define S3C2410_GPE10_INP (0x00 << 20)
#define S3C2410_GPE10_OUTP (0x01 << 20) #define S3C2410_GPE10_OUTP (0x01 << 20)
#define S3C2410_GPE10_SDDAT3 (0x02 << 20) #define S3C2410_GPE10_SDDAT3 (0x02 << 20)
#define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
#define S3C2410_GPE11_INP (0x00 << 22) #define S3C2410_GPE11_INP (0x00 << 22)
#define S3C2410_GPE11_OUTP (0x01 << 22) #define S3C2410_GPE11_OUTP (0x01 << 22)
#define S3C2410_GPE11_SPIMISO0 (0x02 << 22) #define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
#define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
#define S3C2410_GPE12_INP (0x00 << 24) #define S3C2410_GPE12_INP (0x00 << 24)
#define S3C2410_GPE12_OUTP (0x01 << 24) #define S3C2410_GPE12_OUTP (0x01 << 24)
#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
#define S3C2410_GPE13 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13)
#define S3C2410_GPE13_INP (0x00 << 26) #define S3C2410_GPE13_INP (0x00 << 26)
#define S3C2410_GPE13_OUTP (0x01 << 26) #define S3C2410_GPE13_OUTP (0x01 << 26)
#define S3C2410_GPE13_SPICLK0 (0x02 << 26) #define S3C2410_GPE13_SPICLK0 (0x02 << 26)
#define S3C2410_GPE14 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14)
#define S3C2410_GPE14_INP (0x00 << 28) #define S3C2410_GPE14_INP (0x00 << 28)
#define S3C2410_GPE14_OUTP (0x01 << 28) #define S3C2410_GPE14_OUTP (0x01 << 28)
#define S3C2410_GPE14_IICSCL (0x02 << 28) #define S3C2410_GPE14_IICSCL (0x02 << 28)
#define S3C2410_GPE14_MASK (0x03 << 28) #define S3C2410_GPE14_MASK (0x03 << 28)
#define S3C2410_GPE15 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15)
#define S3C2410_GPE15_INP (0x00 << 30) #define S3C2410_GPE15_INP (0x00 << 30)
#define S3C2410_GPE15_OUTP (0x01 << 30) #define S3C2410_GPE15_OUTP (0x01 << 30)
#define S3C2410_GPE15_IICSDA (0x02 << 30) #define S3C2410_GPE15_IICSDA (0x02 << 30)
...@@ -333,35 +503,42 @@ ...@@ -333,35 +503,42 @@
#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) #define S3C2410_GPFDAT S3C2410_GPIOREG(0x54)
#define S3C2410_GPFUP S3C2410_GPIOREG(0x58) #define S3C2410_GPFUP S3C2410_GPIOREG(0x58)
#define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
#define S3C2410_GPF0_INP (0x00 << 0) #define S3C2410_GPF0_INP (0x00 << 0)
#define S3C2410_GPF0_OUTP (0x01 << 0) #define S3C2410_GPF0_OUTP (0x01 << 0)
#define S3C2410_GPF0_EINT0 (0x02 << 0) #define S3C2410_GPF0_EINT0 (0x02 << 0)
#define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
#define S3C2410_GPF1_INP (0x00 << 2) #define S3C2410_GPF1_INP (0x00 << 2)
#define S3C2410_GPF1_OUTP (0x01 << 2) #define S3C2410_GPF1_OUTP (0x01 << 2)
#define S3C2410_GPF1_EINT1 (0x02 << 2) #define S3C2410_GPF1_EINT1 (0x02 << 2)
#define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
#define S3C2410_GPF2_INP (0x00 << 4) #define S3C2410_GPF2_INP (0x00 << 4)
#define S3C2410_GPF2_OUTP (0x01 << 4) #define S3C2410_GPF2_OUTP (0x01 << 4)
#define S3C2410_GPF2_EINT2 (0x02 << 4) #define S3C2410_GPF2_EINT2 (0x02 << 4)
#define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
#define S3C2410_GPF3_INP (0x00 << 6) #define S3C2410_GPF3_INP (0x00 << 6)
#define S3C2410_GPF3_OUTP (0x01 << 6) #define S3C2410_GPF3_OUTP (0x01 << 6)
#define S3C2410_GPF3_EINT3 (0x02 << 6) #define S3C2410_GPF3_EINT3 (0x02 << 6)
#define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
#define S3C2410_GPF4_INP (0x00 << 8) #define S3C2410_GPF4_INP (0x00 << 8)
#define S3C2410_GPF4_OUTP (0x01 << 8) #define S3C2410_GPF4_OUTP (0x01 << 8)
#define S3C2410_GPF4_EINT4 (0x02 << 8) #define S3C2410_GPF4_EINT4 (0x02 << 8)
#define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
#define S3C2410_GPF5_INP (0x00 << 10) #define S3C2410_GPF5_INP (0x00 << 10)
#define S3C2410_GPF5_OUTP (0x01 << 10) #define S3C2410_GPF5_OUTP (0x01 << 10)
#define S3C2410_GPF5_EINT5 (0x02 << 10) #define S3C2410_GPF5_EINT5 (0x02 << 10)
#define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
#define S3C2410_GPF6_INP (0x00 << 12) #define S3C2410_GPF6_INP (0x00 << 12)
#define S3C2410_GPF6_OUTP (0x01 << 12) #define S3C2410_GPF6_OUTP (0x01 << 12)
#define S3C2410_GPF6_EINT6 (0x02 << 12) #define S3C2410_GPF6_EINT6 (0x02 << 12)
#define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
#define S3C2410_GPF7_INP (0x00 << 14) #define S3C2410_GPF7_INP (0x00 << 14)
#define S3C2410_GPF7_OUTP (0x01 << 14) #define S3C2410_GPF7_OUTP (0x01 << 14)
#define S3C2410_GPF7_EINT7 (0x02 << 14) #define S3C2410_GPF7_EINT7 (0x02 << 14)
...@@ -378,74 +555,90 @@ ...@@ -378,74 +555,90 @@
#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) #define S3C2410_GPGDAT S3C2410_GPIOREG(0x64)
#define S3C2410_GPGUP S3C2410_GPIOREG(0x68) #define S3C2410_GPGUP S3C2410_GPIOREG(0x68)
#define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
#define S3C2410_GPG0_INP (0x00 << 0) #define S3C2410_GPG0_INP (0x00 << 0)
#define S3C2410_GPG0_OUTP (0x01 << 0) #define S3C2410_GPG0_OUTP (0x01 << 0)
#define S3C2410_GPG0_EINT8 (0x02 << 0) #define S3C2410_GPG0_EINT8 (0x02 << 0)
#define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
#define S3C2410_GPG1_INP (0x00 << 2) #define S3C2410_GPG1_INP (0x00 << 2)
#define S3C2410_GPG1_OUTP (0x01 << 2) #define S3C2410_GPG1_OUTP (0x01 << 2)
#define S3C2410_GPG1_EINT9 (0x02 << 2) #define S3C2410_GPG1_EINT9 (0x02 << 2)
#define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
#define S3C2410_GPG2_INP (0x00 << 4) #define S3C2410_GPG2_INP (0x00 << 4)
#define S3C2410_GPG2_OUTP (0x01 << 4) #define S3C2410_GPG2_OUTP (0x01 << 4)
#define S3C2410_GPG2_EINT10 (0x02 << 4) #define S3C2410_GPG2_EINT10 (0x02 << 4)
#define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
#define S3C2410_GPG3_INP (0x00 << 6) #define S3C2410_GPG3_INP (0x00 << 6)
#define S3C2410_GPG3_OUTP (0x01 << 6) #define S3C2410_GPG3_OUTP (0x01 << 6)
#define S3C2410_GPG3_EINT11 (0x02 << 6) #define S3C2410_GPG3_EINT11 (0x02 << 6)
#define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
#define S3C2410_GPG4_INP (0x00 << 8) #define S3C2410_GPG4_INP (0x00 << 8)
#define S3C2410_GPG4_OUTP (0x01 << 8) #define S3C2410_GPG4_OUTP (0x01 << 8)
#define S3C2410_GPG4_EINT12 (0x02 << 8) #define S3C2410_GPG4_EINT12 (0x02 << 8)
#define S3C2410_GPG4_LCDPWREN (0x03 << 8) #define S3C2410_GPG4_LCDPWREN (0x03 << 8)
#define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
#define S3C2410_GPG5_INP (0x00 << 10) #define S3C2410_GPG5_INP (0x00 << 10)
#define S3C2410_GPG5_OUTP (0x01 << 10) #define S3C2410_GPG5_OUTP (0x01 << 10)
#define S3C2410_GPG5_EINT13 (0x02 << 10) #define S3C2410_GPG5_EINT13 (0x02 << 10)
#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) #define S3C2410_GPG5_SPIMISO1 (0x03 << 10)
#define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
#define S3C2410_GPG6_INP (0x00 << 12) #define S3C2410_GPG6_INP (0x00 << 12)
#define S3C2410_GPG6_OUTP (0x01 << 12) #define S3C2410_GPG6_OUTP (0x01 << 12)
#define S3C2410_GPG6_EINT14 (0x02 << 12) #define S3C2410_GPG6_EINT14 (0x02 << 12)
#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
#define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
#define S3C2410_GPG7_INP (0x00 << 14) #define S3C2410_GPG7_INP (0x00 << 14)
#define S3C2410_GPG7_OUTP (0x01 << 14) #define S3C2410_GPG7_OUTP (0x01 << 14)
#define S3C2410_GPG7_EINT15 (0x02 << 14) #define S3C2410_GPG7_EINT15 (0x02 << 14)
#define S3C2410_GPG7_SPICLK1 (0x03 << 14) #define S3C2410_GPG7_SPICLK1 (0x03 << 14)
#define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
#define S3C2410_GPG8_INP (0x00 << 16) #define S3C2410_GPG8_INP (0x00 << 16)
#define S3C2410_GPG8_OUTP (0x01 << 16) #define S3C2410_GPG8_OUTP (0x01 << 16)
#define S3C2410_GPG8_EINT16 (0x02 << 16) #define S3C2410_GPG8_EINT16 (0x02 << 16)
#define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
#define S3C2410_GPG9_INP (0x00 << 18) #define S3C2410_GPG9_INP (0x00 << 18)
#define S3C2410_GPG9_OUTP (0x01 << 18) #define S3C2410_GPG9_OUTP (0x01 << 18)
#define S3C2410_GPG9_EINT17 (0x02 << 18) #define S3C2410_GPG9_EINT17 (0x02 << 18)
#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
#define S3C2410_GPG10_INP (0x00 << 20) #define S3C2410_GPG10_INP (0x00 << 20)
#define S3C2410_GPG10_OUTP (0x01 << 20) #define S3C2410_GPG10_OUTP (0x01 << 20)
#define S3C2410_GPG10_EINT18 (0x02 << 20) #define S3C2410_GPG10_EINT18 (0x02 << 20)
#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
#define S3C2410_GPG11_INP (0x00 << 22) #define S3C2410_GPG11_INP (0x00 << 22)
#define S3C2410_GPG11_OUTP (0x01 << 22) #define S3C2410_GPG11_OUTP (0x01 << 22)
#define S3C2410_GPG11_EINT19 (0x02 << 22) #define S3C2410_GPG11_EINT19 (0x02 << 22)
#define S3C2410_GPG11_TCLK1 (0x03 << 22) #define S3C2410_GPG11_TCLK1 (0x03 << 22)
#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
#define S3C2410_GPG12_INP (0x00 << 24) #define S3C2410_GPG12_INP (0x00 << 24)
#define S3C2410_GPG12_OUTP (0x01 << 24) #define S3C2410_GPG12_OUTP (0x01 << 24)
#define S3C2410_GPG12_EINT18 (0x02 << 24) #define S3C2410_GPG12_EINT18 (0x02 << 24)
#define S3C2410_GPG12_XMON (0x03 << 24) #define S3C2410_GPG12_XMON (0x03 << 24)
#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
#define S3C2410_GPG13_INP (0x00 << 26) #define S3C2410_GPG13_INP (0x00 << 26)
#define S3C2410_GPG13_OUTP (0x01 << 26) #define S3C2410_GPG13_OUTP (0x01 << 26)
#define S3C2410_GPG13_EINT18 (0x02 << 26) #define S3C2410_GPG13_EINT18 (0x02 << 26)
#define S3C2410_GPG13_nXPON (0x03 << 26) #define S3C2410_GPG13_nXPON (0x03 << 26)
#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
#define S3C2410_GPG14_INP (0x00 << 28) #define S3C2410_GPG14_INP (0x00 << 28)
#define S3C2410_GPG14_OUTP (0x01 << 28) #define S3C2410_GPG14_OUTP (0x01 << 28)
#define S3C2410_GPG14_EINT18 (0x02 << 28) #define S3C2410_GPG14_EINT18 (0x02 << 28)
#define S3C2410_GPG14_YMON (0x03 << 28) #define S3C2410_GPG14_YMON (0x03 << 28)
#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
#define S3C2410_GPG15_INP (0x00 << 30) #define S3C2410_GPG15_INP (0x00 << 30)
#define S3C2410_GPG15_OUTP (0x01 << 30) #define S3C2410_GPG15_OUTP (0x01 << 30)
#define S3C2410_GPG15_EINT18 (0x02 << 30) #define S3C2410_GPG15_EINT18 (0x02 << 30)
...@@ -466,51 +659,62 @@ ...@@ -466,51 +659,62 @@
#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) #define S3C2410_GPHDAT S3C2410_GPIOREG(0x74)
#define S3C2410_GPHUP S3C2410_GPIOREG(0x78) #define S3C2410_GPHUP S3C2410_GPIOREG(0x78)
#define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0)
#define S3C2410_GPH0_INP (0x00 << 0) #define S3C2410_GPH0_INP (0x00 << 0)
#define S3C2410_GPH0_OUTP (0x01 << 0) #define S3C2410_GPH0_OUTP (0x01 << 0)
#define S3C2410_GPH0_nCTS0 (0x02 << 0) #define S3C2410_GPH0_nCTS0 (0x02 << 0)
#define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1)
#define S3C2410_GPH1_INP (0x00 << 2) #define S3C2410_GPH1_INP (0x00 << 2)
#define S3C2410_GPH1_OUTP (0x01 << 2) #define S3C2410_GPH1_OUTP (0x01 << 2)
#define S3C2410_GPH1_nRTS0 (0x02 << 2) #define S3C2410_GPH1_nRTS0 (0x02 << 2)
#define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2)
#define S3C2410_GPH2_INP (0x00 << 4) #define S3C2410_GPH2_INP (0x00 << 4)
#define S3C2410_GPH2_OUTP (0x01 << 4) #define S3C2410_GPH2_OUTP (0x01 << 4)
#define S3C2410_GPH2_TXD0 (0x02 << 4) #define S3C2410_GPH2_TXD0 (0x02 << 4)
#define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3)
#define S3C2410_GPH3_INP (0x00 << 6) #define S3C2410_GPH3_INP (0x00 << 6)
#define S3C2410_GPH3_OUTP (0x01 << 6) #define S3C2410_GPH3_OUTP (0x01 << 6)
#define S3C2410_GPH3_RXD0 (0x02 << 6) #define S3C2410_GPH3_RXD0 (0x02 << 6)
#define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4)
#define S3C2410_GPH4_INP (0x00 << 8) #define S3C2410_GPH4_INP (0x00 << 8)
#define S3C2410_GPH4_OUTP (0x01 << 8) #define S3C2410_GPH4_OUTP (0x01 << 8)
#define S3C2410_GPH4_TXD1 (0x02 << 8) #define S3C2410_GPH4_TXD1 (0x02 << 8)
#define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5)
#define S3C2410_GPH5_INP (0x00 << 10) #define S3C2410_GPH5_INP (0x00 << 10)
#define S3C2410_GPH5_OUTP (0x01 << 10) #define S3C2410_GPH5_OUTP (0x01 << 10)
#define S3C2410_GPH5_RXD1 (0x02 << 10) #define S3C2410_GPH5_RXD1 (0x02 << 10)
#define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6)
#define S3C2410_GPH6_INP (0x00 << 12) #define S3C2410_GPH6_INP (0x00 << 12)
#define S3C2410_GPH6_OUTP (0x01 << 12) #define S3C2410_GPH6_OUTP (0x01 << 12)
#define S3C2410_GPH6_TXD2 (0x02 << 12) #define S3C2410_GPH6_TXD2 (0x02 << 12)
#define S3C2410_GPH6_nRTS1 (0x03 << 12) #define S3C2410_GPH6_nRTS1 (0x03 << 12)
#define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7)
#define S3C2410_GPH7_INP (0x00 << 14) #define S3C2410_GPH7_INP (0x00 << 14)
#define S3C2410_GPH7_OUTP (0x01 << 14) #define S3C2410_GPH7_OUTP (0x01 << 14)
#define S3C2410_GPH7_RXD2 (0x02 << 14) #define S3C2410_GPH7_RXD2 (0x02 << 14)
#define S3C2410_GPH7_nCTS1 (0x03 << 14) #define S3C2410_GPH7_nCTS1 (0x03 << 14)
#define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8)
#define S3C2410_GPH8_INP (0x00 << 16) #define S3C2410_GPH8_INP (0x00 << 16)
#define S3C2410_GPH8_OUTP (0x01 << 16) #define S3C2410_GPH8_OUTP (0x01 << 16)
#define S3C2410_GPH8_UCLK (0x02 << 16) #define S3C2410_GPH8_UCLK (0x02 << 16)
#define S3C2410_GPH9_INP (0x00 << 18) #define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9)
#define S3C2410_GPH9_OUTP (0x01 << 18) #define S3C2410_GPH9_INP (0x00 << 18)
#define S3C2410_GPH9_CLKOUT0 (0x02 << 18) #define S3C2410_GPH9_OUTP (0x01 << 18)
#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
#define S3C2410_GPH10_INP (0x00 << 20) #define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
#define S3C2410_GPH10_OUTP (0x01 << 20) #define S3C2410_GPH10_INP (0x00 << 20)
#define S3C2410_GPH10_CLKOUT1 (0x02 << 20) #define S3C2410_GPH10_OUTP (0x01 << 20)
#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
/* miscellaneous control */ /* miscellaneous control */
......
include/linux/fs.h
View file @ a2769608
...@@ -1527,6 +1527,8 @@ extern int simple_fill_super(struct super_block *, int, struct tree_descr *); ...@@ -1527,6 +1527,8 @@ extern int simple_fill_super(struct super_block *, int, struct tree_descr *);
extern int simple_pin_fs(char *name, struct vfsmount **mount, int *count); extern int simple_pin_fs(char *name, struct vfsmount **mount, int *count);
extern void simple_release_fs(struct vfsmount **mount, int *count); extern void simple_release_fs(struct vfsmount **mount, int *count);
extern ssize_t simple_read_from_buffer(void __user *, size_t, loff_t *, void *, size_t);
extern int inode_change_ok(struct inode *, struct iattr *); extern int inode_change_ok(struct inode *, struct iattr *);
extern int __must_check inode_setattr(struct inode *, struct iattr *); extern int __must_check inode_setattr(struct inode *, struct iattr *);
......
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