arm64: dts: realtek: rtd139x: Introduce CRT, iso and misc syscon

Group the non-iso reset controller nodes into a CRT syscon mfd node.
Group reset controller, watchdog and UART0 into an Isolation mfd node.
Group UART1 and UART2 into a Miscellaneous syscon mfd node.
Acked-by: James Tai <james.tai@realtek.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>

arch/arm64/boot/dts/realtek/rtd139x.dtsi

@@ -61,6 +61,48 @@ rbus: bus@98000000 {
 			#size-cells = <1>;
 			ranges = <0x0 0x98000000 0x200000>;
 
+			crt: syscon@0 {
+				compatible = "syscon", "simple-mfd";
+				reg = <0x0 0x1000>;
+				reg-io-width = <4>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0x0 0x1000>;
+			};
+
+			iso: syscon@7000 {
+				compatible = "syscon", "simple-mfd";
+				reg = <0x7000 0x1000>;
+				reg-io-width = <4>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0x7000 0x1000>;
+			};
+
+			misc: syscon@1b000 {
+				compatible = "syscon", "simple-mfd";
+				reg = <0x1b000 0x1000>;
+				reg-io-width = <4>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0x1b000 0x1000>;
+			};
+		};
+
+		gic: interrupt-controller@ff011000 {
+			compatible = "arm,gic-400";
+			reg = <0xff011000 0x1000>,
+			      <0xff012000 0x2000>,
+			      <0xff014000 0x2000>,
+			      <0xff016000 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+	};
+};
+
+&crt {
 	reset1: reset-controller@0 {
 		compatible = "snps,dw-low-reset";
 		reg = <0x0 0x4>;
@@ -84,32 +126,36 @@ reset4: reset-controller@50 {
 		reg = <0x50 0x4>;
 		#reset-cells = <1>;
 	};
+};
 
-			iso_reset: reset-controller@7088 {
+&iso {
+	iso_reset: reset-controller@88 {
 		compatible = "snps,dw-low-reset";
-				reg = <0x7088 0x4>;
+		reg = <0x88 0x4>;
 		#reset-cells = <1>;
 	};
 
-			wdt: watchdog@7680 {
+	wdt: watchdog@680 {
 		compatible = "realtek,rtd1295-watchdog";
-				reg = <0x7680 0x100>;
+		reg = <0x680 0x100>;
 		clocks = <&osc27M>;
 	};
 
-			uart0: serial@7800 {
+	uart0: serial@800 {
 		compatible = "snps,dw-apb-uart";
-				reg = <0x7800 0x400>;
+		reg = <0x800 0x400>;
 		reg-shift = <2>;
 		reg-io-width = <4>;
 		clock-frequency = <27000000>;
 		resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
 		status = "disabled";
 	};
+};
 
-			uart1: serial@1b200 {
+&misc {
+	uart1: serial@200 {
 		compatible = "snps,dw-apb-uart";
-				reg = <0x1b200 0x100>;
+		reg = <0x200 0x100>;
 		reg-shift = <2>;
 		reg-io-width = <4>;
 		clock-frequency = <432000000>;
@@ -117,26 +163,13 @@ uart1: serial@1b200 {
 		status = "disabled";
 	};
 
-			uart2: serial@1b400 {
+	uart2: serial@400 {
 		compatible = "snps,dw-apb-uart";
-				reg = <0x1b400 0x100>;
+		reg = <0x400 0x100>;
 		reg-shift = <2>;
 		reg-io-width = <4>;
 		clock-frequency = <432000000>;
 		resets = <&reset2 RTD1295_RSTN_UR2>;
 		status = "disabled";
 	};
-		};
-
-		gic: interrupt-controller@ff011000 {
-			compatible = "arm,gic-400";
-			reg = <0xff011000 0x1000>,
-			      <0xff012000 0x2000>,
-			      <0xff014000 0x2000>,
-			      <0xff016000 0x2000>;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-			interrupt-controller;
-			#interrupt-cells = <3>;
-		};
-	};
 };