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Commit a7448db4 authored by Haavard Skinnemoen's avatar Haavard Skinnemoen
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avr32: Remove include/asm-avr32/arch-at32ap 

Since all users have been converted over to use <mach/foo.h>, there's no
need for the arch-at32ap directory and associated symlink anymore.
Signed-off-by: default avatarHaavard Skinnemoen <haavard.skinnemoen@atmel.com>
parent a09e64fb
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arch/avr32/Makefile
View file @ a7448db4
...@@ -39,20 +39,6 @@ core-y += arch/avr32/mm/ ...@@ -39,20 +39,6 @@ core-y += arch/avr32/mm/
drivers-$(CONFIG_OPROFILE) += arch/avr32/oprofile/ drivers-$(CONFIG_OPROFILE) += arch/avr32/oprofile/
libs-y += arch/avr32/lib/ libs-y += arch/avr32/lib/
archincdir-$(CONFIG_PLATFORM_AT32AP) := arch-at32ap
include/asm-avr32/.arch: $(wildcard include/config/platform/*.h) include/config/auto.conf
@echo ' SYMLINK include/asm-avr32/arch -> include/asm-avr32/$(archincdir-y)'
ifneq ($(KBUILD_SRC),)
$(Q)mkdir -p include/asm-avr32
$(Q)ln -fsn $(srctree)/include/asm-avr32/$(archincdir-y) include/asm-avr32/arch
else
$(Q)ln -fsn $(archincdir-y) include/asm-avr32/arch
endif
@touch $@
archprepare: include/asm-avr32/.arch
CLEAN_FILES += include/asm-avr32/.arch include/asm-avr32/arch CLEAN_FILES += include/asm-avr32/.arch include/asm-avr32/arch
BOOT_TARGETS := vmlinux.elf vmlinux.bin uImage uImage.srec BOOT_TARGETS := vmlinux.elf vmlinux.bin uImage uImage.srec
......
include/asm-avr32/arch-at32ap/at32ap700x.h deleted 100644 → 0
View file @ a09e64fb
/*
* Pin definitions for AT32AP7000.
*
* Copyright (C) 2006 Atmel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_AT32AP700X_H__
#define __ASM_ARCH_AT32AP700X_H__
#define GPIO_PERIPH_A 0
#define GPIO_PERIPH_B 1
/*
* Pin numbers identifying specific GPIO pins on the chip. They can
* also be converted to IRQ numbers by passing them through
* gpio_to_irq().
*/
#define GPIO_PIOA_BASE (0)
#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
#define GPIO_PIN_PA(N) (GPIO_PIOA_BASE + (N))
#define GPIO_PIN_PB(N) (GPIO_PIOB_BASE + (N))
#define GPIO_PIN_PC(N) (GPIO_PIOC_BASE + (N))
#define GPIO_PIN_PD(N) (GPIO_PIOD_BASE + (N))
#define GPIO_PIN_PE(N) (GPIO_PIOE_BASE + (N))
/*
* DMAC peripheral hardware handshaking interfaces, used with dw_dmac
*/
#define DMAC_MCI_RX 0
#define DMAC_MCI_TX 1
#define DMAC_DAC_TX 2
#define DMAC_AC97_A_RX 3
#define DMAC_AC97_A_TX 4
#define DMAC_AC97_B_RX 5
#define DMAC_AC97_B_TX 6
#define DMAC_DMAREQ_0 7
#define DMAC_DMAREQ_1 8
#define DMAC_DMAREQ_2 9
#define DMAC_DMAREQ_3 10
#endif /* __ASM_ARCH_AT32AP700X_H__ */
include/asm-avr32/arch-at32ap/board.h deleted 100644 → 0
View file @ a09e64fb
/*
* Platform data definitions.
*/
#ifndef __ASM_ARCH_BOARD_H
#define __ASM_ARCH_BOARD_H
#include <linux/types.h>
#define GPIO_PIN_NONE (-1)
/*
* Clock rates for various on-board oscillators. The number of entries
* in this array is chip-dependent.
*/
extern unsigned long at32_board_osc_rates[];
/* Add basic devices: system manager, interrupt controller, portmuxes, etc. */
void at32_add_system_devices(void);
#define ATMEL_MAX_UART 4
extern struct platform_device *atmel_default_console_device;
struct atmel_uart_data {
short use_dma_tx; /* use transmit DMA? */
short use_dma_rx; /* use receive DMA? */
void __iomem *regs; /* virtual base address, if any */
};
void at32_map_usart(unsigned int hw_id, unsigned int line);
struct platform_device *at32_add_device_usart(unsigned int id);
struct eth_platform_data {
u32 phy_mask;
u8 is_rmii;
};
struct platform_device *
at32_add_device_eth(unsigned int id, struct eth_platform_data *data);
struct spi_board_info;
struct platform_device *
at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n);
struct atmel_lcdfb_info;
struct platform_device *
at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
unsigned long fbmem_start, unsigned long fbmem_len,
unsigned int pin_config);
struct usba_platform_data;
struct platform_device *
at32_add_device_usba(unsigned int id, struct usba_platform_data *data);
struct ide_platform_data {
u8 cs;
};
struct platform_device *
at32_add_device_ide(unsigned int id, unsigned int extint,
struct ide_platform_data *data);
/* mask says which PWM channels to mux */
struct platform_device *at32_add_device_pwm(u32 mask);
/* depending on what's hooked up, not all SSC pins will be used */
#define ATMEL_SSC_TK 0x01
#define ATMEL_SSC_TF 0x02
#define ATMEL_SSC_TD 0x04
#define ATMEL_SSC_TX (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD)
#define ATMEL_SSC_RK 0x10
#define ATMEL_SSC_RF 0x20
#define ATMEL_SSC_RD 0x40
#define ATMEL_SSC_RX (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD)
struct platform_device *
at32_add_device_ssc(unsigned int id, unsigned int flags);
struct i2c_board_info;
struct platform_device *at32_add_device_twi(unsigned int id,
struct i2c_board_info *b,
unsigned int n);
struct mci_platform_data;
struct platform_device *
at32_add_device_mci(unsigned int id, struct mci_platform_data *data);
struct ac97c_platform_data {
unsigned short dma_rx_periph_id;
unsigned short dma_tx_periph_id;
unsigned short dma_controller_id;
int reset_pin;
};
struct platform_device *
at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data);
struct platform_device *at32_add_device_abdac(unsigned int id);
struct platform_device *at32_add_device_psif(unsigned int id);
struct cf_platform_data {
int detect_pin;
int reset_pin;
int vcc_pin;
int ready_pin;
u8 cs;
};
struct platform_device *
at32_add_device_cf(unsigned int id, unsigned int extint,
struct cf_platform_data *data);
/* NAND / SmartMedia */
struct atmel_nand_data {
int enable_pin; /* chip enable */
int det_pin; /* card detect */
int rdy_pin; /* ready/busy */
u8 ale; /* address line number connected to ALE */
u8 cle; /* address line number connected to CLE */
u8 bus_width_16; /* buswidth is 16 bit */
struct mtd_partition *(*partition_info)(int size, int *num_partitions);
};
struct platform_device *
at32_add_device_nand(unsigned int id, struct atmel_nand_data *data);
#endif /* __ASM_ARCH_BOARD_H */
include/asm-avr32/arch-at32ap/cpu.h deleted 100644 → 0
View file @ a09e64fb
/*
* AVR32 and (fake) AT91 CPU identification
*
* Copyright (C) 2007 Atmel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_CPU_H
#define __ASM_ARCH_CPU_H
/*
* Only AT32AP7000 is defined for now. We can identify the specific
* chip at runtime, but I'm not sure if it's really worth it.
*/
#ifdef CONFIG_CPU_AT32AP700X
# define cpu_is_at32ap7000() (1)
#else
# define cpu_is_at32ap7000() (0)
#endif
/*
* Since this is AVR32, we will never run on any AT91 CPU. But these
* definitions may reduce clutter in common drivers.
*/
#define cpu_is_at91rm9200() (0)
#define cpu_is_at91sam9xe() (0)
#define cpu_is_at91sam9260() (0)
#define cpu_is_at91sam9261() (0)
#define cpu_is_at91sam9263() (0)
#define cpu_is_at91sam9rl() (0)
#define cpu_is_at91cap9() (0)
#endif /* __ASM_ARCH_CPU_H */
include/asm-avr32/arch-at32ap/gpio.h deleted 100644 → 0
View file @ a09e64fb
#ifndef __ASM_AVR32_ARCH_GPIO_H
#define __ASM_AVR32_ARCH_GPIO_H
#include <linux/compiler.h>
#include <asm/irq.h>
/* Some GPIO chips can manage IRQs; some can't. The exact numbers can
* be changed if needed, but for the moment they're not configurable.
*/
#define ARCH_NR_GPIOS (NR_GPIO_IRQS + 2 * 32)
/* Arch-neutral GPIO API, supporting both "native" and external GPIOs. */
#include <asm-generic/gpio.h>
static inline int gpio_get_value(unsigned int gpio)
{
return __gpio_get_value(gpio);
}
static inline void gpio_set_value(unsigned int gpio, int value)
{
__gpio_set_value(gpio, value);
}
static inline int gpio_cansleep(unsigned int gpio)
{
return __gpio_cansleep(gpio);
}
static inline int gpio_to_irq(unsigned int gpio)
{
if (gpio < NR_GPIO_IRQS)
return gpio + GPIO_IRQ_BASE;
return -EINVAL;
}
static inline int irq_to_gpio(unsigned int irq)
{
return irq - GPIO_IRQ_BASE;
}
#endif /* __ASM_AVR32_ARCH_GPIO_H */
include/asm-avr32/arch-at32ap/init.h deleted 100644 → 0
View file @ a09e64fb
/*
* AT32AP platform initialization calls.
*
* Copyright (C) 2006 Atmel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_AVR32_AT32AP_INIT_H__
#define __ASM_AVR32_AT32AP_INIT_H__
void setup_platform(void);
void setup_board(void);
void at32_setup_serial_console(unsigned int usart_id);
#endif /* __ASM_AVR32_AT32AP_INIT_H__ */
include/asm-avr32/arch-at32ap/io.h deleted 100644 → 0
View file @ a09e64fb
#ifndef __ASM_AVR32_ARCH_AT32AP_IO_H
#define __ASM_AVR32_ARCH_AT32AP_IO_H
/* For "bizarre" halfword swapping */
#include <linux/byteorder/swabb.h>
#if defined(CONFIG_AP700X_32_BIT_SMC)
# define __swizzle_addr_b(addr) (addr ^ 3UL)
# define __swizzle_addr_w(addr) (addr ^ 2UL)
# define __swizzle_addr_l(addr) (addr)
# define ioswabb(a, x) (x)
# define ioswabw(a, x) (x)
# define ioswabl(a, x) (x)
# define __mem_ioswabb(a, x) (x)
# define __mem_ioswabw(a, x) swab16(x)
# define __mem_ioswabl(a, x) swab32(x)
#elif defined(CONFIG_AP700X_16_BIT_SMC)
# define __swizzle_addr_b(addr) (addr ^ 1UL)
# define __swizzle_addr_w(addr) (addr)
# define __swizzle_addr_l(addr) (addr)
# define ioswabb(a, x) (x)
# define ioswabw(a, x) (x)
# define ioswabl(a, x) swahw32(x)
# define __mem_ioswabb(a, x) (x)
# define __mem_ioswabw(a, x) swab16(x)
# define __mem_ioswabl(a, x) swahb32(x)
#else
# define __swizzle_addr_b(addr) (addr)
# define __swizzle_addr_w(addr) (addr)
# define __swizzle_addr_l(addr) (addr)
# define ioswabb(a, x) (x)
# define ioswabw(a, x) swab16(x)
# define ioswabl(a, x) swab32(x)
# define __mem_ioswabb(a, x) (x)
# define __mem_ioswabw(a, x) (x)
# define __mem_ioswabl(a, x) (x)
#endif
#endif /* __ASM_AVR32_ARCH_AT32AP_IO_H */
include/asm-avr32/arch-at32ap/irq.h deleted 100644 → 0
View file @ a09e64fb
#ifndef __ASM_AVR32_ARCH_IRQ_H
#define __ASM_AVR32_ARCH_IRQ_H
#define EIM_IRQ_BASE NR_INTERNAL_IRQS
#define NR_EIM_IRQS 32
#define AT32_EXTINT(n) (EIM_IRQ_BASE + (n))
#define GPIO_IRQ_BASE (EIM_IRQ_BASE + NR_EIM_IRQS)
#define NR_GPIO_CTLR (5 /*internal*/ + 1 /*external*/)
#define NR_GPIO_IRQS (NR_GPIO_CTLR * 32)
#define NR_IRQS (GPIO_IRQ_BASE + NR_GPIO_IRQS)
#endif /* __ASM_AVR32_ARCH_IRQ_H */
include/asm-avr32/arch-at32ap/pm.h deleted 100644 → 0
View file @ a09e64fb
/*
* AVR32 AP Power Management.
*
* Copyright (C) 2008 Atmel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_AVR32_ARCH_PM_H
#define __ASM_AVR32_ARCH_PM_H
/* Possible arguments to the "sleep" instruction */
#define CPU_SLEEP_IDLE 0
#define CPU_SLEEP_FROZEN 1
#define CPU_SLEEP_STANDBY 2
#define CPU_SLEEP_STOP 3
#define CPU_SLEEP_STATIC 5
#ifndef __ASSEMBLY__
extern void cpu_enter_idle(void);
extern void cpu_enter_standby(unsigned long sdramc_base);
extern bool disable_idle_sleep;
static inline void cpu_disable_idle_sleep(void)
{
disable_idle_sleep = true;
}
static inline void cpu_enable_idle_sleep(void)
{
disable_idle_sleep = false;
}
static inline void cpu_idle_sleep(void)
{
/*
* If we're using the COUNT and COMPARE registers for
* timekeeping, we can't use the IDLE state.
*/
if (disable_idle_sleep)
cpu_relax();
else
cpu_enter_idle();
}
void intc_set_suspend_handler(unsigned long offset);
#endif
#endif /* __ASM_AVR32_ARCH_PM_H */
include/asm-avr32/arch-at32ap/portmux.h deleted 100644 → 0
View file @ a09e64fb
/*
* AT32 portmux interface.
*
* Copyright (C) 2006 Atmel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_PORTMUX_H__
#define __ASM_ARCH_PORTMUX_H__
/*
* Set up pin multiplexing, called from board init only.
*
* The following flags determine the initial state of the pin.
*/
#define AT32_GPIOF_PULLUP 0x00000001 /* (not-OUT) Enable pull-up */
#define AT32_GPIOF_OUTPUT 0x00000002 /* (OUT) Enable output driver */
#define AT32_GPIOF_HIGH 0x00000004 /* (OUT) Set output high */
#define AT32_GPIOF_DEGLITCH 0x00000008 /* (IN) Filter glitches */
#define AT32_GPIOF_MULTIDRV 0x00000010 /* Enable multidriver option */
void at32_select_periph(unsigned int pin, unsigned int periph,
unsigned long flags);
void at32_select_gpio(unsigned int pin, unsigned long flags);
void at32_reserve_pin(unsigned int pin);
#endif /* __ASM_ARCH_PORTMUX_H__ */
include/asm-avr32/arch-at32ap/smc.h deleted 100644 → 0
View file @ a09e64fb
/*
* Static Memory Controller for AT32 chips
*
* Copyright (C) 2006 Atmel Corporation
*
* Inspired by the OMAP2 General-Purpose Memory Controller interface
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_AT32AP_SMC_H
#define __ARCH_AT32AP_SMC_H
/*
* All timing parameters are in nanoseconds.
*/
struct smc_timing {
/* Delay from address valid to assertion of given strobe */
int ncs_read_setup;
int nrd_setup;
int ncs_write_setup;
int nwe_setup;
/* Pulse length of given strobe */
int ncs_read_pulse;
int nrd_pulse;
int ncs_write_pulse;
int nwe_pulse;
/* Total cycle length of given operation */
int read_cycle;
int write_cycle;
/* Minimal recovery times, will extend cycle if needed */
int ncs_read_recover;
int nrd_recover;
int ncs_write_recover;
int nwe_recover;
};
/*
* All timing parameters are in clock cycles.
*/
struct smc_config {
/* Delay from address valid to assertion of given strobe */
u8 ncs_read_setup;
u8 nrd_setup;
u8 ncs_write_setup;
u8 nwe_setup;
/* Pulse length of given strobe */
u8 ncs_read_pulse;
u8 nrd_pulse;
u8 ncs_write_pulse;
u8 nwe_pulse;
/* Total cycle length of given operation */
u8 read_cycle;
u8 write_cycle;
/* Bus width in bytes */
u8 bus_width;
/*
* 0: Data is sampled on rising edge of NCS
* 1: Data is sampled on rising edge of NRD
*/
unsigned int nrd_controlled:1;
/*
* 0: Data is driven on falling edge of NCS
* 1: Data is driven on falling edge of NWR
*/
unsigned int nwe_controlled:1;
/*
* 0: NWAIT is disabled
* 1: Reserved
* 2: NWAIT is frozen mode
* 3: NWAIT in ready mode
*/
unsigned int nwait_mode:2;
/*
* 0: Byte select access type
* 1: Byte write access type
*/
unsigned int byte_write:1;
/*
* Number of clock cycles before data is released after
* the rising edge of the read controlling signal
*
* Total cycles from SMC is tdf_cycles + 1
*/
unsigned int tdf_cycles:4;
/*
* 0: TDF optimization disabled
* 1: TDF optimization enabled
*/
unsigned int tdf_mode:1;
};
extern void smc_set_timing(struct smc_config *config,
const struct smc_timing *timing);
extern int smc_set_configuration(int cs, const struct smc_config *config);
extern struct smc_config *smc_get_configuration(int cs);
#endif /* __ARCH_AT32AP_SMC_H */
include/asm-avr32/arch-at32ap/sram.h deleted 100644 → 0
View file @ a09e64fb
/*
* Simple SRAM allocator
*
* Copyright (C) 2008 Atmel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_AVR32_ARCH_SRAM_H
#define __ASM_AVR32_ARCH_SRAM_H
#include <linux/genalloc.h>
extern struct gen_pool *sram_pool;
static inline unsigned long sram_alloc(size_t len)
{
if (!sram_pool)
return 0UL;
return gen_pool_alloc(sram_pool, len);
}
static inline void sram_free(unsigned long addr, size_t len)
{
return gen_pool_free(sram_pool, addr, len);
}
#endif /* __ASM_AVR32_ARCH_SRAM_H */
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