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Commit a9e61410 authored by Alex Deucher's avatar Alex Deucher
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drm/radeon/kms: add dpm support for SI (v7) 

This adds dpm support for SI asics.  This includes:
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen1/gen2/gen3 switching
- power containment
- shader power scaling

Set radeon.dpm=1 to enable.

v2: enable hainan support, rebase
v3: guard acpi stuff
v4: fix 64 bit math
v5: fix 64 bit div harder
v6: fix thermal interrupt check noticed by Jerome
v7: attempt fix state enable
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a0ceada6
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Showing with 7665 additions and 25 deletions
drivers/gpu/drm/radeon/Makefile
View file @ a9e61410
......@@ -79,7 +79,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \
r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \
rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \
trinity_smc.o ni_dpm.o
trinity_smc.o ni_dpm.o si_smc.o si_dpm.o
radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
......
drivers/gpu/drm/radeon/atombios.h
View file @ a9e61410
......@@ -7763,6 +7763,9 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER
#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature.
#define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state.
#define ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE 0x00040000 // Does the driver supports new CAC voltage table.
#define ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY 0x00080000 // Does the driver supports revert GPIO5 polarity.
#define ATOM_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17 0x00100000 // Does the driver supports thermal2GPIO17.
#define ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE 0x00200000 // Does the driver supports VR HOT GPIO Configurable.
typedef struct _ATOM_PPLIB_POWERPLAYTABLE
{
......
drivers/gpu/drm/radeon/ni_dpm.c
View file @ a9e61410
......@@ -719,7 +719,7 @@ static const u32 cayman_sysls_enable[] =
struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
static struct ni_power_info *ni_get_pi(struct radeon_device *rdev)
struct ni_power_info *ni_get_pi(struct radeon_device *rdev)
{
struct ni_power_info *pi = rdev->pm.dpm.priv;
......@@ -1471,8 +1471,8 @@ static int ni_populate_smc_tdp_limits(struct radeon_device *rdev,
return 0;
}
static int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
u32 arb_freq_src, u32 arb_freq_dest)
int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
u32 arb_freq_src, u32 arb_freq_dest)
{
u32 mc_arb_dram_timing;
u32 mc_arb_dram_timing2;
......@@ -3488,8 +3488,8 @@ void ni_dpm_setup_asic(struct radeon_device *rdev)
rv770_enable_acpi_pm(rdev);
}
static void ni_update_current_ps(struct radeon_device *rdev,
struct radeon_ps *rps)
void ni_update_current_ps(struct radeon_device *rdev,
struct radeon_ps *rps)
{
struct ni_ps *new_ps = ni_get_ps(rps);
struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
......@@ -3500,8 +3500,8 @@ static void ni_update_current_ps(struct radeon_device *rdev,
eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
}
static void ni_update_requested_ps(struct radeon_device *rdev,
struct radeon_ps *rps)
void ni_update_requested_ps(struct radeon_device *rdev,
struct radeon_ps *rps)
{
struct ni_ps *new_ps = ni_get_ps(rps);
struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
......@@ -4192,8 +4192,12 @@ void ni_dpm_print_power_state(struct radeon_device *rdev,
printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
for (i = 0; i < ps->performance_level_count; i++) {
pl = &ps->performance_levels[i];
printk("\t\tpower level 0 sclk: %u mclk: %u vddc: %u vddci: %u\n",
pl->sclk, pl->mclk, pl->vddc, pl->vddci);
if (rdev->family >= CHIP_TAHITI)
printk("\t\tpower level 0 sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
else
printk("\t\tpower level 0 sclk: %u mclk: %u vddc: %u vddci: %u\n",
pl->sclk, pl->mclk, pl->vddc, pl->vddci);
}
r600_dpm_print_ps_status(rdev, rps);
}
......
drivers/gpu/drm/radeon/ni_dpm.h
View file @ a9e61410
......@@ -231,4 +231,11 @@ struct ni_power_info {
#define NISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E
#define NISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF
int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
u32 arb_freq_src, u32 arb_freq_dest);
void ni_update_current_ps(struct radeon_device *rdev,
struct radeon_ps *rps);
void ni_update_requested_ps(struct radeon_device *rdev,
struct radeon_ps *rps);
#endif
drivers/gpu/drm/radeon/ppsmc.h
View file @ a9e61410
......@@ -26,6 +26,9 @@
#pragma pack(push, 1)
#define PPSMC_SWSTATE_FLAG_DC 0x01
#define PPSMC_SWSTATE_FLAG_UVD 0x02
#define PPSMC_SWSTATE_FLAG_VCE 0x04
#define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
......@@ -36,17 +39,22 @@
#define PPSMC_SYSTEMFLAG_GDDR5 0x04
#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08
#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10
#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20
#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO 0x40
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07
#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01
#define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH 0x02
#define PPSMC_DISPLAY_WATERMARK_LOW 0
#define PPSMC_DISPLAY_WATERMARK_HIGH 1
#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01
#define PPSMC_STATEFLAG_POWERBOOST 0x02
#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40
#define PPSMC_Result_OK ((uint8_t)0x01)
#define PPSMC_Result_Failed ((uint8_t)0xFF)
......@@ -80,9 +88,14 @@ typedef uint8_t PPSMC_Result;
#define PPSMC_CACLongTermAvgEnable ((uint8_t)0x6E)
#define PPSMC_CACLongTermAvgDisable ((uint8_t)0x6F)
#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint8_t)0x7A)
#define PPSMC_FlushDataCache ((uint8_t)0x80)
#define PPSMC_MSG_SetEnabledLevels ((uint8_t)0x82)
#define PPSMC_MSG_SetForcedLevels ((uint8_t)0x83)
#define PPSMC_MSG_ResetToDefaults ((uint8_t)0x84)
#define PPSMC_MSG_EnableDTE ((uint8_t)0x87)
#define PPSMC_MSG_DisableDTE ((uint8_t)0x88)
#define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint8_t)0x96)
#define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint8_t)0x97)
/* TN */
#define PPSMC_MSG_DPM_Config ((uint32_t) 0x102)
......
drivers/gpu/drm/radeon/r600_dpm.c
View file @ a9e61410
......@@ -906,6 +906,7 @@ int r600_parse_extended_power_table(struct radeon_device *rdev)
sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE5)) {
rdev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit);
rdev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit);
rdev->pm.dpm.near_tdp_limit_adjusted = rdev->pm.dpm.near_tdp_limit;
rdev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit);
if (rdev->pm.dpm.tdp_od_limit)
rdev->pm.dpm.power_control = true;
......
drivers/gpu/drm/radeon/radeon.h
View file @ a9e61410
......@@ -1359,6 +1359,7 @@ struct radeon_dpm {
struct radeon_dpm_fan fan;
u32 tdp_limit;
u32 near_tdp_limit;
u32 near_tdp_limit_adjusted;
u32 sq_ramping_threshold;
u32 cac_leakage;
u16 tdp_od_limit;
......
drivers/gpu/drm/radeon/radeon_asic.c
View file @ a9e61410
......@@ -2262,6 +2262,20 @@ static struct radeon_asic si_asic = {
.set_uvd_clocks = &si_set_uvd_clocks,
.get_temperature = &si_get_temp,
},
.dpm = {
.init = &si_dpm_init,
.setup_asic = &si_dpm_setup_asic,
.enable = &si_dpm_enable,
.disable = &si_dpm_disable,
.pre_set_power_state = &si_dpm_pre_set_power_state,
.set_power_state = &si_dpm_set_power_state,
.post_set_power_state = &si_dpm_post_set_power_state,
.display_configuration_changed = &si_dpm_display_configuration_changed,
.fini = &si_dpm_fini,
.get_sclk = &ni_dpm_get_sclk,
.get_mclk = &ni_dpm_get_mclk,
.print_power_state = &ni_dpm_print_power_state,
},
.pflip = {
.pre_page_flip = &evergreen_pre_page_flip,
.page_flip = &evergreen_page_flip,
......
drivers/gpu/drm/radeon/radeon_asic.h
View file @ a9e61410
......@@ -658,6 +658,15 @@ u32 si_get_xclk(struct radeon_device *rdev);
uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
int si_get_temp(struct radeon_device *rdev);
int si_dpm_init(struct radeon_device *rdev);
void si_dpm_setup_asic(struct radeon_device *rdev);
int si_dpm_enable(struct radeon_device *rdev);
void si_dpm_disable(struct radeon_device *rdev);
int si_dpm_pre_set_power_state(struct radeon_device *rdev);
int si_dpm_set_power_state(struct radeon_device *rdev);
void si_dpm_post_set_power_state(struct radeon_device *rdev);
void si_dpm_fini(struct radeon_device *rdev);
void si_dpm_display_configuration_changed(struct radeon_device *rdev);
/* DCE8 - CIK */
void dce8_bandwidth_update(struct radeon_device *rdev);
......
drivers/gpu/drm/radeon/radeon_pm.c
View file @ a9e61410
......@@ -1096,6 +1096,11 @@ int radeon_pm_init(struct radeon_device *rdev)
case CHIP_CAICOS:
case CHIP_CAYMAN:
case CHIP_ARUBA:
case CHIP_TAHITI:
case CHIP_PITCAIRN:
case CHIP_VERDE:
case CHIP_OLAND:
case CHIP_HAINAN:
if (radeon_dpm == 1)
rdev->pm.pm_method = PM_METHOD_DPM;
else
......
drivers/gpu/drm/radeon/radeon_ucode.h
View file @ a9e61410
......@@ -111,4 +111,19 @@
#define CAYMAN_SMC_INT_VECTOR_START 0xffc0
#define CAYMAN_SMC_INT_VECTOR_SIZE 0x0040
#define TAHITI_SMC_UCODE_START 0x10000
#define TAHITI_SMC_UCODE_SIZE 0xf458
#define PITCAIRN_SMC_UCODE_START 0x10000
#define PITCAIRN_SMC_UCODE_SIZE 0xe9f4
#define VERDE_SMC_UCODE_START 0x10000
#define VERDE_SMC_UCODE_SIZE 0xebe4
#define OLAND_SMC_UCODE_START 0x10000
#define OLAND_SMC_UCODE_SIZE 0xe7b4
#define HAINAN_SMC_UCODE_START 0x10000
#define HAINAN_SMC_UCODE_SIZE 0xe67C
#endif
drivers/gpu/drm/radeon/rv770_dpm.h
View file @ a9e61410
......@@ -144,6 +144,7 @@ struct rv7xx_pl {
u16 vddc;
u16 vddci; /* eg+ only */
u32 flags;
enum radeon_pcie_gen pcie_gen; /* si+ only */
};
struct rv7xx_ps {
......
drivers/gpu/drm/radeon/si.c
View file @ a9e61410
......@@ -41,26 +41,31 @@ MODULE_FIRMWARE("radeon/TAHITI_me.bin");
MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
MODULE_FIRMWARE("radeon/TAHITI_smc.bin");
MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
MODULE_FIRMWARE("radeon/PITCAIRN_smc.bin");
MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
MODULE_FIRMWARE("radeon/VERDE_me.bin");
MODULE_FIRMWARE("radeon/VERDE_ce.bin");
MODULE_FIRMWARE("radeon/VERDE_mc.bin");
MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
MODULE_FIRMWARE("radeon/VERDE_smc.bin");
MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
MODULE_FIRMWARE("radeon/OLAND_me.bin");
MODULE_FIRMWARE("radeon/OLAND_ce.bin");
MODULE_FIRMWARE("radeon/OLAND_mc.bin");
MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
MODULE_FIRMWARE("radeon/OLAND_smc.bin");
MODULE_FIRMWARE("radeon/HAINAN_pfp.bin");
MODULE_FIRMWARE("radeon/HAINAN_me.bin");
MODULE_FIRMWARE("radeon/HAINAN_ce.bin");
MODULE_FIRMWARE("radeon/HAINAN_mc.bin");
MODULE_FIRMWARE("radeon/HAINAN_rlc.bin");
MODULE_FIRMWARE("radeon/HAINAN_smc.bin");
static void si_pcie_gen3_enable(struct radeon_device *rdev);
static void si_program_aspm(struct radeon_device *rdev);
......@@ -1540,6 +1545,7 @@ static int si_init_microcode(struct radeon_device *rdev)
const char *chip_name;
const char *rlc_chip_name;
size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
size_t smc_req_size;
char fw_name[30];
int err;
......@@ -1561,6 +1567,7 @@ static int si_init_microcode(struct radeon_device *rdev)
ce_req_size = SI_CE_UCODE_SIZE * 4;
rlc_req_size = SI_RLC_UCODE_SIZE * 4;
mc_req_size = SI_MC_UCODE_SIZE * 4;
smc_req_size = ALIGN(TAHITI_SMC_UCODE_SIZE, 4);
break;
case CHIP_PITCAIRN:
chip_name = "PITCAIRN";
......@@ -1570,6 +1577,7 @@ static int si_init_microcode(struct radeon_device *rdev)
ce_req_size = SI_CE_UCODE_SIZE * 4;
rlc_req_size = SI_RLC_UCODE_SIZE * 4;
mc_req_size = SI_MC_UCODE_SIZE * 4;
smc_req_size = ALIGN(PITCAIRN_SMC_UCODE_SIZE, 4);
break;
case CHIP_VERDE:
chip_name = "VERDE";
......@@ -1579,6 +1587,7 @@ static int si_init_microcode(struct radeon_device *rdev)
ce_req_size = SI_CE_UCODE_SIZE * 4;
rlc_req_size = SI_RLC_UCODE_SIZE * 4;
mc_req_size = SI_MC_UCODE_SIZE * 4;
smc_req_size = ALIGN(VERDE_SMC_UCODE_SIZE, 4);
break;
case CHIP_OLAND:
chip_name = "OLAND";
......@@ -1588,6 +1597,7 @@ static int si_init_microcode(struct radeon_device *rdev)
ce_req_size = SI_CE_UCODE_SIZE * 4;
rlc_req_size = SI_RLC_UCODE_SIZE * 4;
mc_req_size = OLAND_MC_UCODE_SIZE * 4;
smc_req_size = ALIGN(OLAND_SMC_UCODE_SIZE, 4);
break;
case CHIP_HAINAN:
chip_name = "HAINAN";
......@@ -1597,6 +1607,7 @@ static int si_init_microcode(struct radeon_device *rdev)
ce_req_size = SI_CE_UCODE_SIZE * 4;
rlc_req_size = SI_RLC_UCODE_SIZE * 4;
mc_req_size = OLAND_MC_UCODE_SIZE * 4;
smc_req_size = ALIGN(HAINAN_SMC_UCODE_SIZE, 4);
break;
default: BUG();
}
......@@ -1659,6 +1670,17 @@ static int si_init_microcode(struct radeon_device *rdev)
err = -EINVAL;
}
snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
err = request_firmware(&rdev->smc_fw, fw_name, &pdev->dev);
if (err)
goto out;
if (rdev->smc_fw->size != smc_req_size) {
printk(KERN_ERR
"si_smc: Bogus length %zu in firmware \"%s\"\n",
rdev->smc_fw->size, fw_name);
err = -EINVAL;
}
out:
platform_device_unregister(pdev);
......@@ -1677,6 +1699,8 @@ static int si_init_microcode(struct radeon_device *rdev)
rdev->rlc_fw = NULL;
release_firmware(rdev->mc_fw);
rdev->mc_fw = NULL;
release_firmware(rdev->smc_fw);
rdev->smc_fw = NULL;
}
return err;
}
......@@ -5420,6 +5444,7 @@ int si_irq_set(struct radeon_device *rdev)
u32 grbm_int_cntl = 0;
u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
u32 dma_cntl, dma_cntl1;
u32 thermal_int = 0;
if (!rdev->irq.installed) {
WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
......@@ -5445,6 +5470,9 @@ int si_irq_set(struct radeon_device *rdev)
dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
thermal_int = RREG32(CG_THERMAL_INT) &
~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
/* enable CP interrupts on all rings */
if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
DRM_DEBUG("si_irq_set: sw int gfx\n");
......@@ -5531,6 +5559,11 @@ int si_irq_set(struct radeon_device *rdev)
WREG32(GRBM_INT_CNTL, grbm_int_cntl);
if (rdev->irq.dpm_thermal) {
DRM_DEBUG("dpm thermal\n");
thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
}
if (rdev->num_crtc >= 2) {
WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
......@@ -5566,6 +5599,8 @@ int si_irq_set(struct radeon_device *rdev)
WREG32(DC_HPD6_INT_CONTROL, hpd6);
}
WREG32(CG_THERMAL_INT, thermal_int);
return 0;
}
......@@ -5730,6 +5765,7 @@ int si_irq_process(struct radeon_device *rdev)
u32 src_id, src_data, ring_id;
u32 ring_index;
bool queue_hotplug = false;
bool queue_thermal = false;
if (!rdev->ih.enabled || rdev->shutdown)
return IRQ_NONE;
......@@ -6000,6 +6036,16 @@ int si_irq_process(struct radeon_device *rdev)
DRM_DEBUG("IH: DMA trap\n");
radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
break;
case 230: /* thermal low to high */
DRM_DEBUG("IH: thermal low to high\n");
rdev->pm.dpm.thermal.high_to_low = false;
queue_thermal = true;
break;
case 231: /* thermal high to low */
DRM_DEBUG("IH: thermal high to low\n");
rdev->pm.dpm.thermal.high_to_low = true;
queue_thermal = true;
break;
case 233: /* GUI IDLE */
DRM_DEBUG("IH: GUI idle\n");
break;
......@@ -6018,6 +6064,8 @@ int si_irq_process(struct radeon_device *rdev)
}
if (queue_hotplug)
schedule_work(&rdev->hotplug_work);
if (queue_thermal && rdev->pm.dpm_enabled)
schedule_work(&rdev->pm.dpm.thermal.work);
rdev->ih.rptr = rptr;
WREG32(IH_RB_RPTR, rdev->ih.rptr);
atomic_set(&rdev->ih.lock, 0);
......
drivers/gpu/drm/radeon/si_dpm.c 0 → 100644
View file @ a9e61410
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/gpu/drm/radeon/si_dpm.h 0 → 100644
View file @ a9e61410
/*
* Copyright 2012 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __SI_DPM_H__
#define __SI_DPM_H__
#include "ni_dpm.h"
#include "sislands_smc.h"
enum si_cac_config_reg_type
{
SISLANDS_CACCONFIG_MMR = 0,
SISLANDS_CACCONFIG_CGIND,
SISLANDS_CACCONFIG_MAX
};
struct si_cac_config_reg
{
u32 offset;
u32 mask;
u32 shift;
u32 value;
enum si_cac_config_reg_type type;
};
struct si_powertune_data
{
u32 cac_window;
u32 l2_lta_window_size_default;
u8 lts_truncate_default;
u8 shift_n_default;
u8 operating_temp;
struct ni_leakage_coeffients leakage_coefficients;
u32 fixed_kt;
u32 lkge_lut_v0_percent;
u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];
bool enable_powertune_by_default;
};
struct si_dyn_powertune_data
{
u32 cac_leakage;
s32 leakage_minimum_temperature;
u32 wintime;
u32 l2_lta_window_size;
u8 lts_truncate;
u8 shift_n;
u8 dc_pwr_value;
bool disable_uvd_powertune;
};
struct si_dte_data
{
u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
u32 k;
u32 t0;
u32 max_t;
u8 window_size;
u8 temp_select;
u8 dte_mode;
u8 tdep_count;
u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
u32 t_threshold;
bool enable_dte_by_default;
};
struct si_clock_registers {
u32 cg_spll_func_cntl;
u32 cg_spll_func_cntl_2;
u32 cg_spll_func_cntl_3;
u32 cg_spll_func_cntl_4;
u32 cg_spll_spread_spectrum;
u32 cg_spll_spread_spectrum_2;
u32 dll_cntl;
u32 mclk_pwrmgt_cntl;
u32 mpll_ad_func_cntl;
u32 mpll_dq_func_cntl;
u32 mpll_func_cntl;
u32 mpll_func_cntl_1;
u32 mpll_func_cntl_2;
u32 mpll_ss1;
u32 mpll_ss2;
};
struct si_mc_reg_entry {
u32 mclk_max;
u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
};
struct si_mc_reg_table {
u8 last;
u8 num_entries;
u16 valid_flag;
struct si_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
};
#define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT 0
#define SISLANDS_MCREGISTERTABLE_ACPI_SLOT 1
#define SISLANDS_MCREGISTERTABLE_ULV_SLOT 2
#define SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT 3
struct si_leakage_voltage_entry
{
u16 voltage;
u16 leakage_index;
};
#define SISLANDS_LEAKAGE_INDEX0 0xff01
#define SISLANDS_MAX_LEAKAGE_COUNT 4
struct si_leakage_voltage
{
u16 count;
struct si_leakage_voltage_entry entries[SISLANDS_MAX_LEAKAGE_COUNT];
};
#define SISLANDS_MAX_HARDWARE_POWERLEVELS 5
struct si_ulv_param {
bool supported;
u32 cg_ulv_control;
u32 cg_ulv_parameter;
u32 volt_change_delay;
struct rv7xx_pl pl;
bool one_pcie_lane_in_ulv;
};
struct si_power_info {
/* must be first! */
struct ni_power_info ni;
struct si_clock_registers clock_registers;
struct si_mc_reg_table mc_reg_table;
struct atom_voltage_table mvdd_voltage_table;
struct atom_voltage_table vddc_phase_shed_table;
struct si_leakage_voltage leakage_voltage;
u16 mvdd_bootup_value;
struct si_ulv_param ulv;
u32 max_cu;
/* pcie gen */
enum radeon_pcie_gen force_pcie_gen;
enum radeon_pcie_gen boot_pcie_gen;
enum radeon_pcie_gen acpi_pcie_gen;
u32 sys_pcie_mask;
/* flags */
bool enable_dte;
bool enable_ppm;
bool vddc_phase_shed_control;
bool pspp_notify_required;
bool sclk_deep_sleep_above_low;
/* smc offsets */
u32 sram_end;
u32 state_table_start;
u32 soft_regs_start;
u32 mc_reg_table_start;
u32 arb_table_start;
u32 cac_table_start;
u32 dte_table_start;
u32 spll_table_start;
u32 papm_cfg_table_start;
/* CAC stuff */
const struct si_cac_config_reg *cac_weights;
const struct si_cac_config_reg *lcac_config;
const struct si_cac_config_reg *cac_override;
const struct si_powertune_data *powertune_data;
struct si_dyn_powertune_data dyn_powertune_data;
/* DTE stuff */
struct si_dte_data dte_data;
/* scratch structs */
SMC_SIslands_MCRegisters smc_mc_reg_table;
SISLANDS_SMC_STATETABLE smc_statetable;
PP_SIslands_PAPMParameters papm_parm;
};
#define SISLANDS_INITIAL_STATE_ARB_INDEX 0
#define SISLANDS_ACPI_STATE_ARB_INDEX 1
#define SISLANDS_ULV_STATE_ARB_INDEX 2
#define SISLANDS_DRIVER_STATE_ARB_INDEX 3
#define SISLANDS_DPM2_MAX_PULSE_SKIP 256
#define SISLANDS_DPM2_NEAR_TDP_DEC 10
#define SISLANDS_DPM2_ABOVE_SAFE_INC 5
#define SISLANDS_DPM2_BELOW_SAFE_INC 20
#define SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT 80
#define SISLANDS_DPM2_MAXPS_PERCENT_H 99
#define SISLANDS_DPM2_MAXPS_PERCENT_M 99
#define SISLANDS_DPM2_SQ_RAMP_MAX_POWER 0x3FFF
#define SISLANDS_DPM2_SQ_RAMP_MIN_POWER 0x12
#define SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15
#define SISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E
#define SISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF
#define SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN 10
#define SISLANDS_VRC_DFLT 0xC000B3
#define SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT 1687
#define SISLANDS_CGULVPARAMETER_DFLT 0x00040035
#define SISLANDS_CGULVCONTROL_DFLT 0x1f007550
#endif
drivers/gpu/drm/radeon/si_smc.c 0 → 100644
View file @ a9e61410
/*
* Copyright 2011 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Alex Deucher
*/
#include <linux/firmware.h>
#include "drmP.h"
#include "radeon.h"
#include "sid.h"
#include "ppsmc.h"
#include "radeon_ucode.h"
int si_set_smc_sram_address(struct radeon_device *rdev,
u32 smc_address, u32 limit)
{
if (smc_address & 3)
return -EINVAL;
if ((smc_address + 3) > limit)
return -EINVAL;
WREG32(SMC_IND_INDEX_0, smc_address);
WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
return 0;
}
int si_copy_bytes_to_smc(struct radeon_device *rdev,
u32 smc_start_address,
const u8 *src, u32 byte_count, u32 limit)
{
int ret;
u32 data, original_data, addr, extra_shift;
if (smc_start_address & 3)
return -EINVAL;
if ((smc_start_address + byte_count) > limit)
return -EINVAL;
addr = smc_start_address;
while (byte_count >= 4) {
/* SMC address space is BE */
data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
ret = si_set_smc_sram_address(rdev, addr, limit);
if (ret)
return ret;
WREG32(SMC_IND_DATA_0, data);
src += 4;
byte_count -= 4;
addr += 4;
}
/* RMW for the final bytes */
if (byte_count > 0) {
data = 0;
ret = si_set_smc_sram_address(rdev, addr, limit);
if (ret)
return ret;
original_data = RREG32(SMC_IND_DATA_0);
extra_shift = 8 * (4 - byte_count);
while (byte_count > 0) {
/* SMC address space is BE */
data = (data << 8) + *src++;
byte_count--;
}
data <<= extra_shift;
data |= (original_data & ~((~0UL) << extra_shift));
ret = si_set_smc_sram_address(rdev, addr, limit);
if (ret)
return ret;
WREG32(SMC_IND_DATA_0, data);
}
return 0;
}
void si_start_smc(struct radeon_device *rdev)
{
u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
tmp &= ~RST_REG;
WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
}
void si_reset_smc(struct radeon_device *rdev)
{
u32 tmp;
RREG32(CB_CGTT_SCLK_CTRL);
RREG32(CB_CGTT_SCLK_CTRL);
RREG32(CB_CGTT_SCLK_CTRL);
RREG32(CB_CGTT_SCLK_CTRL);
tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
tmp |= RST_REG;
WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
}
int si_program_jump_on_start(struct radeon_device *rdev)
{
static u8 data[] = { 0x0E, 0x00, 0x40, 0x40 };
return si_copy_bytes_to_smc(rdev, 0x0, data, 4, sizeof(data)+1);
}
void si_stop_smc_clock(struct radeon_device *rdev)
{
u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
tmp |= CK_DISABLE;
WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
}
void si_start_smc_clock(struct radeon_device *rdev)
{
u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
tmp &= ~CK_DISABLE;
WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
}
bool si_is_smc_running(struct radeon_device *rdev)
{
u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
if (!(rst & RST_REG) && !(clk & CK_DISABLE))
return true;
return false;
}
PPSMC_Result si_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg)
{
u32 tmp;
int i;
if (!si_is_smc_running(rdev))
return PPSMC_Result_Failed;
WREG32(SMC_MESSAGE_0, msg);
for (i = 0; i < rdev->usec_timeout; i++) {
tmp = RREG32(SMC_RESP_0);
if (tmp != 0)
break;
udelay(1);
}
tmp = RREG32(SMC_RESP_0);
return (PPSMC_Result)tmp;
}
PPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev)
{
u32 tmp;
int i;
if (!si_is_smc_running(rdev))
return PPSMC_Result_OK;
for (i = 0; i < rdev->usec_timeout; i++) {
tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
if ((tmp & CKEN) == 0)
break;
udelay(1);
}
return PPSMC_Result_OK;
}
int si_load_smc_ucode(struct radeon_device *rdev, u32 limit)
{
u32 ucode_start_address;
u32 ucode_size;
const u8 *src;
u32 data;
if (!rdev->smc_fw)
return -EINVAL;
switch (rdev->family) {
case CHIP_TAHITI:
ucode_start_address = TAHITI_SMC_UCODE_START;
ucode_size = TAHITI_SMC_UCODE_SIZE;
break;
case CHIP_PITCAIRN:
ucode_start_address = PITCAIRN_SMC_UCODE_START;
ucode_size = PITCAIRN_SMC_UCODE_SIZE;
break;
case CHIP_VERDE:
ucode_start_address = VERDE_SMC_UCODE_START;
ucode_size = VERDE_SMC_UCODE_SIZE;
break;
case CHIP_OLAND:
ucode_start_address = OLAND_SMC_UCODE_START;
ucode_size = OLAND_SMC_UCODE_SIZE;
break;
case CHIP_HAINAN:
ucode_start_address = HAINAN_SMC_UCODE_START;
ucode_size = HAINAN_SMC_UCODE_SIZE;
break;
default:
DRM_ERROR("unknown asic in smc ucode loader\n");
BUG();
}
if (ucode_size & 3)
return -EINVAL;
src = (const u8 *)rdev->smc_fw->data;
WREG32(SMC_IND_INDEX_0, ucode_start_address);
WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
while (ucode_size >= 4) {
/* SMC address space is BE */
data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
WREG32(SMC_IND_DATA_0, data);
src += 4;
ucode_size -= 4;
}
WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
return 0;
}
int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
u32 *value, u32 limit)
{
int ret;
ret = si_set_smc_sram_address(rdev, smc_address, limit);
if (ret)
return ret;
*value = RREG32(SMC_IND_DATA_0);
return 0;
}
int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
u32 value, u32 limit)
{
int ret;
ret = si_set_smc_sram_address(rdev, smc_address, limit);
if (ret)
return ret;
WREG32(SMC_IND_DATA_0, value);
return 0;
}
drivers/gpu/drm/radeon/sid.h
View file @ a9e61410
......@@ -48,12 +48,76 @@
#define SI_MAX_TCC 16
#define SI_MAX_TCC_MASK 0xFFFF
/* SMC IND accessor regs */
#define SMC_IND_INDEX_0 0x200
#define SMC_IND_DATA_0 0x204
#define SMC_IND_ACCESS_CNTL 0x228
# define AUTO_INCREMENT_IND_0 (1 << 0)
#define SMC_MESSAGE_0 0x22c
#define SMC_RESP_0 0x230
/* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */
#define SMC_CG_IND_START 0xc0030000
#define SMC_CG_IND_END 0xc0040000
#define CG_CGTT_LOCAL_0 0x400
#define CG_CGTT_LOCAL_1 0x401
/* SMC IND registers */
#define SMC_SYSCON_RESET_CNTL 0x80000000
# define RST_REG (1 << 0)
#define SMC_SYSCON_CLOCK_CNTL_0 0x80000004
# define CK_DISABLE (1 << 0)
# define CKEN (1 << 24)
#define VGA_HDP_CONTROL 0x328
#define VGA_MEMORY_DISABLE (1 << 4)
#define DCCG_DISP_SLOW_SELECT_REG 0x4fc
#define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0)
#define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0)
#define DCCG_DISP1_SLOW_SELECT_SHIFT 0
#define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4)
#define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4)
#define DCCG_DISP2_SLOW_SELECT_SHIFT 4
#define CG_SPLL_FUNC_CNTL 0x600
#define SPLL_RESET (1 << 0)
#define SPLL_SLEEP (1 << 1)
#define SPLL_BYPASS_EN (1 << 3)
#define SPLL_REF_DIV(x) ((x) << 4)
#define SPLL_REF_DIV_MASK (0x3f << 4)
#define SPLL_PDIV_A(x) ((x) << 20)
#define SPLL_PDIV_A_MASK (0x7f << 20)
#define SPLL_PDIV_A_SHIFT 20
#define CG_SPLL_FUNC_CNTL_2 0x604
#define SCLK_MUX_SEL(x) ((x) << 0)
#define SCLK_MUX_SEL_MASK (0x1ff << 0)
#define CG_SPLL_FUNC_CNTL_3 0x608
#define SPLL_FB_DIV(x) ((x) << 0)
#define SPLL_FB_DIV_MASK (0x3ffffff << 0)
#define SPLL_FB_DIV_SHIFT 0
#define SPLL_DITHEN (1 << 28)
#define CG_SPLL_FUNC_CNTL_4 0x60c
#define SPLL_CNTL_MODE 0x618
# define SPLL_REFCLK_SEL(x) ((x) << 8)
# define SPLL_REFCLK_SEL_MASK 0xFF00
#define CG_SPLL_SPREAD_SPECTRUM 0x620
#define SSEN (1 << 0)
#define CLK_S(x) ((x) << 4)
#define CLK_S_MASK (0xfff << 4)
#define CLK_S_SHIFT 4
#define CG_SPLL_SPREAD_SPECTRUM_2 0x624
#define CLK_V(x) ((x) << 0)
#define CLK_V_MASK (0x3ffffff << 0)
#define CLK_V_SHIFT 0
#define CG_SPLL_AUTOSCALE_CNTL 0x62c
# define AUTOSCALE_ON_SS_CLEAR (1 << 9)
/* discrete uvd clocks */
#define CG_UPLL_FUNC_CNTL 0x634
# define UPLL_RESET_MASK 0x00000001
......@@ -83,21 +147,6 @@
#define CG_UPLL_SPREAD_SPECTRUM 0x650
# define SSEN_MASK 0x00000001
#define CG_MULT_THERMAL_STATUS 0x714
#define ASIC_MAX_TEMP(x) ((x) << 0)
#define ASIC_MAX_TEMP_MASK 0x000001ff
#define ASIC_MAX_TEMP_SHIFT 0
#define CTF_TEMP(x) ((x) << 9)
#define CTF_TEMP_MASK 0x0003fe00
#define CTF_TEMP_SHIFT 9
#define VGA_HDP_CONTROL 0x328
#define VGA_MEMORY_DISABLE (1 << 4)
#define SPLL_CNTL_MODE 0x618
# define SPLL_REFCLK_SEL(x) ((x) << 8)
# define SPLL_REFCLK_SEL_MASK 0xFF00
#define MPLL_BYPASSCLK_SEL 0x65c
# define MPLL_CLKOUT_SEL(x) ((x) << 8)
# define MPLL_CLKOUT_SEL_MASK 0xFF00
......@@ -120,6 +169,111 @@
# define ZCLK_SEL(x) ((x) << 8)
# define ZCLK_SEL_MASK 0xFF00
#define CG_THERMAL_CTRL 0x700
#define DPM_EVENT_SRC(x) ((x) << 0)
#define DPM_EVENT_SRC_MASK (7 << 0)
#define DIG_THERM_DPM(x) ((x) << 14)
#define DIG_THERM_DPM_MASK 0x003FC000
#define DIG_THERM_DPM_SHIFT 14
#define CG_THERMAL_INT 0x708
#define DIG_THERM_INTH(x) ((x) << 8)
#define DIG_THERM_INTH_MASK 0x0000FF00
#define DIG_THERM_INTH_SHIFT 8
#define DIG_THERM_INTL(x) ((x) << 16)
#define DIG_THERM_INTL_MASK 0x00FF0000
#define DIG_THERM_INTL_SHIFT 16
#define THERM_INT_MASK_HIGH (1 << 24)
#define THERM_INT_MASK_LOW (1 << 25)
#define CG_MULT_THERMAL_STATUS 0x714
#define ASIC_MAX_TEMP(x) ((x) << 0)
#define ASIC_MAX_TEMP_MASK 0x000001ff
#define ASIC_MAX_TEMP_SHIFT 0
#define CTF_TEMP(x) ((x) << 9)
#define CTF_TEMP_MASK 0x0003fe00
#define CTF_TEMP_SHIFT 9
#define GENERAL_PWRMGT 0x780
# define GLOBAL_PWRMGT_EN (1 << 0)
# define STATIC_PM_EN (1 << 1)
# define THERMAL_PROTECTION_DIS (1 << 2)
# define THERMAL_PROTECTION_TYPE (1 << 3)
# define SW_SMIO_INDEX(x) ((x) << 6)
# define SW_SMIO_INDEX_MASK (1 << 6)
# define SW_SMIO_INDEX_SHIFT 6
# define VOLT_PWRMGT_EN (1 << 10)
# define DYN_SPREAD_SPECTRUM_EN (1 << 23)
#define CG_TPC 0x784
#define SCLK_PWRMGT_CNTL 0x788
# define SCLK_PWRMGT_OFF (1 << 0)
# define SCLK_LOW_D1 (1 << 1)
# define FIR_RESET (1 << 4)
# define FIR_FORCE_TREND_SEL (1 << 5)
# define FIR_TREND_MODE (1 << 6)
# define DYN_GFX_CLK_OFF_EN (1 << 7)
# define GFX_CLK_FORCE_ON (1 << 8)
# define GFX_CLK_REQUEST_OFF (1 << 9)
# define GFX_CLK_FORCE_OFF (1 << 10)
# define GFX_CLK_OFF_ACPI_D1 (1 << 11)
# define GFX_CLK_OFF_ACPI_D2 (1 << 12)
# define GFX_CLK_OFF_ACPI_D3 (1 << 13)
# define DYN_LIGHT_SLEEP_EN (1 << 14)
#define CG_FTV 0x7bc
#define CG_FFCT_0 0x7c0
# define UTC_0(x) ((x) << 0)
# define UTC_0_MASK (0x3ff << 0)
# define DTC_0(x) ((x) << 10)
# define DTC_0_MASK (0x3ff << 10)
#define CG_BSP 0x7fc
# define BSP(x) ((x) << 0)
# define BSP_MASK (0xffff << 0)
# define BSU(x) ((x) << 16)
# define BSU_MASK (0xf << 16)
#define CG_AT 0x800
# define CG_R(x) ((x) << 0)
# define CG_R_MASK (0xffff << 0)
# define CG_L(x) ((x) << 16)
# define CG_L_MASK (0xffff << 16)
#define CG_GIT 0x804
# define CG_GICST(x) ((x) << 0)
# define CG_GICST_MASK (0xffff << 0)
# define CG_GIPOT(x) ((x) << 16)
# define CG_GIPOT_MASK (0xffff << 16)
#define CG_SSP 0x80c
# define SST(x) ((x) << 0)
# define SST_MASK (0xffff << 0)
# define SSTU(x) ((x) << 16)
# define SSTU_MASK (0xf << 16)
#define CG_DISPLAY_GAP_CNTL 0x828
# define DISP1_GAP(x) ((x) << 0)
# define DISP1_GAP_MASK (3 << 0)
# define DISP2_GAP(x) ((x) << 2)
# define DISP2_GAP_MASK (3 << 2)
# define VBI_TIMER_COUNT(x) ((x) << 4)
# define VBI_TIMER_COUNT_MASK (0x3fff << 4)
# define VBI_TIMER_UNIT(x) ((x) << 20)
# define VBI_TIMER_UNIT_MASK (7 << 20)
# define DISP1_GAP_MCHG(x) ((x) << 24)
# define DISP1_GAP_MCHG_MASK (3 << 24)
# define DISP2_GAP_MCHG(x) ((x) << 26)
# define DISP2_GAP_MCHG_MASK (3 << 26)
#define CG_ULV_CONTROL 0x878
#define CG_ULV_PARAMETER 0x87c
#define SMC_SCRATCH0 0x884
#define CG_CAC_CTRL 0x8b8
# define CAC_WINDOW(x) ((x) << 0)
# define CAC_WINDOW_MASK 0x00ffffff
#define DMIF_ADDR_CONFIG 0xBD4
#define DMIF_ADDR_CALC 0xC00
......@@ -285,6 +439,23 @@
#define NOOFGROUPS_SHIFT 12
#define NOOFGROUPS_MASK 0x00001000
#define MC_ARB_DRAM_TIMING 0x2774
#define MC_ARB_DRAM_TIMING2 0x2778
#define MC_ARB_BURST_TIME 0x2808
#define STATE0(x) ((x) << 0)
#define STATE0_MASK (0x1f << 0)
#define STATE0_SHIFT 0
#define STATE1(x) ((x) << 5)
#define STATE1_MASK (0x1f << 5)
#define STATE1_SHIFT 5
#define STATE2(x) ((x) << 10)
#define STATE2_MASK (0x1f << 10)
#define STATE2_SHIFT 10
#define STATE3(x) ((x) << 15)
#define STATE3_MASK (0x1f << 15)
#define STATE3_SHIFT 15
#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808
#define TRAIN_DONE_D0 (1 << 30)
#define TRAIN_DONE_D1 (1 << 31)
......@@ -292,15 +463,105 @@
#define MC_SEQ_SUP_CNTL 0x28c8
#define RUN_MASK (1 << 0)
#define MC_SEQ_SUP_PGM 0x28cc
#define MC_PMG_AUTO_CMD 0x28d0
#define MC_IO_PAD_CNTL_D0 0x29d0
#define MEM_FALL_OUT_CMD (1 << 8)
#define MC_SEQ_RAS_TIMING 0x28a0
#define MC_SEQ_CAS_TIMING 0x28a4
#define MC_SEQ_MISC_TIMING 0x28a8
#define MC_SEQ_MISC_TIMING2 0x28ac
#define MC_SEQ_PMG_TIMING 0x28b0
#define MC_SEQ_RD_CTL_D0 0x28b4
#define MC_SEQ_RD_CTL_D1 0x28b8
#define MC_SEQ_WR_CTL_D0 0x28bc
#define MC_SEQ_WR_CTL_D1 0x28c0
#define MC_SEQ_MISC0 0x2a00
#define MC_SEQ_MISC0_VEN_ID_SHIFT 8
#define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00
#define MC_SEQ_MISC0_VEN_ID_VALUE 3
#define MC_SEQ_MISC0_REV_ID_SHIFT 12
#define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000
#define MC_SEQ_MISC0_REV_ID_VALUE 1
#define MC_SEQ_MISC0_GDDR5_SHIFT 28
#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
#define MC_SEQ_MISC0_GDDR5_VALUE 5
#define MC_SEQ_MISC1 0x2a04
#define MC_SEQ_RESERVE_M 0x2a08
#define MC_PMG_CMD_EMRS 0x2a0c
#define MC_SEQ_IO_DEBUG_INDEX 0x2a44
#define MC_SEQ_IO_DEBUG_DATA 0x2a48
#define MC_SEQ_MISC5 0x2a54
#define MC_SEQ_MISC6 0x2a58
#define MC_SEQ_MISC7 0x2a64
#define MC_SEQ_RAS_TIMING_LP 0x2a6c
#define MC_SEQ_CAS_TIMING_LP 0x2a70
#define MC_SEQ_MISC_TIMING_LP 0x2a74
#define MC_SEQ_MISC_TIMING2_LP 0x2a78
#define MC_SEQ_WR_CTL_D0_LP 0x2a7c
#define MC_SEQ_WR_CTL_D1_LP 0x2a80
#define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
#define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
#define MC_PMG_CMD_MRS 0x2aac
#define MC_SEQ_RD_CTL_D0_LP 0x2b1c
#define MC_SEQ_RD_CTL_D1_LP 0x2b20
#define MC_PMG_CMD_MRS1 0x2b44
#define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
#define MC_SEQ_PMG_TIMING_LP 0x2b4c
#define MC_SEQ_WR_CTL_2 0x2b54
#define MC_SEQ_WR_CTL_2_LP 0x2b58
#define MC_PMG_CMD_MRS2 0x2b5c
#define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60
#define MCLK_PWRMGT_CNTL 0x2ba0
# define DLL_SPEED(x) ((x) << 0)
# define DLL_SPEED_MASK (0x1f << 0)
# define DLL_READY (1 << 6)
# define MC_INT_CNTL (1 << 7)
# define MRDCK0_PDNB (1 << 8)
# define MRDCK1_PDNB (1 << 9)
# define MRDCK0_RESET (1 << 16)
# define MRDCK1_RESET (1 << 17)
# define DLL_READY_READ (1 << 24)
#define DLL_CNTL 0x2ba4
# define MRDCK0_BYPASS (1 << 24)
# define MRDCK1_BYPASS (1 << 25)
#define MPLL_FUNC_CNTL 0x2bb4
#define BWCTRL(x) ((x) << 20)
#define BWCTRL_MASK (0xff << 20)
#define MPLL_FUNC_CNTL_1 0x2bb8
#define VCO_MODE(x) ((x) << 0)
#define VCO_MODE_MASK (3 << 0)
#define CLKFRAC(x) ((x) << 4)
#define CLKFRAC_MASK (0xfff << 4)
#define CLKF(x) ((x) << 16)
#define CLKF_MASK (0xfff << 16)
#define MPLL_FUNC_CNTL_2 0x2bbc
#define MPLL_AD_FUNC_CNTL 0x2bc0
#define YCLK_POST_DIV(x) ((x) << 0)
#define YCLK_POST_DIV_MASK (7 << 0)
#define MPLL_DQ_FUNC_CNTL 0x2bc4
#define YCLK_SEL(x) ((x) << 4)
#define YCLK_SEL_MASK (1 << 4)
#define MPLL_SS1 0x2bcc
#define CLKV(x) ((x) << 0)
#define CLKV_MASK (0x3ffffff << 0)
#define MPLL_SS2 0x2bd0
#define CLKS(x) ((x) << 0)
#define CLKS_MASK (0xfff << 0)
#define HDP_HOST_PATH_CNTL 0x2C00
#define HDP_NONSURFACE_BASE 0x2C04
#define HDP_NONSURFACE_INFO 0x2C08
......@@ -470,6 +731,9 @@
# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
# define DC_HPDx_EN (1 << 28)
#define DPG_PIPE_STUTTER_CONTROL 0x6cd4
# define STUTTER_ENABLE (1 << 0)
/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
#define CRTC_STATUS_FRAME_COUNT 0x6e98
......@@ -645,6 +909,24 @@
#define SQC_CACHES 0x8C08
#define SQ_POWER_THROTTLE 0x8e58
#define MIN_POWER(x) ((x) << 0)
#define MIN_POWER_MASK (0x3fff << 0)
#define MIN_POWER_SHIFT 0
#define MAX_POWER(x) ((x) << 16)
#define MAX_POWER_MASK (0x3fff << 16)
#define MAX_POWER_SHIFT 0
#define SQ_POWER_THROTTLE2 0x8e5c
#define MAX_POWER_DELTA(x) ((x) << 0)
#define MAX_POWER_DELTA_MASK (0x3fff << 0)
#define MAX_POWER_DELTA_SHIFT 0
#define STI_SIZE(x) ((x) << 16)
#define STI_SIZE_MASK (0x3ff << 16)
#define STI_SIZE_SHIFT 16
#define LTI_RATIO(x) ((x) << 27)
#define LTI_RATIO_MASK (0xf << 27)
#define LTI_RATIO_SHIFT 27
#define SX_DEBUG_1 0x9060
#define SPI_STATIC_THREAD_MGMT_1 0x90E0
......
drivers/gpu/drm/radeon/sislands_smc.h 0 → 100644
View file @ a9e61410
/*
* Copyright 2013 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef PP_SISLANDS_SMC_H
#define PP_SISLANDS_SMC_H
#include "ppsmc.h"
#pragma pack(push, 1)
#define SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16
struct PP_SIslands_Dpm2PerfLevel
{
uint8_t MaxPS;
uint8_t TgtAct;
uint8_t MaxPS_StepInc;
uint8_t MaxPS_StepDec;
uint8_t PSSamplingTime;
uint8_t NearTDPDec;
uint8_t AboveSafeInc;
uint8_t BelowSafeInc;
uint8_t PSDeltaLimit;
uint8_t PSDeltaWin;
uint16_t PwrEfficiencyRatio;
uint8_t Reserved[4];
};
typedef struct PP_SIslands_Dpm2PerfLevel PP_SIslands_Dpm2PerfLevel;
struct PP_SIslands_DPM2Status
{
uint32_t dpm2Flags;
uint8_t CurrPSkip;
uint8_t CurrPSkipPowerShift;
uint8_t CurrPSkipTDP;
uint8_t CurrPSkipOCP;
uint8_t MaxSPLLIndex;
uint8_t MinSPLLIndex;
uint8_t CurrSPLLIndex;
uint8_t InfSweepMode;
uint8_t InfSweepDir;
uint8_t TDPexceeded;
uint8_t reserved;
uint8_t SwitchDownThreshold;
uint32_t SwitchDownCounter;
uint32_t SysScalingFactor;
};
typedef struct PP_SIslands_DPM2Status PP_SIslands_DPM2Status;
struct PP_SIslands_DPM2Parameters
{
uint32_t TDPLimit;
uint32_t NearTDPLimit;
uint32_t SafePowerLimit;
uint32_t PowerBoostLimit;
uint32_t MinLimitDelta;
};
typedef struct PP_SIslands_DPM2Parameters PP_SIslands_DPM2Parameters;
struct PP_SIslands_PAPMStatus
{
uint32_t EstimatedDGPU_T;
uint32_t EstimatedDGPU_P;
uint32_t EstimatedAPU_T;
uint32_t EstimatedAPU_P;
uint8_t dGPU_T_Limit_Exceeded;
uint8_t reserved[3];
};
typedef struct PP_SIslands_PAPMStatus PP_SIslands_PAPMStatus;
struct PP_SIslands_PAPMParameters
{
uint32_t NearTDPLimitTherm;
uint32_t NearTDPLimitPAPM;
uint32_t PlatformPowerLimit;
uint32_t dGPU_T_Limit;
uint32_t dGPU_T_Warning;
uint32_t dGPU_T_Hysteresis;
};
typedef struct PP_SIslands_PAPMParameters PP_SIslands_PAPMParameters;
struct SISLANDS_SMC_SCLK_VALUE
{
uint32_t vCG_SPLL_FUNC_CNTL;
uint32_t vCG_SPLL_FUNC_CNTL_2;
uint32_t vCG_SPLL_FUNC_CNTL_3;
uint32_t vCG_SPLL_FUNC_CNTL_4;
uint32_t vCG_SPLL_SPREAD_SPECTRUM;
uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;
uint32_t sclk_value;
};
typedef struct SISLANDS_SMC_SCLK_VALUE SISLANDS_SMC_SCLK_VALUE;
struct SISLANDS_SMC_MCLK_VALUE
{
uint32_t vMPLL_FUNC_CNTL;
uint32_t vMPLL_FUNC_CNTL_1;
uint32_t vMPLL_FUNC_CNTL_2;
uint32_t vMPLL_AD_FUNC_CNTL;
uint32_t vMPLL_DQ_FUNC_CNTL;
uint32_t vMCLK_PWRMGT_CNTL;
uint32_t vDLL_CNTL;
uint32_t vMPLL_SS;
uint32_t vMPLL_SS2;
uint32_t mclk_value;
};
typedef struct SISLANDS_SMC_MCLK_VALUE SISLANDS_SMC_MCLK_VALUE;
struct SISLANDS_SMC_VOLTAGE_VALUE
{
uint16_t value;
uint8_t index;
uint8_t phase_settings;
};
typedef struct SISLANDS_SMC_VOLTAGE_VALUE SISLANDS_SMC_VOLTAGE_VALUE;
struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL
{
uint8_t ACIndex;
uint8_t displayWatermark;
uint8_t gen2PCIE;
uint8_t UVDWatermark;
uint8_t VCEWatermark;
uint8_t strobeMode;
uint8_t mcFlags;
uint8_t padding;
uint32_t aT;
uint32_t bSP;
SISLANDS_SMC_SCLK_VALUE sclk;
SISLANDS_SMC_MCLK_VALUE mclk;
SISLANDS_SMC_VOLTAGE_VALUE vddc;
SISLANDS_SMC_VOLTAGE_VALUE mvdd;
SISLANDS_SMC_VOLTAGE_VALUE vddci;
SISLANDS_SMC_VOLTAGE_VALUE std_vddc;
uint8_t hysteresisUp;
uint8_t hysteresisDown;
uint8_t stateFlags;
uint8_t arbRefreshState;
uint32_t SQPowerThrottle;
uint32_t SQPowerThrottle_2;
uint32_t MaxPoweredUpCU;
SISLANDS_SMC_VOLTAGE_VALUE high_temp_vddc;
SISLANDS_SMC_VOLTAGE_VALUE low_temp_vddc;
uint32_t reserved[2];
PP_SIslands_Dpm2PerfLevel dpm2;
};
#define SISLANDS_SMC_STROBE_RATIO 0x0F
#define SISLANDS_SMC_STROBE_ENABLE 0x10
#define SISLANDS_SMC_MC_EDC_RD_FLAG 0x01
#define SISLANDS_SMC_MC_EDC_WR_FLAG 0x02
#define SISLANDS_SMC_MC_RTT_ENABLE 0x04
#define SISLANDS_SMC_MC_STUTTER_EN 0x08
#define SISLANDS_SMC_MC_PG_EN 0x10
typedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL SISLANDS_SMC_HW_PERFORMANCE_LEVEL;
struct SISLANDS_SMC_SWSTATE
{
uint8_t flags;
uint8_t levelCount;
uint8_t padding2;
uint8_t padding3;
SISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[1];
};
typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE;
#define SISLANDS_SMC_VOLTAGEMASK_VDDC 0
#define SISLANDS_SMC_VOLTAGEMASK_MVDD 1
#define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2
#define SISLANDS_SMC_VOLTAGEMASK_MAX 4
struct SISLANDS_SMC_VOLTAGEMASKTABLE
{
uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX];
};
typedef struct SISLANDS_SMC_VOLTAGEMASKTABLE SISLANDS_SMC_VOLTAGEMASKTABLE;
#define SISLANDS_MAX_NO_VREG_STEPS 32
struct SISLANDS_SMC_STATETABLE
{
uint8_t thermalProtectType;
uint8_t systemFlags;
uint8_t maxVDDCIndexInPPTable;
uint8_t extraFlags;
uint32_t lowSMIO[SISLANDS_MAX_NO_VREG_STEPS];
SISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable;
SISLANDS_SMC_VOLTAGEMASKTABLE phaseMaskTable;
PP_SIslands_DPM2Parameters dpm2Params;
SISLANDS_SMC_SWSTATE initialState;
SISLANDS_SMC_SWSTATE ACPIState;
SISLANDS_SMC_SWSTATE ULVState;
SISLANDS_SMC_SWSTATE driverState;
SISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1];
};
typedef struct SISLANDS_SMC_STATETABLE SISLANDS_SMC_STATETABLE;
#define SI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0
#define SI_SMC_SOFT_REGISTER_delay_vreg 0xC
#define SI_SMC_SOFT_REGISTER_delay_acpi 0x28
#define SI_SMC_SOFT_REGISTER_seq_index 0x5C
#define SI_SMC_SOFT_REGISTER_mvdd_chg_time 0x60
#define SI_SMC_SOFT_REGISTER_mclk_switch_lim 0x70
#define SI_SMC_SOFT_REGISTER_watermark_threshold 0x78
#define SI_SMC_SOFT_REGISTER_phase_shedding_delay 0x88
#define SI_SMC_SOFT_REGISTER_ulv_volt_change_delay 0x8C
#define SI_SMC_SOFT_REGISTER_mc_block_delay 0x98
#define SI_SMC_SOFT_REGISTER_ticks_per_us 0xA8
#define SI_SMC_SOFT_REGISTER_crtc_index 0xC4
#define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min 0xC8
#define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max 0xCC
#define SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width 0xF4
#define SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen 0xFC
#define SI_SMC_SOFT_REGISTER_vr_hot_gpio 0x100
#define SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
#define SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 32
#define SMC_SISLANDS_SCALE_I 7
#define SMC_SISLANDS_SCALE_R 12
struct PP_SIslands_CacConfig
{
uint16_t cac_lkge_lut[SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES];
uint32_t lkge_lut_V0;
uint32_t lkge_lut_Vstep;
uint32_t WinTime;
uint32_t R_LL;
uint32_t calculation_repeats;
uint32_t l2numWin_TDP;
uint32_t dc_cac;
uint8_t lts_truncate_n;
uint8_t SHIFT_N;
uint8_t log2_PG_LKG_SCALE;
uint8_t cac_temp;
uint32_t lkge_lut_T0;
uint32_t lkge_lut_Tstep;
};
typedef struct PP_SIslands_CacConfig PP_SIslands_CacConfig;
#define SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE 16
#define SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20
struct SMC_SIslands_MCRegisterAddress
{
uint16_t s0;
uint16_t s1;
};
typedef struct SMC_SIslands_MCRegisterAddress SMC_SIslands_MCRegisterAddress;
struct SMC_SIslands_MCRegisterSet
{
uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
};
typedef struct SMC_SIslands_MCRegisterSet SMC_SIslands_MCRegisterSet;
struct SMC_SIslands_MCRegisters
{
uint8_t last;
uint8_t reserved[3];
SMC_SIslands_MCRegisterAddress address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
SMC_SIslands_MCRegisterSet data[SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT];
};
typedef struct SMC_SIslands_MCRegisters SMC_SIslands_MCRegisters;
struct SMC_SIslands_MCArbDramTimingRegisterSet
{
uint32_t mc_arb_dram_timing;
uint32_t mc_arb_dram_timing2;
uint8_t mc_arb_rfsh_rate;
uint8_t mc_arb_burst_time;
uint8_t padding[2];
};
typedef struct SMC_SIslands_MCArbDramTimingRegisterSet SMC_SIslands_MCArbDramTimingRegisterSet;
struct SMC_SIslands_MCArbDramTimingRegisters
{
uint8_t arb_current;
uint8_t reserved[3];
SMC_SIslands_MCArbDramTimingRegisterSet data[16];
};
typedef struct SMC_SIslands_MCArbDramTimingRegisters SMC_SIslands_MCArbDramTimingRegisters;
struct SMC_SISLANDS_SPLL_DIV_TABLE
{
uint32_t freq[256];
uint32_t ss[256];
};
#define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK 0x01ffffff
#define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0
#define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK 0xfe000000
#define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT 25
#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff
#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT 0
#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK 0xfff00000
#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT 20
typedef struct SMC_SISLANDS_SPLL_DIV_TABLE SMC_SISLANDS_SPLL_DIV_TABLE;
#define SMC_SISLANDS_DTE_MAX_FILTER_STAGES 5
#define SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE 16
struct Smc_SIslands_DTE_Configuration
{
uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
uint32_t K;
uint32_t T0;
uint32_t MaxT;
uint8_t WindowSize;
uint8_t Tdep_count;
uint8_t temp_select;
uint8_t DTE_mode;
uint8_t T_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
uint32_t Tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
uint32_t Tdep_R[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
uint32_t Tthreshold;
};
typedef struct Smc_SIslands_DTE_Configuration Smc_SIslands_DTE_Configuration;
#define SMC_SISLANDS_DTE_STATUS_FLAG_DTE_ON 1
#define SISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x10000
#define SISLANDS_SMC_FIRMWARE_HEADER_version 0x0
#define SISLANDS_SMC_FIRMWARE_HEADER_flags 0x4
#define SISLANDS_SMC_FIRMWARE_HEADER_softRegisters 0xC
#define SISLANDS_SMC_FIRMWARE_HEADER_stateTable 0x10
#define SISLANDS_SMC_FIRMWARE_HEADER_fanTable 0x14
#define SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable 0x18
#define SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable 0x24
#define SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x30
#define SISLANDS_SMC_FIRMWARE_HEADER_spllTable 0x38
#define SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration 0x40
#define SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters 0x48
#pragma pack(pop)
int si_set_smc_sram_address(struct radeon_device *rdev,
u32 smc_address, u32 limit);
int si_copy_bytes_to_smc(struct radeon_device *rdev,
u32 smc_start_address,
const u8 *src, u32 byte_count, u32 limit);
void si_start_smc(struct radeon_device *rdev);
void si_reset_smc(struct radeon_device *rdev);
int si_program_jump_on_start(struct radeon_device *rdev);
void si_stop_smc_clock(struct radeon_device *rdev);
void si_start_smc_clock(struct radeon_device *rdev);
bool si_is_smc_running(struct radeon_device *rdev);
PPSMC_Result si_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);
PPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev);
int si_load_smc_ucode(struct radeon_device *rdev, u32 limit);
int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
u32 *value, u32 limit);
int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
u32 value, u32 limit);
#endif
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