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Commit ab28e96f authored by Rabin Vincent's avatar Rabin Vincent Committed by Jesper Nilsson
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CRIS v32: remove old GPIO and LEDs code 

Since we now have a gpiolib driver, remove this code:

The gpio-etraxfs driver (along with things like gpio-keys-polled for
polling support) replaces the GIO driver implementations in mach-a3 and
mach-fs.  The various generic external chip drivers replace the "virtual
gpio" parts.

The generic gpio-leds driver replaces the LED handling.
Signed-off-by: default avatarRabin Vincent <rabin@rab.in>
Signed-off-by: default avatarJesper Nilsson <jespern@axis.com>
parent 79b863c6
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Showing with 4 additions and 2702 deletions
arch/cris/arch-v32/Kconfig
View file @ ab28e96f
......@@ -10,95 +10,6 @@ config ETRAX_DRAM_VIRTUAL_BASE
depends on ETRAX_ARCH_V32
default "c0000000"
choice
prompt "Nbr of Ethernet LED groups"
depends on ETRAX_ARCH_V32
default ETRAX_NBR_LED_GRP_ONE
help
Select how many Ethernet LED groups that can be used. Usually one per Ethernet
interface is a good choice.
config ETRAX_NBR_LED_GRP_ZERO
bool "Use zero LED groups"
help
Select this if you do not want any Ethernet LEDs.
config ETRAX_NBR_LED_GRP_ONE
bool "Use one LED group"
help
Select this if you want one Ethernet LED group. This LED group
can be used for one or more Ethernet interfaces. However, it is
recommended that each Ethernet interface use a dedicated LED group.
config ETRAX_NBR_LED_GRP_TWO
bool "Use two LED groups"
help
Select this if you want two Ethernet LED groups. This is the
best choice if you have more than one Ethernet interface and
would like to have separate LEDs for the interfaces.
endchoice
config ETRAX_LED_G_NET0
string "Ethernet LED group 0 green LED bit"
depends on ETRAX_ARCH_V32 && (ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO)
default "PA3"
help
Bit to use for the green LED in Ethernet LED group 0.
config ETRAX_LED_R_NET0
string "Ethernet LED group 0 red LED bit"
depends on ETRAX_ARCH_V32 && (ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO)
default "PA4"
help
Bit to use for the red LED in Ethernet LED group 0.
config ETRAX_LED_G_NET1
string "Ethernet group 1 green LED bit"
depends on ETRAX_ARCH_V32 && ETRAX_NBR_LED_GRP_TWO
default ""
help
Bit to use for the green LED in Ethernet LED group 1.
config ETRAX_LED_R_NET1
string "Ethernet group 1 red LED bit"
depends on ETRAX_ARCH_V32 && ETRAX_NBR_LED_GRP_TWO
default ""
help
Bit to use for the red LED in Ethernet LED group 1.
config ETRAX_V32_LED2G
string "Second green LED bit"
depends on ETRAX_ARCH_V32
default "PA5"
help
Bit to use for the first green LED (status LED).
Most Axis products use bit A5 here.
config ETRAX_V32_LED2R
string "Second red LED bit"
depends on ETRAX_ARCH_V32
default "PA6"
help
Bit to use for the first red LED (network LED).
Most Axis products use bit A6 here.
config ETRAX_V32_LED3G
string "Third green LED bit"
depends on ETRAX_ARCH_V32
default "PA7"
help
Bit to use for the first green LED (drive/power LED).
Most Axis products use bit A7 here.
config ETRAX_V32_LED3R
string "Third red LED bit"
depends on ETRAX_ARCH_V32
default "PA7"
help
Bit to use for the first red LED (drive/power LED).
Most Axis products use bit A7 here.
choice
prompt "Kernel GDB port"
depends on ETRAX_KGDB
......
arch/cris/arch-v32/drivers/Kconfig
View file @ ab28e96f
......@@ -149,155 +149,6 @@ config ETRAX_NANDBOOT
Say Y if your boot code, kernel and root file system is in
NAND flash. Say N if they are in NOR flash.
config ETRAX_GPIO
bool "GPIO support"
depends on ETRAX_ARCH_V32
---help---
Enables the ETRAX general port device (major 120, minors 0-4).
You can use this driver to access the general port bits. It supports
these ioctl's:
#include <linux/etraxgpio.h>
fd = open("/dev/gpioa", O_RDWR); // or /dev/gpiob
ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_SETBITS), bits_to_set);
ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_CLRBITS), bits_to_clear);
err = ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_READ_INBITS), &val);
Remember that you need to setup the port directions appropriately in
the General configuration.
config ETRAX_VIRTUAL_GPIO
bool "Virtual GPIO support"
depends on ETRAX_GPIO
help
Enables the virtual Etrax general port device (major 120, minor 6).
It uses an I/O expander for the I2C-bus.
config ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN
int "Virtual GPIO interrupt pin on PA pin"
range 0 7
depends on ETRAX_VIRTUAL_GPIO
help
The pin to use on PA for virtual gpio interrupt.
config ETRAX_PA_CHANGEABLE_DIR
hex "PA user changeable dir mask"
depends on ETRAX_GPIO
default "0x00" if ETRAXFS
default "0x00000000" if !ETRAXFS
help
This is a bitmask with information of what bits in PA that a
user can change direction on using ioctl's.
Bit set = changeable.
You probably want 0 here, but it depends on your hardware.
config ETRAX_PA_CHANGEABLE_BITS
hex "PA user changeable bits mask"
depends on ETRAX_GPIO
default "0x00" if ETRAXFS
default "0x00000000" if !ETRAXFS
help
This is a bitmask with information of what bits in PA
that a user can change the value on using ioctl's.
Bit set = changeable.
config ETRAX_PB_CHANGEABLE_DIR
hex "PB user changeable dir mask"
depends on ETRAX_GPIO
default "0x00000" if ETRAXFS
default "0x00000000" if !ETRAXFS
help
This is a bitmask with information of what bits in PB
that a user can change direction on using ioctl's.
Bit set = changeable.
You probably want 0 here, but it depends on your hardware.
config ETRAX_PB_CHANGEABLE_BITS
hex "PB user changeable bits mask"
depends on ETRAX_GPIO
default "0x00000" if ETRAXFS
default "0x00000000" if !ETRAXFS
help
This is a bitmask with information of what bits in PB
that a user can change the value on using ioctl's.
Bit set = changeable.
config ETRAX_PC_CHANGEABLE_DIR
hex "PC user changeable dir mask"
depends on ETRAX_GPIO
default "0x00000" if ETRAXFS
default "0x00000000" if !ETRAXFS
help
This is a bitmask with information of what bits in PC
that a user can change direction on using ioctl's.
Bit set = changeable.
You probably want 0 here, but it depends on your hardware.
config ETRAX_PC_CHANGEABLE_BITS
hex "PC user changeable bits mask"
depends on ETRAX_GPIO
default "0x00000" if ETRAXFS
default "0x00000000" if !ETRAXFS
help
This is a bitmask with information of what bits in PC
that a user can change the value on using ioctl's.
Bit set = changeable.
config ETRAX_PD_CHANGEABLE_DIR
hex "PD user changeable dir mask"
depends on ETRAX_GPIO && ETRAXFS
default "0x00000"
help
This is a bitmask with information of what bits in PD
that a user can change direction on using ioctl's.
Bit set = changeable.
You probably want 0x00000 here, but it depends on your hardware.
config ETRAX_PD_CHANGEABLE_BITS
hex "PD user changeable bits mask"
depends on ETRAX_GPIO && ETRAXFS
default "0x00000"
help
This is a bitmask (18 bits) with information of what bits in PD
that a user can change the value on using ioctl's.
Bit set = changeable.
config ETRAX_PE_CHANGEABLE_DIR
hex "PE user changeable dir mask"
depends on ETRAX_GPIO && ETRAXFS
default "0x00000"
help
This is a bitmask (18 bits) with information of what bits in PE
that a user can change direction on using ioctl's.
Bit set = changeable.
You probably want 0x00000 here, but it depends on your hardware.
config ETRAX_PE_CHANGEABLE_BITS
hex "PE user changeable bits mask"
depends on ETRAX_GPIO && ETRAXFS
default "0x00000"
help
This is a bitmask (18 bits) with information of what bits in PE
that a user can change the value on using ioctl's.
Bit set = changeable.
config ETRAX_PV_CHANGEABLE_DIR
hex "PV user changeable dir mask"
depends on ETRAX_VIRTUAL_GPIO
default "0x0000"
help
This is a bitmask (16 bits) with information of what bits in PV
that a user can change direction on using ioctl's.
Bit set = changeable.
You probably want 0x0000 here, but it depends on your hardware.
config ETRAX_PV_CHANGEABLE_BITS
hex "PV user changeable bits mask"
depends on ETRAX_VIRTUAL_GPIO
default "0x0000"
help
This is a bitmask (16 bits) with information of what bits in PV
that a user can change the value on using ioctl's.
Bit set = changeable.
config ETRAX_CARDBUS
bool "Cardbus support"
depends on ETRAX_ARCH_V32
......
arch/cris/arch-v32/drivers/mach-a3/Makefile
View file @ ab28e96f
......@@ -3,4 +3,3 @@
#
obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o
obj-$(CONFIG_ETRAX_GPIO) += gpio.o
arch/cris/arch-v32/drivers/mach-a3/gpio.c deleted 100644 → 0
View file @ 79b863c6
/*
* Artec-3 general port I/O device
*
* Copyright (c) 2007 Axis Communications AB
*
* Authors: Bjorn Wesen (initial version)
* Ola Knutsson (LED handling)
* Johan Adolfsson (read/set directions, write, port G,
* port to ETRAX FS.
* Ricard Wanderlof (PWM for Artpec-3)
*
*/
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/ioport.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/poll.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/mutex.h>
#include <asm/etraxgpio.h>
#include <hwregs/reg_map.h>
#include <hwregs/reg_rdwr.h>
#include <hwregs/gio_defs.h>
#include <hwregs/intr_vect_defs.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <mach/pinmux.h>
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
#include "../i2c.h"
#define VIRT_I2C_ADDR 0x40
#endif
/* The following gio ports on ARTPEC-3 is available:
* pa 32 bits
* pb 32 bits
* pc 16 bits
* each port has a rw_px_dout, r_px_din and rw_px_oe register.
*/
#define GPIO_MAJOR 120 /* experimental MAJOR number */
#define I2C_INTERRUPT_BITS 0x300 /* i2c0_done and i2c1_done bits */
#define D(x)
#if 0
static int dp_cnt;
#define DP(x) \
do { \
dp_cnt++; \
if (dp_cnt % 1000 == 0) \
x; \
} while (0)
#else
#define DP(x)
#endif
static DEFINE_MUTEX(gpio_mutex);
static char gpio_name[] = "etrax gpio";
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
static int virtual_gpio_ioctl(struct file *file, unsigned int cmd,
unsigned long arg);
#endif
static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
static ssize_t gpio_write(struct file *file, const char __user *buf,
size_t count, loff_t *off);
static int gpio_open(struct inode *inode, struct file *filp);
static int gpio_release(struct inode *inode, struct file *filp);
static unsigned int gpio_poll(struct file *filp,
struct poll_table_struct *wait);
/* private data per open() of this driver */
struct gpio_private {
struct gpio_private *next;
/* The IO_CFG_WRITE_MODE_VALUE only support 8 bits: */
unsigned char clk_mask;
unsigned char data_mask;
unsigned char write_msb;
unsigned char pad1;
/* These fields are generic */
unsigned long highalarm, lowalarm;
wait_queue_head_t alarm_wq;
int minor;
};
static void gpio_set_alarm(struct gpio_private *priv);
static int gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
static int gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd,
unsigned long arg);
/* linked list of alarms to check for */
static struct gpio_private *alarmlist;
static int wanted_interrupts;
static DEFINE_SPINLOCK(gpio_lock);
#define NUM_PORTS (GPIO_MINOR_LAST+1)
#define GIO_REG_RD_ADDR(reg) \
(unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
#define GIO_REG_WR_ADDR(reg) \
(unsigned long *)(regi_gio + REG_WR_ADDR_gio_##reg)
static unsigned long led_dummy;
static unsigned long port_d_dummy; /* Only input on Artpec-3 */
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
static unsigned long port_e_dummy; /* Non existent on Artpec-3 */
static unsigned long virtual_dummy;
static unsigned long virtual_rw_pv_oe = CONFIG_ETRAX_DEF_GIO_PV_OE;
static unsigned short cached_virtual_gpio_read;
#endif
static unsigned long *data_out[NUM_PORTS] = {
GIO_REG_WR_ADDR(rw_pa_dout),
GIO_REG_WR_ADDR(rw_pb_dout),
&led_dummy,
GIO_REG_WR_ADDR(rw_pc_dout),
&port_d_dummy,
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
&port_e_dummy,
&virtual_dummy,
#endif
};
static unsigned long *data_in[NUM_PORTS] = {
GIO_REG_RD_ADDR(r_pa_din),
GIO_REG_RD_ADDR(r_pb_din),
&led_dummy,
GIO_REG_RD_ADDR(r_pc_din),
GIO_REG_RD_ADDR(r_pd_din),
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
&port_e_dummy,
&virtual_dummy,
#endif
};
static unsigned long changeable_dir[NUM_PORTS] = {
CONFIG_ETRAX_PA_CHANGEABLE_DIR,
CONFIG_ETRAX_PB_CHANGEABLE_DIR,
0,
CONFIG_ETRAX_PC_CHANGEABLE_DIR,
0,
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
0,
CONFIG_ETRAX_PV_CHANGEABLE_DIR,
#endif
};
static unsigned long changeable_bits[NUM_PORTS] = {
CONFIG_ETRAX_PA_CHANGEABLE_BITS,
CONFIG_ETRAX_PB_CHANGEABLE_BITS,
0,
CONFIG_ETRAX_PC_CHANGEABLE_BITS,
0,
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
0,
CONFIG_ETRAX_PV_CHANGEABLE_BITS,
#endif
};
static unsigned long *dir_oe[NUM_PORTS] = {
GIO_REG_WR_ADDR(rw_pa_oe),
GIO_REG_WR_ADDR(rw_pb_oe),
&led_dummy,
GIO_REG_WR_ADDR(rw_pc_oe),
&port_d_dummy,
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
&port_e_dummy,
&virtual_rw_pv_oe,
#endif
};
static void gpio_set_alarm(struct gpio_private *priv)
{
int bit;
int intr_cfg;
int mask;
int pins;
unsigned long flags;
spin_lock_irqsave(&gpio_lock, flags);
intr_cfg = REG_RD_INT(gio, regi_gio, rw_intr_cfg);
pins = REG_RD_INT(gio, regi_gio, rw_intr_pins);
mask = REG_RD_INT(gio, regi_gio, rw_intr_mask) & I2C_INTERRUPT_BITS;
for (bit = 0; bit < 32; bit++) {
int intr = bit % 8;
int pin = bit / 8;
if (priv->minor < GPIO_MINOR_LEDS)
pin += priv->minor * 4;
else
pin += (priv->minor - 1) * 4;
if (priv->highalarm & (1<<bit)) {
intr_cfg |= (regk_gio_hi << (intr * 3));
mask |= 1 << intr;
wanted_interrupts = mask & 0xff;
pins |= pin << (intr * 4);
} else if (priv->lowalarm & (1<<bit)) {
intr_cfg |= (regk_gio_lo << (intr * 3));
mask |= 1 << intr;
wanted_interrupts = mask & 0xff;
pins |= pin << (intr * 4);
}
}
REG_WR_INT(gio, regi_gio, rw_intr_cfg, intr_cfg);
REG_WR_INT(gio, regi_gio, rw_intr_pins, pins);
REG_WR_INT(gio, regi_gio, rw_intr_mask, mask);
spin_unlock_irqrestore(&gpio_lock, flags);
}
static unsigned int gpio_poll(struct file *file, struct poll_table_struct *wait)
{
unsigned int mask = 0;
struct gpio_private *priv = file->private_data;
unsigned long data;
unsigned long tmp;
if (priv->minor >= GPIO_MINOR_PWM0 &&
priv->minor <= GPIO_MINOR_LAST_PWM)
return 0;
poll_wait(file, &priv->alarm_wq, wait);
if (priv->minor <= GPIO_MINOR_D) {
data = readl(data_in[priv->minor]);
REG_WR_INT(gio, regi_gio, rw_ack_intr, wanted_interrupts);
tmp = REG_RD_INT(gio, regi_gio, rw_intr_mask);
tmp &= I2C_INTERRUPT_BITS;
tmp |= wanted_interrupts;
REG_WR_INT(gio, regi_gio, rw_intr_mask, tmp);
} else
return 0;
if ((data & priv->highalarm) || (~data & priv->lowalarm))
mask = POLLIN|POLLRDNORM;
DP(printk(KERN_DEBUG "gpio_poll ready: mask 0x%08X\n", mask));
return mask;
}
static irqreturn_t gpio_interrupt(int irq, void *dev_id)
{
reg_gio_rw_intr_mask intr_mask;
reg_gio_r_masked_intr masked_intr;
reg_gio_rw_ack_intr ack_intr;
unsigned long flags;
unsigned long tmp;
unsigned long tmp2;
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
unsigned char enable_gpiov_ack = 0;
#endif
/* Find what PA interrupts are active */
masked_intr = REG_RD(gio, regi_gio, r_masked_intr);
tmp = REG_TYPE_CONV(unsigned long, reg_gio_r_masked_intr, masked_intr);
/* Find those that we have enabled */
spin_lock_irqsave(&gpio_lock, flags);
tmp &= wanted_interrupts;
spin_unlock_irqrestore(&gpio_lock, flags);
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
/* Something changed on virtual GPIO. Interrupt is acked by
* reading the device.
*/
if (tmp & (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN)) {
i2c_read(VIRT_I2C_ADDR, (void *)&cached_virtual_gpio_read,
sizeof(cached_virtual_gpio_read));
enable_gpiov_ack = 1;
}
#endif
/* Ack them */
ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp);
REG_WR(gio, regi_gio, rw_ack_intr, ack_intr);
/* Disable those interrupts.. */
intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask);
tmp2 &= ~tmp;
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
/* Do not disable interrupt on virtual GPIO. Changes on virtual
* pins are only noticed by an interrupt.
*/
if (enable_gpiov_ack)
tmp2 |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
#endif
intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2);
REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
return IRQ_RETVAL(tmp);
}
static void gpio_write_bit(unsigned long *port, unsigned char data, int bit,
unsigned char clk_mask, unsigned char data_mask)
{
unsigned long shadow = readl(port) & ~clk_mask;
writel(shadow, port);
if (data & 1 << bit)
shadow |= data_mask;
else
shadow &= ~data_mask;
writel(shadow, port);
/* For FPGA: min 5.0ns (DCC) before CCLK high */
shadow |= clk_mask;
writel(shadow, port);
}
static void gpio_write_byte(struct gpio_private *priv, unsigned long *port,
unsigned char data)
{
int i;
if (priv->write_msb)
for (i = 7; i >= 0; i--)
gpio_write_bit(port, data, i, priv->clk_mask,
priv->data_mask);
else
for (i = 0; i <= 7; i++)
gpio_write_bit(port, data, i, priv->clk_mask,
priv->data_mask);
}
static ssize_t gpio_write(struct file *file, const char __user *buf,
size_t count, loff_t *off)
{
struct gpio_private *priv = file->private_data;
unsigned long flags;
ssize_t retval = count;
/* Only bits 0-7 may be used for write operations but allow all
devices except leds... */
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
if (priv->minor == GPIO_MINOR_V)
return -EFAULT;
#endif
if (priv->minor == GPIO_MINOR_LEDS)
return -EFAULT;
if (priv->minor >= GPIO_MINOR_PWM0 &&
priv->minor <= GPIO_MINOR_LAST_PWM)
return -EFAULT;
if (!access_ok(VERIFY_READ, buf, count))
return -EFAULT;
/* It must have been configured using the IO_CFG_WRITE_MODE */
/* Perhaps a better error code? */
if (priv->clk_mask == 0 || priv->data_mask == 0)
return -EPERM;
D(printk(KERN_DEBUG "gpio_write: %lu to data 0x%02X clk 0x%02X "
"msb: %i\n",
count, priv->data_mask, priv->clk_mask, priv->write_msb));
spin_lock_irqsave(&gpio_lock, flags);
while (count--)
gpio_write_byte(priv, data_out[priv->minor], *buf++);
spin_unlock_irqrestore(&gpio_lock, flags);
return retval;
}
static int gpio_open(struct inode *inode, struct file *filp)
{
struct gpio_private *priv;
int p = iminor(inode);
if (p > GPIO_MINOR_LAST_PWM ||
(p > GPIO_MINOR_LAST && p < GPIO_MINOR_PWM0))
return -EINVAL;
priv = kmalloc(sizeof(struct gpio_private), GFP_KERNEL);
if (!priv)
return -ENOMEM;
mutex_lock(&gpio_mutex);
memset(priv, 0, sizeof(*priv));
priv->minor = p;
filp->private_data = priv;
/* initialize the io/alarm struct, not for PWM ports though */
if (p <= GPIO_MINOR_LAST) {
priv->clk_mask = 0;
priv->data_mask = 0;
priv->highalarm = 0;
priv->lowalarm = 0;
init_waitqueue_head(&priv->alarm_wq);
/* link it into our alarmlist */
spin_lock_irq(&gpio_lock);
priv->next = alarmlist;
alarmlist = priv;
spin_unlock_irq(&gpio_lock);
}
mutex_unlock(&gpio_mutex);
return 0;
}
static int gpio_release(struct inode *inode, struct file *filp)
{
struct gpio_private *p;
struct gpio_private *todel;
/* local copies while updating them: */
unsigned long a_high, a_low;
/* prepare to free private structure */
todel = filp->private_data;
/* unlink from alarmlist - only for non-PWM ports though */
if (todel->minor <= GPIO_MINOR_LAST) {
spin_lock_irq(&gpio_lock);
p = alarmlist;
if (p == todel)
alarmlist = todel->next;
else {
while (p->next != todel)
p = p->next;
p->next = todel->next;
}
/* Check if there are still any alarms set */
p = alarmlist;
a_high = 0;
a_low = 0;
while (p) {
if (p->minor == GPIO_MINOR_A) {
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
p->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
#endif
a_high |= p->highalarm;
a_low |= p->lowalarm;
}
p = p->next;
}
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
/* Variable 'a_low' needs to be set here again
* to ensure that interrupt for virtual GPIO is handled.
*/
a_low |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
#endif
spin_unlock_irq(&gpio_lock);
}
kfree(todel);
return 0;
}
/* Main device API. ioctl's to read/set/clear bits, as well as to
* set alarms to wait for using a subsequent select().
*/
inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg)
{
/* Set direction 0=unchanged 1=input,
* return mask with 1=input
*/
unsigned long flags;
unsigned long dir_shadow;
spin_lock_irqsave(&gpio_lock, flags);
dir_shadow = readl(dir_oe[priv->minor]) &
~(arg & changeable_dir[priv->minor]);
writel(dir_shadow, dir_oe[priv->minor]);
spin_unlock_irqrestore(&gpio_lock, flags);
if (priv->minor == GPIO_MINOR_C)
dir_shadow ^= 0xFFFF; /* Only 16 bits */
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
else if (priv->minor == GPIO_MINOR_V)
dir_shadow ^= 0xFFFF; /* Only 16 bits */
#endif
else
dir_shadow ^= 0xFFFFFFFF; /* PA, PB and PD 32 bits */
return dir_shadow;
} /* setget_input */
static inline unsigned long setget_output(struct gpio_private *priv,
unsigned long arg)
{
unsigned long flags;
unsigned long dir_shadow;
spin_lock_irqsave(&gpio_lock, flags);
dir_shadow = readl(dir_oe[priv->minor]) |
(arg & changeable_dir[priv->minor]);
writel(dir_shadow, dir_oe[priv->minor]);
spin_unlock_irqrestore(&gpio_lock, flags);
return dir_shadow;
} /* setget_output */
static long gpio_ioctl_unlocked(struct file *file,
unsigned int cmd, unsigned long arg)
{
unsigned long flags;
unsigned long val;
unsigned long shadow;
struct gpio_private *priv = file->private_data;
if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
return -ENOTTY;
/* Check for special ioctl handlers first */
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
if (priv->minor == GPIO_MINOR_V)
return virtual_gpio_ioctl(file, cmd, arg);
#endif
if (priv->minor == GPIO_MINOR_LEDS)
return gpio_leds_ioctl(cmd, arg);
if (priv->minor >= GPIO_MINOR_PWM0 &&
priv->minor <= GPIO_MINOR_LAST_PWM)
return gpio_pwm_ioctl(priv, cmd, arg);
switch (_IOC_NR(cmd)) {
case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
/* Read the port. */
return readl(data_in[priv->minor]);
case IO_SETBITS:
spin_lock_irqsave(&gpio_lock, flags);
/* Set changeable bits with a 1 in arg. */
shadow = readl(data_out[priv->minor]) |
(arg & changeable_bits[priv->minor]);
writel(shadow, data_out[priv->minor]);
spin_unlock_irqrestore(&gpio_lock, flags);
break;
case IO_CLRBITS:
spin_lock_irqsave(&gpio_lock, flags);
/* Clear changeable bits with a 1 in arg. */
shadow = readl(data_out[priv->minor]) &
~(arg & changeable_bits[priv->minor]);
writel(shadow, data_out[priv->minor]);
spin_unlock_irqrestore(&gpio_lock, flags);
break;
case IO_HIGHALARM:
/* Set alarm when bits with 1 in arg go high. */
priv->highalarm |= arg;
gpio_set_alarm(priv);
break;
case IO_LOWALARM:
/* Set alarm when bits with 1 in arg go low. */
priv->lowalarm |= arg;
gpio_set_alarm(priv);
break;
case IO_CLRALARM:
/* Clear alarm for bits with 1 in arg. */
priv->highalarm &= ~arg;
priv->lowalarm &= ~arg;
gpio_set_alarm(priv);
break;
case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
/* Read direction 0=input 1=output */
return readl(dir_oe[priv->minor]);
case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
/* Set direction 0=unchanged 1=input,
* return mask with 1=input
*/
return setget_input(priv, arg);
case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
/* Set direction 0=unchanged 1=output,
* return mask with 1=output
*/
return setget_output(priv, arg);
case IO_CFG_WRITE_MODE:
{
int res = -EPERM;
unsigned long dir_shadow, clk_mask, data_mask, write_msb;
clk_mask = arg & 0xFF;
data_mask = (arg >> 8) & 0xFF;
write_msb = (arg >> 16) & 0x01;
/* Check if we're allowed to change the bits and
* the direction is correct
*/
spin_lock_irqsave(&gpio_lock, flags);
dir_shadow = readl(dir_oe[priv->minor]);
if ((clk_mask & changeable_bits[priv->minor]) &&
(data_mask & changeable_bits[priv->minor]) &&
(clk_mask & dir_shadow) &&
(data_mask & dir_shadow)) {
priv->clk_mask = clk_mask;
priv->data_mask = data_mask;
priv->write_msb = write_msb;
res = 0;
}
spin_unlock_irqrestore(&gpio_lock, flags);
return res;
}
case IO_READ_INBITS:
/* *arg is result of reading the input pins */
val = readl(data_in[priv->minor]);
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
return -EFAULT;
return 0;
case IO_READ_OUTBITS:
/* *arg is result of reading the output shadow */
val = *data_out[priv->minor];
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
return -EFAULT;
break;
case IO_SETGET_INPUT:
/* bits set in *arg is set to input,
* *arg updated with current input pins.
*/
if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
return -EFAULT;
val = setget_input(priv, val);
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
return -EFAULT;
break;
case IO_SETGET_OUTPUT:
/* bits set in *arg is set to output,
* *arg updated with current output pins.
*/
if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
return -EFAULT;
val = setget_output(priv, val);
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
return -EFAULT;
break;
default:
return -EINVAL;
} /* switch */
return 0;
}
static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
long ret;
mutex_lock(&gpio_mutex);
ret = gpio_ioctl_unlocked(file, cmd, arg);
mutex_unlock(&gpio_mutex);
return ret;
}
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
static int virtual_gpio_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
unsigned long flags;
unsigned short val;
unsigned short shadow;
struct gpio_private *priv = file->private_data;
switch (_IOC_NR(cmd)) {
case IO_SETBITS:
spin_lock_irqsave(&gpio_lock, flags);
/* Set changeable bits with a 1 in arg. */
i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
shadow |= ~readl(dir_oe[priv->minor]) |
(arg & changeable_bits[priv->minor]);
i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
spin_unlock_irqrestore(&gpio_lock, flags);
break;
case IO_CLRBITS:
spin_lock_irqsave(&gpio_lock, flags);
/* Clear changeable bits with a 1 in arg. */
i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
shadow |= ~readl(dir_oe[priv->minor]) &
~(arg & changeable_bits[priv->minor]);
i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
spin_unlock_irqrestore(&gpio_lock, flags);
break;
case IO_HIGHALARM:
/* Set alarm when bits with 1 in arg go high. */
priv->highalarm |= arg;
break;
case IO_LOWALARM:
/* Set alarm when bits with 1 in arg go low. */
priv->lowalarm |= arg;
break;
case IO_CLRALARM:
/* Clear alarm for bits with 1 in arg. */
priv->highalarm &= ~arg;
priv->lowalarm &= ~arg;
break;
case IO_CFG_WRITE_MODE:
{
unsigned long dir_shadow;
dir_shadow = readl(dir_oe[priv->minor]);
priv->clk_mask = arg & 0xFF;
priv->data_mask = (arg >> 8) & 0xFF;
priv->write_msb = (arg >> 16) & 0x01;
/* Check if we're allowed to change the bits and
* the direction is correct
*/
if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
(priv->data_mask & changeable_bits[priv->minor]) &&
(priv->clk_mask & dir_shadow) &&
(priv->data_mask & dir_shadow))) {
priv->clk_mask = 0;
priv->data_mask = 0;
return -EPERM;
}
break;
}
case IO_READ_INBITS:
/* *arg is result of reading the input pins */
val = cached_virtual_gpio_read & ~readl(dir_oe[priv->minor]);
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
return -EFAULT;
return 0;
case IO_READ_OUTBITS:
/* *arg is result of reading the output shadow */
i2c_read(VIRT_I2C_ADDR, (void *)&val, sizeof(val));
val &= readl(dir_oe[priv->minor]);
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
return -EFAULT;
break;
case IO_SETGET_INPUT:
{
/* bits set in *arg is set to input,
* *arg updated with current input pins.
*/
unsigned short input_mask = ~readl(dir_oe[priv->minor]);
if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
return -EFAULT;
val = setget_input(priv, val);
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
return -EFAULT;
if ((input_mask & val) != input_mask) {
/* Input pins changed. All ports desired as input
* should be set to logic 1.
*/
unsigned short change = input_mask ^ val;
i2c_read(VIRT_I2C_ADDR, (void *)&shadow,
sizeof(shadow));
shadow &= ~change;
shadow |= val;
i2c_write(VIRT_I2C_ADDR, (void *)&shadow,
sizeof(shadow));
}
break;
}
case IO_SETGET_OUTPUT:
/* bits set in *arg is set to output,
* *arg updated with current output pins.
*/
if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
return -EFAULT;
val = setget_output(priv, val);
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
return -EFAULT;
break;
default:
return -EINVAL;
} /* switch */
return 0;
}
#endif /* CONFIG_ETRAX_VIRTUAL_GPIO */
static int gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
{
unsigned char green;
unsigned char red;
switch (_IOC_NR(cmd)) {
case IO_LEDACTIVE_SET:
green = ((unsigned char) arg) & 1;
red = (((unsigned char) arg) >> 1) & 1;
CRIS_LED_ACTIVE_SET_G(green);
CRIS_LED_ACTIVE_SET_R(red);
break;
default:
return -EINVAL;
} /* switch */
return 0;
}
static int gpio_pwm_set_mode(unsigned long arg, int pwm_port)
{
int pinmux_pwm = pinmux_pwm0 + pwm_port;
int mode;
reg_gio_rw_pwm0_ctrl rw_pwm_ctrl = {
.ccd_val = 0,
.ccd_override = regk_gio_no,
.mode = regk_gio_no
};
int allocstatus;
if (get_user(mode, &((struct io_pwm_set_mode *) arg)->mode))
return -EFAULT;
rw_pwm_ctrl.mode = mode;
if (mode != PWM_OFF)
allocstatus = crisv32_pinmux_alloc_fixed(pinmux_pwm);
else
allocstatus = crisv32_pinmux_dealloc_fixed(pinmux_pwm);
if (allocstatus)
return allocstatus;
REG_WRITE(reg_gio_rw_pwm0_ctrl, REG_ADDR(gio, regi_gio, rw_pwm0_ctrl) +
12 * pwm_port, rw_pwm_ctrl);
return 0;
}
static int gpio_pwm_set_period(unsigned long arg, int pwm_port)
{
struct io_pwm_set_period periods;
reg_gio_rw_pwm0_var rw_pwm_widths;
if (copy_from_user(&periods, (void __user *)arg, sizeof(periods)))
return -EFAULT;
if (periods.lo > 8191 || periods.hi > 8191)
return -EINVAL;
rw_pwm_widths.lo = periods.lo;
rw_pwm_widths.hi = periods.hi;
REG_WRITE(reg_gio_rw_pwm0_var, REG_ADDR(gio, regi_gio, rw_pwm0_var) +
12 * pwm_port, rw_pwm_widths);
return 0;
}
static int gpio_pwm_set_duty(unsigned long arg, int pwm_port)
{
unsigned int duty;
reg_gio_rw_pwm0_data rw_pwm_duty;
if (get_user(duty, &((struct io_pwm_set_duty *) arg)->duty))
return -EFAULT;
if (duty > 255)
return -EINVAL;
rw_pwm_duty.data = duty;
REG_WRITE(reg_gio_rw_pwm0_data, REG_ADDR(gio, regi_gio, rw_pwm0_data) +
12 * pwm_port, rw_pwm_duty);
return 0;
}
static int gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd,
unsigned long arg)
{
int pwm_port = priv->minor - GPIO_MINOR_PWM0;
switch (_IOC_NR(cmd)) {
case IO_PWM_SET_MODE:
return gpio_pwm_set_mode(arg, pwm_port);
case IO_PWM_SET_PERIOD:
return gpio_pwm_set_period(arg, pwm_port);
case IO_PWM_SET_DUTY:
return gpio_pwm_set_duty(arg, pwm_port);
default:
return -EINVAL;
}
return 0;
}
static const struct file_operations gpio_fops = {
.owner = THIS_MODULE,
.poll = gpio_poll,
.unlocked_ioctl = gpio_ioctl,
.write = gpio_write,
.open = gpio_open,
.release = gpio_release,
.llseek = noop_llseek,
};
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
static void __init virtual_gpio_init(void)
{
reg_gio_rw_intr_cfg intr_cfg;
reg_gio_rw_intr_mask intr_mask;
unsigned short shadow;
shadow = ~virtual_rw_pv_oe; /* Input ports should be set to logic 1 */
shadow |= CONFIG_ETRAX_DEF_GIO_PV_OUT;
i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
/* Set interrupt mask and on what state the interrupt shall trigger.
* For virtual gpio the interrupt shall trigger on logic '0'.
*/
intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
switch (CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN) {
case 0:
intr_cfg.pa0 = regk_gio_lo;
intr_mask.pa0 = regk_gio_yes;
break;
case 1:
intr_cfg.pa1 = regk_gio_lo;
intr_mask.pa1 = regk_gio_yes;
break;
case 2:
intr_cfg.pa2 = regk_gio_lo;
intr_mask.pa2 = regk_gio_yes;
break;
case 3:
intr_cfg.pa3 = regk_gio_lo;
intr_mask.pa3 = regk_gio_yes;
break;
case 4:
intr_cfg.pa4 = regk_gio_lo;
intr_mask.pa4 = regk_gio_yes;
break;
case 5:
intr_cfg.pa5 = regk_gio_lo;
intr_mask.pa5 = regk_gio_yes;
break;
case 6:
intr_cfg.pa6 = regk_gio_lo;
intr_mask.pa6 = regk_gio_yes;
break;
case 7:
intr_cfg.pa7 = regk_gio_lo;
intr_mask.pa7 = regk_gio_yes;
break;
}
REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
}
#endif
/* main driver initialization routine, called from mem.c */
static int __init gpio_init(void)
{
int res, res2;
printk(KERN_INFO "ETRAX FS GPIO driver v2.7, (c) 2003-2008 "
"Axis Communications AB\n");
/* do the formalities */
res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
if (res < 0) {
printk(KERN_ERR "gpio: couldn't get a major number.\n");
return res;
}
/* Clear all leds */
CRIS_LED_NETWORK_GRP0_SET(0);
CRIS_LED_NETWORK_GRP1_SET(0);
CRIS_LED_ACTIVE_SET(0);
CRIS_LED_DISK_READ(0);
CRIS_LED_DISK_WRITE(0);
res2 = request_irq(GIO_INTR_VECT, gpio_interrupt,
IRQF_SHARED, "gpio", &alarmlist);
if (res2) {
printk(KERN_ERR "err: irq for gpio\n");
return res2;
}
/* No IRQs by default. */
REG_WR_INT(gio, regi_gio, rw_intr_pins, 0);
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
virtual_gpio_init();
#endif
return res;
}
/* this makes sure that gpio_init is called during kernel boot */
module_init(gpio_init);
arch/cris/arch-v32/drivers/mach-fs/Makefile
View file @ ab28e96f
......@@ -3,4 +3,3 @@
#
obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o
obj-$(CONFIG_ETRAX_GPIO) += gpio.o
arch/cris/arch-v32/drivers/mach-fs/gpio.c deleted 100644 → 0
View file @ 79b863c6
/*
* ETRAX CRISv32 general port I/O device
*
* Copyright (c) 1999-2006 Axis Communications AB
*
* Authors: Bjorn Wesen (initial version)
* Ola Knutsson (LED handling)
* Johan Adolfsson (read/set directions, write, port G,
* port to ETRAX FS.
*
*/
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/ioport.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/poll.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/mutex.h>
#include <asm/etraxgpio.h>
#include <hwregs/reg_map.h>
#include <hwregs/reg_rdwr.h>
#include <hwregs/gio_defs.h>
#include <hwregs/intr_vect_defs.h>
#include <asm/io.h>
#include <asm/irq.h>
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
#include "../i2c.h"
#define VIRT_I2C_ADDR 0x40
#endif
/* The following gio ports on ETRAX FS is available:
* pa 8 bits, supports interrupts off, hi, low, set, posedge, negedge anyedge
* pb 18 bits
* pc 18 bits
* pd 18 bits
* pe 18 bits
* each port has a rw_px_dout, r_px_din and rw_px_oe register.
*/
#define GPIO_MAJOR 120 /* experimental MAJOR number */
#define D(x)
#if 0
static int dp_cnt;
#define DP(x) \
do { \
dp_cnt++; \
if (dp_cnt % 1000 == 0) \
x; \
} while (0)
#else
#define DP(x)
#endif
static DEFINE_MUTEX(gpio_mutex);
static char gpio_name[] = "etrax gpio";
#if 0
static wait_queue_head_t *gpio_wq;
#endif
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
static int virtual_gpio_ioctl(struct file *file, unsigned int cmd,
unsigned long arg);
#endif
static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
static ssize_t gpio_write(struct file *file, const char *buf, size_t count,
loff_t *off);
static int gpio_open(struct inode *inode, struct file *filp);
static int gpio_release(struct inode *inode, struct file *filp);
static unsigned int gpio_poll(struct file *filp,
struct poll_table_struct *wait);
/* private data per open() of this driver */
struct gpio_private {
struct gpio_private *next;
/* The IO_CFG_WRITE_MODE_VALUE only support 8 bits: */
unsigned char clk_mask;
unsigned char data_mask;
unsigned char write_msb;
unsigned char pad1;
/* These fields are generic */
unsigned long highalarm, lowalarm;
wait_queue_head_t alarm_wq;
int minor;
};
/* linked list of alarms to check for */
static struct gpio_private *alarmlist;
static int gpio_some_alarms; /* Set if someone uses alarm */
static unsigned long gpio_pa_high_alarms;
static unsigned long gpio_pa_low_alarms;
static DEFINE_SPINLOCK(alarm_lock);
#define NUM_PORTS (GPIO_MINOR_LAST+1)
#define GIO_REG_RD_ADDR(reg) \
(volatile unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
#define GIO_REG_WR_ADDR(reg) \
(volatile unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
unsigned long led_dummy;
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
static unsigned long virtual_dummy;
static unsigned long virtual_rw_pv_oe = CONFIG_ETRAX_DEF_GIO_PV_OE;
static unsigned short cached_virtual_gpio_read;
#endif
static volatile unsigned long *data_out[NUM_PORTS] = {
GIO_REG_WR_ADDR(rw_pa_dout),
GIO_REG_WR_ADDR(rw_pb_dout),
&led_dummy,
GIO_REG_WR_ADDR(rw_pc_dout),
GIO_REG_WR_ADDR(rw_pd_dout),
GIO_REG_WR_ADDR(rw_pe_dout),
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
&virtual_dummy,
#endif
};
static volatile unsigned long *data_in[NUM_PORTS] = {
GIO_REG_RD_ADDR(r_pa_din),
GIO_REG_RD_ADDR(r_pb_din),
&led_dummy,
GIO_REG_RD_ADDR(r_pc_din),
GIO_REG_RD_ADDR(r_pd_din),
GIO_REG_RD_ADDR(r_pe_din),
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
&virtual_dummy,
#endif
};
static unsigned long changeable_dir[NUM_PORTS] = {
CONFIG_ETRAX_PA_CHANGEABLE_DIR,
CONFIG_ETRAX_PB_CHANGEABLE_DIR,
0,
CONFIG_ETRAX_PC_CHANGEABLE_DIR,
CONFIG_ETRAX_PD_CHANGEABLE_DIR,
CONFIG_ETRAX_PE_CHANGEABLE_DIR,
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
CONFIG_ETRAX_PV_CHANGEABLE_DIR,
#endif
};
static unsigned long changeable_bits[NUM_PORTS] = {
CONFIG_ETRAX_PA_CHANGEABLE_BITS,
CONFIG_ETRAX_PB_CHANGEABLE_BITS,
0,
CONFIG_ETRAX_PC_CHANGEABLE_BITS,
CONFIG_ETRAX_PD_CHANGEABLE_BITS,
CONFIG_ETRAX_PE_CHANGEABLE_BITS,
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
CONFIG_ETRAX_PV_CHANGEABLE_BITS,
#endif
};
static volatile unsigned long *dir_oe[NUM_PORTS] = {
GIO_REG_WR_ADDR(rw_pa_oe),
GIO_REG_WR_ADDR(rw_pb_oe),
&led_dummy,
GIO_REG_WR_ADDR(rw_pc_oe),
GIO_REG_WR_ADDR(rw_pd_oe),
GIO_REG_WR_ADDR(rw_pe_oe),
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
&virtual_rw_pv_oe,
#endif
};
static unsigned int gpio_poll(struct file *file, struct poll_table_struct *wait)
{
unsigned int mask = 0;
struct gpio_private *priv = file->private_data;
unsigned long data;
poll_wait(file, &priv->alarm_wq, wait);
if (priv->minor == GPIO_MINOR_A) {
reg_gio_rw_intr_cfg intr_cfg;
unsigned long tmp;
unsigned long flags;
local_irq_save(flags);
data = REG_TYPE_CONV(unsigned long, reg_gio_r_pa_din,
REG_RD(gio, regi_gio, r_pa_din));
/* PA has support for interrupt
* lets activate high for those low and with highalarm set
*/
intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
tmp = ~data & priv->highalarm & 0xFF;
if (tmp & (1 << 0))
intr_cfg.pa0 = regk_gio_hi;
if (tmp & (1 << 1))
intr_cfg.pa1 = regk_gio_hi;
if (tmp & (1 << 2))
intr_cfg.pa2 = regk_gio_hi;
if (tmp & (1 << 3))
intr_cfg.pa3 = regk_gio_hi;
if (tmp & (1 << 4))
intr_cfg.pa4 = regk_gio_hi;
if (tmp & (1 << 5))
intr_cfg.pa5 = regk_gio_hi;
if (tmp & (1 << 6))
intr_cfg.pa6 = regk_gio_hi;
if (tmp & (1 << 7))
intr_cfg.pa7 = regk_gio_hi;
/*
* lets activate low for those high and with lowalarm set
*/
tmp = data & priv->lowalarm & 0xFF;
if (tmp & (1 << 0))
intr_cfg.pa0 = regk_gio_lo;
if (tmp & (1 << 1))
intr_cfg.pa1 = regk_gio_lo;
if (tmp & (1 << 2))
intr_cfg.pa2 = regk_gio_lo;
if (tmp & (1 << 3))
intr_cfg.pa3 = regk_gio_lo;
if (tmp & (1 << 4))
intr_cfg.pa4 = regk_gio_lo;
if (tmp & (1 << 5))
intr_cfg.pa5 = regk_gio_lo;
if (tmp & (1 << 6))
intr_cfg.pa6 = regk_gio_lo;
if (tmp & (1 << 7))
intr_cfg.pa7 = regk_gio_lo;
REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
local_irq_restore(flags);
} else if (priv->minor <= GPIO_MINOR_E)
data = *data_in[priv->minor];
else
return 0;
if ((data & priv->highalarm) || (~data & priv->lowalarm))
mask = POLLIN|POLLRDNORM;
DP(printk(KERN_DEBUG "gpio_poll ready: mask 0x%08X\n", mask));
return mask;
}
int etrax_gpio_wake_up_check(void)
{
struct gpio_private *priv;
unsigned long data = 0;
unsigned long flags;
int ret = 0;
spin_lock_irqsave(&alarm_lock, flags);
priv = alarmlist;
while (priv) {
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
if (priv->minor == GPIO_MINOR_V)
data = (unsigned long)cached_virtual_gpio_read;
else {
data = *data_in[priv->minor];
if (priv->minor == GPIO_MINOR_A)
priv->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
}
#else
data = *data_in[priv->minor];
#endif
if ((data & priv->highalarm) ||
(~data & priv->lowalarm)) {
DP(printk(KERN_DEBUG
"etrax_gpio_wake_up_check %i\n", priv->minor));
wake_up_interruptible(&priv->alarm_wq);
ret = 1;
}
priv = priv->next;
}
spin_unlock_irqrestore(&alarm_lock, flags);
return ret;
}
static irqreturn_t
gpio_poll_timer_interrupt(int irq, void *dev_id)
{
if (gpio_some_alarms)
return IRQ_RETVAL(etrax_gpio_wake_up_check());
return IRQ_NONE;
}
static irqreturn_t
gpio_pa_interrupt(int irq, void *dev_id)
{
reg_gio_rw_intr_mask intr_mask;
reg_gio_r_masked_intr masked_intr;
reg_gio_rw_ack_intr ack_intr;
unsigned long tmp;
unsigned long tmp2;
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
unsigned char enable_gpiov_ack = 0;
#endif
/* Find what PA interrupts are active */
masked_intr = REG_RD(gio, regi_gio, r_masked_intr);
tmp = REG_TYPE_CONV(unsigned long, reg_gio_r_masked_intr, masked_intr);
/* Find those that we have enabled */
spin_lock(&alarm_lock);
tmp &= (gpio_pa_high_alarms | gpio_pa_low_alarms);
spin_unlock(&alarm_lock);
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
/* Something changed on virtual GPIO. Interrupt is acked by
* reading the device.
*/
if (tmp & (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN)) {
i2c_read(VIRT_I2C_ADDR, (void *)&cached_virtual_gpio_read,
sizeof(cached_virtual_gpio_read));
enable_gpiov_ack = 1;
}
#endif
/* Ack them */
ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp);
REG_WR(gio, regi_gio, rw_ack_intr, ack_intr);
/* Disable those interrupts.. */
intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask);
tmp2 &= ~tmp;
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
/* Do not disable interrupt on virtual GPIO. Changes on virtual
* pins are only noticed by an interrupt.
*/
if (enable_gpiov_ack)
tmp2 |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
#endif
intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2);
REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
if (gpio_some_alarms)
return IRQ_RETVAL(etrax_gpio_wake_up_check());
return IRQ_NONE;
}
static ssize_t gpio_write(struct file *file, const char *buf, size_t count,
loff_t *off)
{
struct gpio_private *priv = file->private_data;
unsigned char data, clk_mask, data_mask, write_msb;
unsigned long flags;
unsigned long shadow;
volatile unsigned long *port;
ssize_t retval = count;
/* Only bits 0-7 may be used for write operations but allow all
devices except leds... */
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
if (priv->minor == GPIO_MINOR_V)
return -EFAULT;
#endif
if (priv->minor == GPIO_MINOR_LEDS)
return -EFAULT;
if (!access_ok(VERIFY_READ, buf, count))
return -EFAULT;
clk_mask = priv->clk_mask;
data_mask = priv->data_mask;
/* It must have been configured using the IO_CFG_WRITE_MODE */
/* Perhaps a better error code? */
if (clk_mask == 0 || data_mask == 0)
return -EPERM;
write_msb = priv->write_msb;
D(printk(KERN_DEBUG "gpio_write: %lu to data 0x%02X clk 0x%02X "
"msb: %i\n", count, data_mask, clk_mask, write_msb));
port = data_out[priv->minor];
while (count--) {
int i;
data = *buf++;
if (priv->write_msb) {
for (i = 7; i >= 0; i--) {
local_irq_save(flags);
shadow = *port;
*port = shadow &= ~clk_mask;
if (data & 1<<i)
*port = shadow |= data_mask;
else
*port = shadow &= ~data_mask;
/* For FPGA: min 5.0ns (DCC) before CCLK high */
*port = shadow |= clk_mask;
local_irq_restore(flags);
}
} else {
for (i = 0; i <= 7; i++) {
local_irq_save(flags);
shadow = *port;
*port = shadow &= ~clk_mask;
if (data & 1<<i)
*port = shadow |= data_mask;
else
*port = shadow &= ~data_mask;
/* For FPGA: min 5.0ns (DCC) before CCLK high */
*port = shadow |= clk_mask;
local_irq_restore(flags);
}
}
}
return retval;
}
static int
gpio_open(struct inode *inode, struct file *filp)
{
struct gpio_private *priv;
int p = iminor(inode);
if (p > GPIO_MINOR_LAST)
return -EINVAL;
priv = kzalloc(sizeof(struct gpio_private), GFP_KERNEL);
if (!priv)
return -ENOMEM;
mutex_lock(&gpio_mutex);
priv->minor = p;
/* initialize the io/alarm struct */
priv->clk_mask = 0;
priv->data_mask = 0;
priv->highalarm = 0;
priv->lowalarm = 0;
init_waitqueue_head(&priv->alarm_wq);
filp->private_data = (void *)priv;
/* link it into our alarmlist */
spin_lock_irq(&alarm_lock);
priv->next = alarmlist;
alarmlist = priv;
spin_unlock_irq(&alarm_lock);
mutex_unlock(&gpio_mutex);
return 0;
}
static int
gpio_release(struct inode *inode, struct file *filp)
{
struct gpio_private *p;
struct gpio_private *todel;
/* local copies while updating them: */
unsigned long a_high, a_low;
unsigned long some_alarms;
/* unlink from alarmlist and free the private structure */
spin_lock_irq(&alarm_lock);
p = alarmlist;
todel = filp->private_data;
if (p == todel) {
alarmlist = todel->next;
} else {
while (p->next != todel)
p = p->next;
p->next = todel->next;
}
kfree(todel);
/* Check if there are still any alarms set */
p = alarmlist;
some_alarms = 0;
a_high = 0;
a_low = 0;
while (p) {
if (p->minor == GPIO_MINOR_A) {
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
p->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
#endif
a_high |= p->highalarm;
a_low |= p->lowalarm;
}
if (p->highalarm | p->lowalarm)
some_alarms = 1;
p = p->next;
}
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
/* Variables 'some_alarms' and 'a_low' needs to be set here again
* to ensure that interrupt for virtual GPIO is handled.
*/
some_alarms = 1;
a_low |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
#endif
gpio_some_alarms = some_alarms;
gpio_pa_high_alarms = a_high;
gpio_pa_low_alarms = a_low;
spin_unlock_irq(&alarm_lock);
return 0;
}
/* Main device API. ioctl's to read/set/clear bits, as well as to
* set alarms to wait for using a subsequent select().
*/
inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg)
{
/* Set direction 0=unchanged 1=input,
* return mask with 1=input
*/
unsigned long flags;
unsigned long dir_shadow;
local_irq_save(flags);
dir_shadow = *dir_oe[priv->minor];
dir_shadow &= ~(arg & changeable_dir[priv->minor]);
*dir_oe[priv->minor] = dir_shadow;
local_irq_restore(flags);
if (priv->minor == GPIO_MINOR_A)
dir_shadow ^= 0xFF; /* Only 8 bits */
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
else if (priv->minor == GPIO_MINOR_V)
dir_shadow ^= 0xFFFF; /* Only 16 bits */
#endif
else
dir_shadow ^= 0x3FFFF; /* Only 18 bits */
return dir_shadow;
} /* setget_input */
inline unsigned long setget_output(struct gpio_private *priv, unsigned long arg)
{
unsigned long flags;
unsigned long dir_shadow;
local_irq_save(flags);
dir_shadow = *dir_oe[priv->minor];
dir_shadow |= (arg & changeable_dir[priv->minor]);
*dir_oe[priv->minor] = dir_shadow;
local_irq_restore(flags);
return dir_shadow;
} /* setget_output */
static int gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
static int
gpio_ioctl_unlocked(struct file *file, unsigned int cmd, unsigned long arg)
{
unsigned long flags;
unsigned long val;
unsigned long shadow;
struct gpio_private *priv = file->private_data;
if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
return -EINVAL;
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
if (priv->minor == GPIO_MINOR_V)
return virtual_gpio_ioctl(file, cmd, arg);
#endif
switch (_IOC_NR(cmd)) {
case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
/* Read the port. */
return *data_in[priv->minor];
break;
case IO_SETBITS:
local_irq_save(flags);
/* Set changeable bits with a 1 in arg. */
shadow = *data_out[priv->minor];
shadow |= (arg & changeable_bits[priv->minor]);
*data_out[priv->minor] = shadow;
local_irq_restore(flags);
break;
case IO_CLRBITS:
local_irq_save(flags);
/* Clear changeable bits with a 1 in arg. */
shadow = *data_out[priv->minor];
shadow &= ~(arg & changeable_bits[priv->minor]);
*data_out[priv->minor] = shadow;
local_irq_restore(flags);
break;
case IO_HIGHALARM:
/* Set alarm when bits with 1 in arg go high. */
priv->highalarm |= arg;
spin_lock_irqsave(&alarm_lock, flags);
gpio_some_alarms = 1;
if (priv->minor == GPIO_MINOR_A)
gpio_pa_high_alarms |= arg;
spin_unlock_irqrestore(&alarm_lock, flags);
break;
case IO_LOWALARM:
/* Set alarm when bits with 1 in arg go low. */
priv->lowalarm |= arg;
spin_lock_irqsave(&alarm_lock, flags);
gpio_some_alarms = 1;
if (priv->minor == GPIO_MINOR_A)
gpio_pa_low_alarms |= arg;
spin_unlock_irqrestore(&alarm_lock, flags);
break;
case IO_CLRALARM:
/* Clear alarm for bits with 1 in arg. */
priv->highalarm &= ~arg;
priv->lowalarm &= ~arg;
spin_lock_irqsave(&alarm_lock, flags);
if (priv->minor == GPIO_MINOR_A) {
if (gpio_pa_high_alarms & arg ||
gpio_pa_low_alarms & arg)
/* Must update the gpio_pa_*alarms masks */
;
}
spin_unlock_irqrestore(&alarm_lock, flags);
break;
case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
/* Read direction 0=input 1=output */
return *dir_oe[priv->minor];
case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
/* Set direction 0=unchanged 1=input,
* return mask with 1=input
*/
return setget_input(priv, arg);
break;
case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
/* Set direction 0=unchanged 1=output,
* return mask with 1=output
*/
return setget_output(priv, arg);
case IO_CFG_WRITE_MODE:
{
unsigned long dir_shadow;
dir_shadow = *dir_oe[priv->minor];
priv->clk_mask = arg & 0xFF;
priv->data_mask = (arg >> 8) & 0xFF;
priv->write_msb = (arg >> 16) & 0x01;
/* Check if we're allowed to change the bits and
* the direction is correct
*/
if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
(priv->data_mask & changeable_bits[priv->minor]) &&
(priv->clk_mask & dir_shadow) &&
(priv->data_mask & dir_shadow))) {
priv->clk_mask = 0;
priv->data_mask = 0;
return -EPERM;
}
break;
}
case IO_READ_INBITS:
/* *arg is result of reading the input pins */
val = *data_in[priv->minor];
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
return -EFAULT;
return 0;
break;
case IO_READ_OUTBITS:
/* *arg is result of reading the output shadow */
val = *data_out[priv->minor];
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
return -EFAULT;
break;
case IO_SETGET_INPUT:
/* bits set in *arg is set to input,
* *arg updated with current input pins.
*/
if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
return -EFAULT;
val = setget_input(priv, val);
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
return -EFAULT;
break;
case IO_SETGET_OUTPUT:
/* bits set in *arg is set to output,
* *arg updated with current output pins.
*/
if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
return -EFAULT;
val = setget_output(priv, val);
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
return -EFAULT;
break;
default:
if (priv->minor == GPIO_MINOR_LEDS)
return gpio_leds_ioctl(cmd, arg);
else
return -EINVAL;
} /* switch */
return 0;
}
static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
long ret;
mutex_lock(&gpio_mutex);
ret = gpio_ioctl_unlocked(file, cmd, arg);
mutex_unlock(&gpio_mutex);
return ret;
}
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
static int
virtual_gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
unsigned long flags;
unsigned short val;
unsigned short shadow;
struct gpio_private *priv = file->private_data;
switch (_IOC_NR(cmd)) {
case IO_SETBITS:
local_irq_save(flags);
/* Set changeable bits with a 1 in arg. */
i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
shadow |= ~*dir_oe[priv->minor];
shadow |= (arg & changeable_bits[priv->minor]);
i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
local_irq_restore(flags);
break;
case IO_CLRBITS:
local_irq_save(flags);
/* Clear changeable bits with a 1 in arg. */
i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
shadow |= ~*dir_oe[priv->minor];
shadow &= ~(arg & changeable_bits[priv->minor]);
i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
local_irq_restore(flags);
break;
case IO_HIGHALARM:
/* Set alarm when bits with 1 in arg go high. */
priv->highalarm |= arg;
spin_lock(&alarm_lock);
gpio_some_alarms = 1;
spin_unlock(&alarm_lock);
break;
case IO_LOWALARM:
/* Set alarm when bits with 1 in arg go low. */
priv->lowalarm |= arg;
spin_lock(&alarm_lock);
gpio_some_alarms = 1;
spin_unlock(&alarm_lock);
break;
case IO_CLRALARM:
/* Clear alarm for bits with 1 in arg. */
priv->highalarm &= ~arg;
priv->lowalarm &= ~arg;
spin_lock(&alarm_lock);
spin_unlock(&alarm_lock);
break;
case IO_CFG_WRITE_MODE:
{
unsigned long dir_shadow;
dir_shadow = *dir_oe[priv->minor];
priv->clk_mask = arg & 0xFF;
priv->data_mask = (arg >> 8) & 0xFF;
priv->write_msb = (arg >> 16) & 0x01;
/* Check if we're allowed to change the bits and
* the direction is correct
*/
if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
(priv->data_mask & changeable_bits[priv->minor]) &&
(priv->clk_mask & dir_shadow) &&
(priv->data_mask & dir_shadow))) {
priv->clk_mask = 0;
priv->data_mask = 0;
return -EPERM;
}
break;
}
case IO_READ_INBITS:
/* *arg is result of reading the input pins */
val = cached_virtual_gpio_read;
val &= ~*dir_oe[priv->minor];
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
return -EFAULT;
return 0;
break;
case IO_READ_OUTBITS:
/* *arg is result of reading the output shadow */
i2c_read(VIRT_I2C_ADDR, (void *)&val, sizeof(val));
val &= *dir_oe[priv->minor];
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
return -EFAULT;
break;
case IO_SETGET_INPUT:
{
/* bits set in *arg is set to input,
* *arg updated with current input pins.
*/
unsigned short input_mask = ~*dir_oe[priv->minor];
if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
return -EFAULT;
val = setget_input(priv, val);
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
return -EFAULT;
if ((input_mask & val) != input_mask) {
/* Input pins changed. All ports desired as input
* should be set to logic 1.
*/
unsigned short change = input_mask ^ val;
i2c_read(VIRT_I2C_ADDR, (void *)&shadow,
sizeof(shadow));
shadow &= ~change;
shadow |= val;
i2c_write(VIRT_I2C_ADDR, (void *)&shadow,
sizeof(shadow));
}
break;
}
case IO_SETGET_OUTPUT:
/* bits set in *arg is set to output,
* *arg updated with current output pins.
*/
if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
return -EFAULT;
val = setget_output(priv, val);
if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
return -EFAULT;
break;
default:
return -EINVAL;
} /* switch */
return 0;
}
#endif /* CONFIG_ETRAX_VIRTUAL_GPIO */
static int
gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
{
unsigned char green;
unsigned char red;
switch (_IOC_NR(cmd)) {
case IO_LEDACTIVE_SET:
green = ((unsigned char) arg) & 1;
red = (((unsigned char) arg) >> 1) & 1;
CRIS_LED_ACTIVE_SET_G(green);
CRIS_LED_ACTIVE_SET_R(red);
break;
default:
return -EINVAL;
} /* switch */
return 0;
}
static const struct file_operations gpio_fops = {
.owner = THIS_MODULE,
.poll = gpio_poll,
.unlocked_ioctl = gpio_ioctl,
.write = gpio_write,
.open = gpio_open,
.release = gpio_release,
.llseek = noop_llseek,
};
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
static void
virtual_gpio_init(void)
{
reg_gio_rw_intr_cfg intr_cfg;
reg_gio_rw_intr_mask intr_mask;
unsigned short shadow;
shadow = ~virtual_rw_pv_oe; /* Input ports should be set to logic 1 */
shadow |= CONFIG_ETRAX_DEF_GIO_PV_OUT;
i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
/* Set interrupt mask and on what state the interrupt shall trigger.
* For virtual gpio the interrupt shall trigger on logic '0'.
*/
intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
switch (CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN) {
case 0:
intr_cfg.pa0 = regk_gio_lo;
intr_mask.pa0 = regk_gio_yes;
break;
case 1:
intr_cfg.pa1 = regk_gio_lo;
intr_mask.pa1 = regk_gio_yes;
break;
case 2:
intr_cfg.pa2 = regk_gio_lo;
intr_mask.pa2 = regk_gio_yes;
break;
case 3:
intr_cfg.pa3 = regk_gio_lo;
intr_mask.pa3 = regk_gio_yes;
break;
case 4:
intr_cfg.pa4 = regk_gio_lo;
intr_mask.pa4 = regk_gio_yes;
break;
case 5:
intr_cfg.pa5 = regk_gio_lo;
intr_mask.pa5 = regk_gio_yes;
break;
case 6:
intr_cfg.pa6 = regk_gio_lo;
intr_mask.pa6 = regk_gio_yes;
break;
case 7:
intr_cfg.pa7 = regk_gio_lo;
intr_mask.pa7 = regk_gio_yes;
break;
}
REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
gpio_pa_low_alarms |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
gpio_some_alarms = 1;
}
#endif
/* main driver initialization routine, called from mem.c */
static __init int
gpio_init(void)
{
int res;
/* do the formalities */
res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
if (res < 0) {
printk(KERN_ERR "gpio: couldn't get a major number.\n");
return res;
}
/* Clear all leds */
CRIS_LED_NETWORK_GRP0_SET(0);
CRIS_LED_NETWORK_GRP1_SET(0);
CRIS_LED_ACTIVE_SET(0);
CRIS_LED_DISK_READ(0);
CRIS_LED_DISK_WRITE(0);
printk(KERN_INFO "ETRAX FS GPIO driver v2.5, (c) 2003-2007 "
"Axis Communications AB\n");
/* We call etrax_gpio_wake_up_check() from timer interrupt */
if (request_irq(TIMER0_INTR_VECT, gpio_poll_timer_interrupt,
IRQF_SHARED, "gpio poll", &alarmlist))
printk(KERN_ERR "timer0 irq for gpio\n");
if (request_irq(GIO_INTR_VECT, gpio_pa_interrupt,
IRQF_SHARED, "gpio PA", &alarmlist))
printk(KERN_ERR "PA irq for gpio\n");
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
virtual_gpio_init();
#endif
return res;
}
/* this makes sure that gpio_init is called during kernel boot */
module_init(gpio_init);
arch/cris/arch-v32/kernel/crisksyms.c
View file @ ab28e96f
......@@ -3,7 +3,6 @@
#include <arch/dma.h>
#include <arch/intmem.h>
#include <mach/pinmux.h>
#include <arch/io.h>
/* Functions for allocating DMA channels */
EXPORT_SYMBOL(crisv32_request_dma);
......@@ -20,8 +19,6 @@ EXPORT_SYMBOL(crisv32_pinmux_alloc);
EXPORT_SYMBOL(crisv32_pinmux_alloc_fixed);
EXPORT_SYMBOL(crisv32_pinmux_dealloc);
EXPORT_SYMBOL(crisv32_pinmux_dealloc_fixed);
EXPORT_SYMBOL(crisv32_io_get_name);
EXPORT_SYMBOL(crisv32_io_get);
/* Functions masking/unmasking interrupts */
EXPORT_SYMBOL(crisv32_mask_irq);
......
arch/cris/arch-v32/mach-a3/Makefile
View file @ ab28e96f
......@@ -2,7 +2,7 @@
# Makefile for the linux kernel.
#
obj-y := dma.o pinmux.o io.o arbiter.o
obj-y := dma.o pinmux.o arbiter.o
clean:
arch/cris/arch-v32/mach-a3/io.c deleted 100644 → 0
View file @ 79b863c6
/*
* Helper functions for I/O pins.
*
* Copyright (c) 2005-2007 Axis Communications AB.
*/
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <asm/io.h>
#include <mach/pinmux.h>
#include <hwregs/gio_defs.h>
struct crisv32_ioport crisv32_ioports[] = {
{
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_oe),
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_dout),
(unsigned long *)REG_ADDR(gio, regi_gio, r_pa_din),
32
},
{
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_oe),
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_dout),
(unsigned long *)REG_ADDR(gio, regi_gio, r_pb_din),
32
},
{
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_oe),
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_dout),
(unsigned long *)REG_ADDR(gio, regi_gio, r_pc_din),
16
},
};
#define NBR_OF_PORTS ARRAY_SIZE(crisv32_ioports)
struct crisv32_iopin crisv32_led_net0_green;
struct crisv32_iopin crisv32_led_net0_red;
struct crisv32_iopin crisv32_led2_green;
struct crisv32_iopin crisv32_led2_red;
struct crisv32_iopin crisv32_led3_green;
struct crisv32_iopin crisv32_led3_red;
/* Dummy port used when green LED and red LED is on the same bit */
static unsigned long io_dummy;
static struct crisv32_ioport dummy_port = {
&io_dummy,
&io_dummy,
&io_dummy,
32
};
static struct crisv32_iopin dummy_led = {
&dummy_port,
0
};
static int __init crisv32_io_init(void)
{
int ret = 0;
u32 i;
/* Locks *should* be dynamically initialized. */
for (i = 0; i < ARRAY_SIZE(crisv32_ioports); i++)
spin_lock_init(&crisv32_ioports[i].lock);
spin_lock_init(&dummy_port.lock);
/* Initialize LEDs */
#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
ret += crisv32_io_get_name(&crisv32_led_net0_green,
CONFIG_ETRAX_LED_G_NET0);
crisv32_io_set_dir(&crisv32_led_net0_green, crisv32_io_dir_out);
if (strcmp(CONFIG_ETRAX_LED_G_NET0, CONFIG_ETRAX_LED_R_NET0)) {
ret += crisv32_io_get_name(&crisv32_led_net0_red,
CONFIG_ETRAX_LED_R_NET0);
crisv32_io_set_dir(&crisv32_led_net0_red, crisv32_io_dir_out);
} else
crisv32_led_net0_red = dummy_led;
#endif
ret += crisv32_io_get_name(&crisv32_led2_green, CONFIG_ETRAX_V32_LED2G);
ret += crisv32_io_get_name(&crisv32_led2_red, CONFIG_ETRAX_V32_LED2R);
ret += crisv32_io_get_name(&crisv32_led3_green, CONFIG_ETRAX_V32_LED3G);
ret += crisv32_io_get_name(&crisv32_led3_red, CONFIG_ETRAX_V32_LED3R);
crisv32_io_set_dir(&crisv32_led2_green, crisv32_io_dir_out);
crisv32_io_set_dir(&crisv32_led2_red, crisv32_io_dir_out);
crisv32_io_set_dir(&crisv32_led3_green, crisv32_io_dir_out);
crisv32_io_set_dir(&crisv32_led3_red, crisv32_io_dir_out);
return ret;
}
__initcall(crisv32_io_init);
int crisv32_io_get(struct crisv32_iopin *iopin,
unsigned int port, unsigned int pin)
{
if (port > NBR_OF_PORTS)
return -EINVAL;
if (port > crisv32_ioports[port].pin_count)
return -EINVAL;
iopin->bit = 1 << pin;
iopin->port = &crisv32_ioports[port];
if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio))
return -EIO;
return 0;
}
int crisv32_io_get_name(struct crisv32_iopin *iopin, const char *name)
{
int port;
int pin;
if (toupper(*name) == 'P')
name++;
if (toupper(*name) < 'A' || toupper(*name) > 'E')
return -EINVAL;
port = toupper(*name) - 'A';
name++;
pin = simple_strtoul(name, NULL, 10);
if (pin < 0 || pin > crisv32_ioports[port].pin_count)
return -EINVAL;
iopin->bit = 1 << pin;
iopin->port = &crisv32_ioports[port];
if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio))
return -EIO;
return 0;
}
#ifdef CONFIG_PCI
/* PCI I/O access stuff */
struct cris_io_operations *cris_iops = NULL;
EXPORT_SYMBOL(cris_iops);
#endif
arch/cris/arch-v32/mach-fs/Makefile
View file @ ab28e96f
......@@ -2,7 +2,7 @@
# Makefile for the linux kernel.
#
obj-y := dma.o pinmux.o io.o arbiter.o
obj-y := dma.o pinmux.o arbiter.o
clean:
arch/cris/arch-v32/mach-fs/io.c deleted 100644 → 0
View file @ 79b863c6
/*
* Helper functions for I/O pins.
*
* Copyright (c) 2004-2007 Axis Communications AB.
*/
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <asm/io.h>
#include <mach/pinmux.h>
#include <hwregs/gio_defs.h>
#ifndef DEBUG
#define DEBUG(x)
#endif
struct crisv32_ioport crisv32_ioports[] = {
{
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_oe),
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_dout),
(unsigned long *)REG_ADDR(gio, regi_gio, r_pa_din),
8
},
{
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_oe),
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_dout),
(unsigned long *)REG_ADDR(gio, regi_gio, r_pb_din),
18
},
{
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_oe),
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_dout),
(unsigned long *)REG_ADDR(gio, regi_gio, r_pc_din),
18
},
{
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pd_oe),
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pd_dout),
(unsigned long *)REG_ADDR(gio, regi_gio, r_pd_din),
18
},
{
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pe_oe),
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pe_dout),
(unsigned long *)REG_ADDR(gio, regi_gio, r_pe_din),
18
}
};
#define NBR_OF_PORTS ARRAY_SIZE(crisv32_ioports)
struct crisv32_iopin crisv32_led_net0_green;
struct crisv32_iopin crisv32_led_net0_red;
struct crisv32_iopin crisv32_led_net1_green;
struct crisv32_iopin crisv32_led_net1_red;
struct crisv32_iopin crisv32_led2_green;
struct crisv32_iopin crisv32_led2_red;
struct crisv32_iopin crisv32_led3_green;
struct crisv32_iopin crisv32_led3_red;
/* Dummy port used when green LED and red LED is on the same bit */
static unsigned long io_dummy;
static struct crisv32_ioport dummy_port = {
&io_dummy,
&io_dummy,
&io_dummy,
18
};
static struct crisv32_iopin dummy_led = {
&dummy_port,
0
};
static int __init crisv32_io_init(void)
{
int ret = 0;
u32 i;
/* Locks *should* be dynamically initialized. */
for (i = 0; i < ARRAY_SIZE(crisv32_ioports); i++)
spin_lock_init(&crisv32_ioports[i].lock);
spin_lock_init(&dummy_port.lock);
/* Initialize LEDs */
#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
ret +=
crisv32_io_get_name(&crisv32_led_net0_green,
CONFIG_ETRAX_LED_G_NET0);
crisv32_io_set_dir(&crisv32_led_net0_green, crisv32_io_dir_out);
if (strcmp(CONFIG_ETRAX_LED_G_NET0, CONFIG_ETRAX_LED_R_NET0)) {
ret +=
crisv32_io_get_name(&crisv32_led_net0_red,
CONFIG_ETRAX_LED_R_NET0);
crisv32_io_set_dir(&crisv32_led_net0_red, crisv32_io_dir_out);
} else
crisv32_led_net0_red = dummy_led;
#endif
#ifdef CONFIG_ETRAX_NBR_LED_GRP_TWO
ret +=
crisv32_io_get_name(&crisv32_led_net1_green,
CONFIG_ETRAX_LED_G_NET1);
crisv32_io_set_dir(&crisv32_led_net1_green, crisv32_io_dir_out);
if (strcmp(CONFIG_ETRAX_LED_G_NET1, CONFIG_ETRAX_LED_R_NET1)) {
crisv32_io_get_name(&crisv32_led_net1_red,
CONFIG_ETRAX_LED_R_NET1);
crisv32_io_set_dir(&crisv32_led_net1_red, crisv32_io_dir_out);
} else
crisv32_led_net1_red = dummy_led;
#endif
ret += crisv32_io_get_name(&crisv32_led2_green, CONFIG_ETRAX_V32_LED2G);
ret += crisv32_io_get_name(&crisv32_led2_red, CONFIG_ETRAX_V32_LED2R);
ret += crisv32_io_get_name(&crisv32_led3_green, CONFIG_ETRAX_V32_LED3G);
ret += crisv32_io_get_name(&crisv32_led3_red, CONFIG_ETRAX_V32_LED3R);
crisv32_io_set_dir(&crisv32_led2_green, crisv32_io_dir_out);
crisv32_io_set_dir(&crisv32_led2_red, crisv32_io_dir_out);
crisv32_io_set_dir(&crisv32_led3_green, crisv32_io_dir_out);
crisv32_io_set_dir(&crisv32_led3_red, crisv32_io_dir_out);
return ret;
}
__initcall(crisv32_io_init);
int crisv32_io_get(struct crisv32_iopin *iopin,
unsigned int port, unsigned int pin)
{
if (port > NBR_OF_PORTS)
return -EINVAL;
if (port > crisv32_ioports[port].pin_count)
return -EINVAL;
iopin->bit = 1 << pin;
iopin->port = &crisv32_ioports[port];
/* Only allocate pinmux gpiopins if port != PORT_A (port 0) */
/* NOTE! crisv32_pinmux_alloc thinks PORT_B is port 0 */
if (port != 0 && crisv32_pinmux_alloc(port - 1, pin, pin, pinmux_gpio))
return -EIO;
DEBUG(printk(KERN_DEBUG "crisv32_io_get: Allocated pin %d on port %d\n",
pin, port));
return 0;
}
int crisv32_io_get_name(struct crisv32_iopin *iopin, const char *name)
{
int port;
int pin;
if (toupper(*name) == 'P')
name++;
if (toupper(*name) < 'A' || toupper(*name) > 'E')
return -EINVAL;
port = toupper(*name) - 'A';
name++;
pin = simple_strtoul(name, NULL, 10);
if (pin < 0 || pin > crisv32_ioports[port].pin_count)
return -EINVAL;
iopin->bit = 1 << pin;
iopin->port = &crisv32_ioports[port];
/* Only allocate pinmux gpiopins if port != PORT_A (port 0) */
/* NOTE! crisv32_pinmux_alloc thinks PORT_B is port 0 */
if (port != 0 && crisv32_pinmux_alloc(port - 1, pin, pin, pinmux_gpio))
return -EIO;
DEBUG(printk(KERN_DEBUG
"crisv32_io_get_name: Allocated pin %d on port %d\n",
pin, port));
return 0;
}
#ifdef CONFIG_PCI
/* PCI I/O access stuff */
struct cris_io_operations *cris_iops = NULL;
EXPORT_SYMBOL(cris_iops);
#endif
arch/cris/include/arch-v32/arch/io.h deleted 100644 → 0
View file @ 79b863c6
#ifndef _ASM_ARCH_CRIS_IO_H
#define _ASM_ARCH_CRIS_IO_H
#include <linux/spinlock.h>
#include <hwregs/reg_map.h>
#include <hwregs/reg_rdwr.h>
#include <hwregs/gio_defs.h>
enum crisv32_io_dir
{
crisv32_io_dir_in = 0,
crisv32_io_dir_out = 1
};
struct crisv32_ioport
{
volatile unsigned long *oe;
volatile unsigned long *data;
volatile unsigned long *data_in;
unsigned int pin_count;
spinlock_t lock;
};
struct crisv32_iopin
{
struct crisv32_ioport* port;
int bit;
};
extern struct crisv32_ioport crisv32_ioports[];
extern struct crisv32_iopin crisv32_led1_green;
extern struct crisv32_iopin crisv32_led1_red;
extern struct crisv32_iopin crisv32_led2_green;
extern struct crisv32_iopin crisv32_led2_red;
extern struct crisv32_iopin crisv32_led3_green;
extern struct crisv32_iopin crisv32_led3_red;
extern struct crisv32_iopin crisv32_led_net0_green;
extern struct crisv32_iopin crisv32_led_net0_red;
extern struct crisv32_iopin crisv32_led_net1_green;
extern struct crisv32_iopin crisv32_led_net1_red;
static inline void crisv32_io_set(struct crisv32_iopin *iopin, int val)
{
unsigned long flags;
spin_lock_irqsave(&iopin->port->lock, flags);
if (iopin->port->data) {
if (val)
*iopin->port->data |= iopin->bit;
else
*iopin->port->data &= ~iopin->bit;
}
spin_unlock_irqrestore(&iopin->port->lock, flags);
}
static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin,
enum crisv32_io_dir dir)
{
unsigned long flags;
spin_lock_irqsave(&iopin->port->lock, flags);
if (iopin->port->oe) {
if (dir == crisv32_io_dir_in)
*iopin->port->oe &= ~iopin->bit;
else
*iopin->port->oe |= iopin->bit;
}
spin_unlock_irqrestore(&iopin->port->lock, flags);
}
static inline int crisv32_io_rd(struct crisv32_iopin* iopin)
{
return ((*iopin->port->data_in & iopin->bit) ? 1 : 0);
}
int crisv32_io_get(struct crisv32_iopin* iopin,
unsigned int port, unsigned int pin);
int crisv32_io_get_name(struct crisv32_iopin* iopin,
const char *name);
#define CRIS_LED_OFF 0x00
#define CRIS_LED_GREEN 0x01
#define CRIS_LED_RED 0x02
#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED)
#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
#define CRIS_LED_NETWORK_GRP0_SET(x) \
do { \
CRIS_LED_NETWORK_GRP0_SET_G((x) & CRIS_LED_GREEN); \
CRIS_LED_NETWORK_GRP0_SET_R((x) & CRIS_LED_RED); \
} while (0)
#else
#define CRIS_LED_NETWORK_GRP0_SET(x) while (0) {}
#endif
#define CRIS_LED_NETWORK_GRP0_SET_G(x) \
crisv32_io_set(&crisv32_led_net0_green, !(x));
#define CRIS_LED_NETWORK_GRP0_SET_R(x) \
crisv32_io_set(&crisv32_led_net0_red, !(x));
#if defined(CONFIG_ETRAX_NBR_LED_GRP_TWO)
#define CRIS_LED_NETWORK_GRP1_SET(x) \
do { \
CRIS_LED_NETWORK_GRP1_SET_G((x) & CRIS_LED_GREEN); \
CRIS_LED_NETWORK_GRP1_SET_R((x) & CRIS_LED_RED); \
} while (0)
#else
#define CRIS_LED_NETWORK_GRP1_SET(x) while (0) {}
#endif
#define CRIS_LED_NETWORK_GRP1_SET_G(x) \
crisv32_io_set(&crisv32_led_net1_green, !(x));
#define CRIS_LED_NETWORK_GRP1_SET_R(x) \
crisv32_io_set(&crisv32_led_net1_red, !(x));
#define CRIS_LED_ACTIVE_SET(x) \
do { \
CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \
CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \
} while (0)
#define CRIS_LED_ACTIVE_SET_G(x) \
crisv32_io_set(&crisv32_led2_green, !(x));
#define CRIS_LED_ACTIVE_SET_R(x) \
crisv32_io_set(&crisv32_led2_red, !(x));
#define CRIS_LED_DISK_WRITE(x) \
do{\
crisv32_io_set(&crisv32_led3_green, !(x)); \
crisv32_io_set(&crisv32_led3_red, !(x)); \
}while(0)
#define CRIS_LED_DISK_READ(x) \
crisv32_io_set(&crisv32_led3_green, !(x));
#endif
arch/cris/include/asm/io.h
View file @ ab28e96f
......@@ -2,7 +2,9 @@
#define _ASM_CRIS_IO_H
#include <asm/page.h> /* for __va, __pa */
#ifdef CONFIG_ETRAX_ARCH_V10
#include <arch/io.h>
#endif
#include <asm-generic/iomap.h>
#include <linux/kernel.h>
......
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