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nexedi
linux
Commits
abbd3f8e
Commit
abbd3f8e
authored
Nov 18, 2011
by
Ben Skeggs
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Plain Diff
drm/nv04/disp: handle dual-link spwg panels without needing quirks
Signed-off-by:
Ben Skeggs
<
bskeggs@redhat.com
>
parent
d4c2c99b
Changes
2
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2 changed files
with
8 additions
and
15 deletions
+8
-15
drivers/gpu/drm/nouveau/nouveau_bios.c
drivers/gpu/drm/nouveau/nouveau_bios.c
+0
-12
drivers/gpu/drm/nouveau/nv04_dfp.c
drivers/gpu/drm/nouveau/nv04_dfp.c
+8
-3
No files found.
drivers/gpu/drm/nouveau/nouveau_bios.c
View file @
abbd3f8e
...
@@ -4304,18 +4304,6 @@ int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, b
...
@@ -4304,18 +4304,6 @@ int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, b
break
;
break
;
}
}
/* Dell Latitude D620 reports a too-high value for the dual-link
* transition freq, causing us to program the panel incorrectly.
*
* It doesn't appear the VBIOS actually uses its transition freq
* (90000kHz), instead it uses the "Number of LVDS channels" field
* out of the panel ID structure (http://www.spwg.org/).
*
* For the moment, a quirk will do :)
*/
if
(
nv_match_device
(
dev
,
0x01d7
,
0x1028
,
0x01c2
))
bios
->
fp
.
duallink_transition_clk
=
80000
;
/* set dual_link flag for EDID case */
/* set dual_link flag for EDID case */
if
(
pxclk
&&
(
chip_version
<
0x25
||
chip_version
>
0x28
))
if
(
pxclk
&&
(
chip_version
<
0x25
||
chip_version
>
0x28
))
bios
->
fp
.
dual_link
=
(
pxclk
>=
bios
->
fp
.
duallink_transition_clk
);
bios
->
fp
.
dual_link
=
(
pxclk
>=
bios
->
fp
.
duallink_transition_clk
);
...
...
drivers/gpu/drm/nouveau/nv04_dfp.c
View file @
abbd3f8e
...
@@ -341,10 +341,15 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
...
@@ -341,10 +341,15 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
output_mode
->
clock
>
165000
)
output_mode
->
clock
>
165000
)
regp
->
fp_control
|=
(
2
<<
24
);
regp
->
fp_control
|=
(
2
<<
24
);
if
(
nv_encoder
->
dcb
->
type
==
OUTPUT_LVDS
)
{
if
(
nv_encoder
->
dcb
->
type
==
OUTPUT_LVDS
)
{
bool
duallink
,
dummy
;
bool
duallink
=
false
,
dummy
;
if
(
nv_connector
->
edid
&&
nv_connector
->
type
==
DCB_CONNECTOR_LVDS_SPWG
)
{
duallink
=
(((
u8
*
)
nv_connector
->
edid
)[
121
]
==
2
);
}
else
{
nouveau_bios_parse_lvds_table
(
dev
,
output_mode
->
clock
,
nouveau_bios_parse_lvds_table
(
dev
,
output_mode
->
clock
,
&
duallink
,
&
dummy
);
&
duallink
,
&
dummy
);
}
if
(
duallink
)
if
(
duallink
)
regp
->
fp_control
|=
(
8
<<
28
);
regp
->
fp_control
|=
(
8
<<
28
);
}
else
}
else
...
...
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