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Commit abfc768d authored by Lior Dotan's avatar Lior Dotan Committed by Greg Kroah-Hartman
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Staging: crystalhd: Remove typedefs from driver 

Remove typedefs from driver
Signed-of-by: default avatarLior Dotan <liodot@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 973267a2
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Showing with 442 additions and 462 deletions
drivers/staging/crystalhd/bc_dts_defs.h
View file @ abfc768d
......@@ -26,12 +26,10 @@
#ifndef _BC_DTS_DEFS_H_
#define _BC_DTS_DEFS_H_
#include "bc_dts_types.h"
/* BIT Mask */
#define BC_BIT(_x) (1 << (_x))
typedef enum _BC_STATUS {
enum BC_STATUS {
BC_STS_SUCCESS = 0,
BC_STS_INV_ARG = 1,
BC_STS_BUSY = 2,
......@@ -62,7 +60,7 @@ typedef enum _BC_STATUS {
/* Must be the last one.*/
BC_STS_ERROR = -1
} BC_STATUS;
};
/*------------------------------------------------------*
* Registry Key Definitions *
......@@ -81,14 +79,14 @@ typedef enum _BC_STATUS {
*
*/
typedef enum _BC_SW_OPTIONS {
enum BC_SW_OPTIONS {
BC_OPT_DOSER_OUT_ENCRYPT = BC_BIT(3),
BC_OPT_LINK_OUT_ENCRYPT = BC_BIT(29),
} BC_SW_OPTIONS;
};
typedef struct _BC_REG_CONFIG{
struct BC_REG_CONFIG{
uint32_t DbgOptions;
} BC_REG_CONFIG;
};
#if defined(__KERNEL__) || defined(__LINUX_USER__)
#else
......@@ -108,7 +106,7 @@ typedef struct _BC_REG_CONFIG{
*/
/* To allow multiple apps to open the device. */
enum _DtsDeviceOpenMode {
enum DtsDeviceOpenMode {
DTS_PLAYBACK_MODE = 0,
DTS_DIAG_MODE,
DTS_MONITOR_MODE,
......@@ -116,7 +114,7 @@ enum _DtsDeviceOpenMode {
};
/* To enable the filter to selectively enable/disable fixes or erratas */
enum _DtsDeviceFixMode {
enum DtsDeviceFixMode {
DTS_LOAD_NEW_FW = BC_BIT(8),
DTS_LOAD_FILE_PLAY_FW = BC_BIT(9),
DTS_DISK_FMT_BD = BC_BIT(10),
......@@ -133,7 +131,7 @@ enum _DtsDeviceFixMode {
#define DTS_DFLT_CLOCK(x) (x<<19)
/* F/W File Version corresponding to S/W Releases */
enum _FW_FILE_VER {
enum FW_FILE_VER {
/* S/W release: 02.04.02 F/W release 2.12.2.0 */
BC_FW_VER_020402 = ((12<<16) | (2<<8) | (0))
};
......@@ -141,7 +139,7 @@ enum _FW_FILE_VER {
/*------------------------------------------------------*
* Stream Types for DtsOpenDecoder() *
*------------------------------------------------------*/
enum _DtsOpenDecStreamTypes {
enum DtsOpenDecStreamTypes {
BC_STREAM_TYPE_ES = 0,
BC_STREAM_TYPE_PES = 1,
BC_STREAM_TYPE_TS = 2,
......@@ -151,7 +149,7 @@ enum _DtsOpenDecStreamTypes {
/*------------------------------------------------------*
* Video Algorithms for DtsSetVideoParams() *
*------------------------------------------------------*/
enum _DtsSetVideoParamsAlgo {
enum DtsSetVideoParamsAlgo {
BC_VID_ALGO_H264 = 0,
BC_VID_ALGO_MPEG2 = 1,
BC_VID_ALGO_VC1 = 4,
......@@ -163,7 +161,7 @@ enum _DtsSetVideoParamsAlgo {
*------------------------------------------------------*/
#define BC_MPEG_VALID_PANSCAN (1)
typedef struct _BC_PIB_EXT_MPEG {
struct BC_PIB_EXT_MPEG {
uint32_t valid;
/* Always valid, defaults to picture size if no
* sequence display extension in the stream. */
......@@ -175,8 +173,7 @@ typedef struct _BC_PIB_EXT_MPEG {
uint32_t offset_count;
int32_t horizontal_offset[3];
int32_t vertical_offset[3];
} BC_PIB_EXT_MPEG;
};
/*------------------------------------------------------*
* H.264 Extension to the PPB *
......@@ -186,7 +183,7 @@ typedef struct _BC_PIB_EXT_MPEG {
#define H264_VALID_SPS_CROP (2)
#define H264_VALID_VUI (4)
typedef struct _BC_PIB_EXT_H264 {
struct BC_PIB_EXT_H264 {
/* 'valid' specifies which fields (or sets of
* fields) below are valid. If the corresponding
* bit in 'valid' is NOT set then that field(s)
......@@ -209,15 +206,14 @@ typedef struct _BC_PIB_EXT_H264 {
/* H264_VALID_VUI */
uint32_t chroma_top;
uint32_t chroma_bottom;
} BC_PIB_EXT_H264;
};
/*------------------------------------------------------*
* VC1 Extension to the PPB *
*------------------------------------------------------*/
#define VC1_VALID_PANSCAN (1)
typedef struct _BC_PIB_EXT_VC1 {
struct BC_PIB_EXT_VC1 {
uint32_t valid;
/* Always valid, defaults to picture size if no
......@@ -231,9 +227,7 @@ typedef struct _BC_PIB_EXT_VC1 {
int32_t ps_vert_offset[4];
int32_t ps_width[4];
int32_t ps_height[4];
} BC_PIB_EXT_VC1;
};
/*------------------------------------------------------*
* Picture Information Block *
......@@ -366,7 +360,7 @@ enum _BC_OUTPUT_FORMAT {
MODE422_UYVY = 0x2,
};
typedef struct _BC_PIC_INFO_BLOCK {
struct BC_PIC_INFO_BLOCK {
/* Common fields. */
uint64_t timeStamp; /* Timestamp */
uint32_t picture_number; /* Ordinal display number */
......@@ -386,18 +380,18 @@ typedef struct _BC_PIC_INFO_BLOCK {
/* Protocol-specific extensions. */
union {
BC_PIB_EXT_H264 h264;
BC_PIB_EXT_MPEG mpeg;
BC_PIB_EXT_VC1 vc1;
struct BC_PIB_EXT_H264 h264;
struct BC_PIB_EXT_MPEG mpeg;
struct BC_PIB_EXT_VC1 vc1;
} other;
} BC_PIC_INFO_BLOCK, *PBC_PIC_INFO_BLOCK;
};
/*------------------------------------------------------*
* ProcOut Info *
*------------------------------------------------------*/
/* Optional flags for ProcOut Interface.*/
enum _POUT_OPTIONAL_IN_FLAGS_{
enum POUT_OPTIONAL_IN_FLAGS_{
/* Flags from App to Device */
BC_POUT_FLAGS_YV12 = 0x01, /* Copy Data in YV12 format */
BC_POUT_FLAGS_STRIDE = 0x02, /* Stride size is valid. */
......@@ -412,17 +406,13 @@ enum _POUT_OPTIONAL_IN_FLAGS_{
BC_POUT_FLAGS_FLD_BOT = 0x80000, /* Bottom Field data */
};
#if defined(__KERNEL__) || defined(__LINUX_USER__)
typedef BC_STATUS(*dts_pout_callback)(void *shnd, uint32_t width, uint32_t height, uint32_t stride, void *pOut);
#else
typedef BC_STATUS(*dts_pout_callback)(void *shnd, uint32_t width, uint32_t height, uint32_t stride, struct _BC_DTS_PROC_OUT *pOut);
#endif
typedef enum BC_STATUS(*dts_pout_callback)(void *shnd, uint32_t width, uint32_t height, uint32_t stride, void *pOut);
/* Line 21 Closed Caption */
/* User Data */
#define MAX_UD_SIZE 1792 /* 1920 - 128 */
typedef struct _BC_DTS_PROC_OUT {
struct BC_DTS_PROC_OUT {
uint8_t *Ybuff; /* Caller Supplied buffer for Y data */
uint32_t YbuffSz; /* Caller Supplied Y buffer size */
uint32_t YBuffDoneSz; /* Transferred Y datasize */
......@@ -436,7 +426,7 @@ typedef struct _BC_DTS_PROC_OUT {
uint32_t discCnt; /* Picture discontinuity count */
BC_PIC_INFO_BLOCK PicInfo; /* Picture Information Block Data */
struct BC_PIC_INFO_BLOCK PicInfo; /* Picture Information Block Data */
/* Line 21 Closed Caption */
/* User Data */
......@@ -450,9 +440,9 @@ typedef struct _BC_DTS_PROC_OUT {
uint8_t bPibEnc; /* PIB encrypted */
uint8_t bRevertScramble;
} BC_DTS_PROC_OUT;
};
typedef struct _BC_DTS_STATUS {
struct BC_DTS_STATUS {
uint8_t ReadyListCount; /* Number of frames in ready list (reported by driver) */
uint8_t FreeListCount; /* Number of frame buffers free. (reported by driver) */
uint8_t PowerStateChange; /* Number of active state power transitions (reported by driver) */
......@@ -479,7 +469,7 @@ typedef struct _BC_DTS_STATUS {
* back from the driver */
uint8_t reserved__[16];
} BC_DTS_STATUS;
};
#define BC_SWAP32(_v) \
((((_v) & 0xFF000000)>>24)| \
......
drivers/staging/crystalhd/bc_dts_glob_lnx.h
View file @ abfc768d
......@@ -58,7 +58,7 @@
* These are SW stack tunable parameters shared
* between the driver and the application.
*/
enum _BC_DTS_GLOBALS {
enum BC_DTS_GLOBALS {
BC_MAX_FW_CMD_BUFF_SZ = 0x40, /* FW passthrough cmd/rsp buffer size */
PCI_CFG_SIZE = 256, /* PCI config size buffer */
BC_IOCTL_DATA_POOL_SIZE = 8, /* BC_IOCTL_DATA Pool size */
......@@ -70,62 +70,62 @@ enum _BC_DTS_GLOBALS {
BC_INFIFO_THRESHOLD = 0x10000,
};
typedef struct _BC_CMD_REG_ACC {
struct BC_CMD_REG_ACC {
uint32_t Offset;
uint32_t Value;
} BC_CMD_REG_ACC;
};
typedef struct _BC_CMD_DEV_MEM {
struct BC_CMD_DEV_MEM {
uint32_t StartOff;
uint32_t NumDwords;
uint32_t Rsrd;
} BC_CMD_DEV_MEM;
};
/* FW Passthrough command structure */
enum _bc_fw_cmd_flags {
enum bc_fw_cmd_flags {
BC_FW_CMD_FLAGS_NONE = 0,
BC_FW_CMD_PIB_QS = 0x01,
};
typedef struct _BC_FW_CMD {
struct BC_FW_CMD {
uint32_t cmd[BC_MAX_FW_CMD_BUFF_SZ];
uint32_t rsp[BC_MAX_FW_CMD_BUFF_SZ];
uint32_t flags;
uint32_t add_data;
} BC_FW_CMD, *PBC_FW_CMD;
};
typedef struct _BC_HW_TYPE {
struct BC_HW_TYPE {
uint16_t PciDevId;
uint16_t PciVenId;
uint8_t HwRev;
uint8_t Align[3];
} BC_HW_TYPE;
};
typedef struct _BC_PCI_CFG {
struct BC_PCI_CFG {
uint32_t Size;
uint32_t Offset;
uint8_t pci_cfg_space[PCI_CFG_SIZE];
} BC_PCI_CFG;
};
typedef struct _BC_VERSION_INFO_ {
struct BC_VERSION_INFO {
uint8_t DriverMajor;
uint8_t DriverMinor;
uint16_t DriverRevision;
} BC_VERSION_INFO;
};
typedef struct _BC_START_RX_CAP_ {
struct BC_START_RX_CAP {
uint32_t Rsrd;
uint32_t StartDeliveryThsh;
uint32_t PauseThsh;
uint32_t ResumeThsh;
} BC_START_RX_CAP;
};
typedef struct _BC_FLUSH_RX_CAP_ {
struct BC_FLUSH_RX_CAP {
uint32_t Rsrd;
uint32_t bDiscardOnly;
} BC_FLUSH_RX_CAP;
};
typedef struct _BC_DTS_STATS {
struct BC_DTS_STATS {
uint8_t drvRLL;
uint8_t drvFLL;
uint8_t eosDetected;
......@@ -154,18 +154,18 @@ typedef struct _BC_DTS_STATS {
uint32_t DrvRepeatedFrms;
uint32_t res1[13];
} BC_DTS_STATS;
};
typedef struct _BC_PROC_INPUT_ {
struct BC_PROC_INPUT {
uint8_t *pDmaBuff;
uint32_t BuffSz;
uint8_t Mapped;
uint8_t Encrypted;
uint8_t Rsrd[2];
uint32_t DramOffset; /* For debug use only */
} BC_PROC_INPUT, *PBC_PROC_INPUT;
};
typedef struct _BC_DEC_YUV_BUFFS {
struct BC_DEC_YUV_BUFFS {
uint32_t b422Mode;
uint8_t *YuvBuff;
uint32_t YuvBuffSz;
......@@ -173,9 +173,9 @@ typedef struct _BC_DEC_YUV_BUFFS {
uint32_t YBuffDoneSz;
uint32_t UVBuffDoneSz;
uint32_t RefCnt;
} BC_DEC_YUV_BUFFS;
};
enum _DECOUT_COMPLETION_FLAGS{
enum DECOUT_COMPLETION_FLAGS{
COMP_FLAG_NO_INFO = 0x00,
COMP_FLAG_FMT_CHANGE = 0x01,
COMP_FLAG_PIB_VALID = 0x02,
......@@ -184,47 +184,47 @@ enum _DECOUT_COMPLETION_FLAGS{
COMP_FLAG_DATA_BOT = 0x10,
};
typedef struct _BC_DEC_OUT_BUFF{
BC_DEC_YUV_BUFFS OutPutBuffs;
BC_PIC_INFO_BLOCK PibInfo;
struct BC_DEC_OUT_BUFF{
struct BC_DEC_YUV_BUFFS OutPutBuffs;
struct BC_PIC_INFO_BLOCK PibInfo;
uint32_t Flags;
uint32_t BadFrCnt;
} BC_DEC_OUT_BUFF;
};
typedef struct _BC_NOTIFY_MODE {
struct BC_NOTIFY_MODE {
uint32_t Mode;
uint32_t Rsvr[3];
} BC_NOTIFY_MODE;
};
typedef struct _BC_CLOCK {
struct BC_CLOCK {
uint32_t clk;
uint32_t Rsvr[3];
} BC_CLOCK;
};
typedef struct _BC_IOCTL_DATA {
BC_STATUS RetSts;
struct BC_IOCTL_DATA {
enum BC_STATUS RetSts;
uint32_t IoctlDataSz;
uint32_t Timeout;
union {
BC_CMD_REG_ACC regAcc;
BC_CMD_DEV_MEM devMem;
BC_FW_CMD fwCmd;
BC_HW_TYPE hwType;
BC_PCI_CFG pciCfg;
BC_VERSION_INFO VerInfo;
BC_PROC_INPUT ProcInput;
BC_DEC_YUV_BUFFS RxBuffs;
BC_DEC_OUT_BUFF DecOutData;
BC_START_RX_CAP RxCap;
BC_FLUSH_RX_CAP FlushRxCap;
BC_DTS_STATS drvStat;
BC_NOTIFY_MODE NotifyMode;
BC_CLOCK clockValue;
struct BC_CMD_REG_ACC regAcc;
struct BC_CMD_DEV_MEM devMem;
struct BC_FW_CMD fwCmd;
struct BC_HW_TYPE hwType;
struct BC_PCI_CFG pciCfg;
struct BC_VERSION_INFO VerInfo;
struct BC_PROC_INPUT ProcInput;
struct BC_DEC_YUV_BUFFS RxBuffs;
struct BC_DEC_OUT_BUFF DecOutData;
struct BC_START_RX_CAP RxCap;
struct BC_FLUSH_RX_CAP FlushRxCap;
struct BC_DTS_STATS drvStat;
struct BC_NOTIFY_MODE NotifyMode;
struct BC_CLOCK clockValue;
} u;
struct _BC_IOCTL_DATA *next;
} BC_IOCTL_DATA;
};
typedef enum _BC_DRV_CMD{
enum BC_DRV_CMD {
DRV_CMD_VERSION = 0, /* Get SW version */
DRV_CMD_GET_HWTYPE, /* Get HW version and type Dozer/Tank */
DRV_CMD_REG_RD, /* Read Device Register */
......@@ -249,12 +249,12 @@ typedef enum _BC_DRV_CMD{
/* MUST be the last one.. */
DRV_CMD_END, /* End of the List.. */
} BC_DRV_CMD;
};
#define BC_IOC_BASE 'b'
#define BC_IOC_VOID _IOC_NONE
#define BC_IOC_IOWR(nr, type) _IOWR(BC_IOC_BASE, nr, type)
#define BC_IOCTL_MB BC_IOCTL_DATA
#define BC_IOCTL_MB struct BC_IOCTL_DATA
#define BCM_IOC_GET_VERSION BC_IOC_IOWR(DRV_CMD_VERSION, BC_IOCTL_MB)
#define BCM_IOC_GET_HWTYPE BC_IOC_IOWR(DRV_CMD_GET_HWTYPE, BC_IOCTL_MB)
......@@ -280,17 +280,16 @@ typedef enum _BC_DRV_CMD{
#define BCM_IOC_END BC_IOC_VOID
/* Wrapper for main IOCTL data */
typedef struct _crystalhd_ioctl_data {
BC_IOCTL_DATA udata; /* IOCTL from App..*/
struct crystalhd_ioctl_data {
struct BC_IOCTL_DATA udata; /* IOCTL from App..*/
uint32_t u_id; /* Driver specific user ID */
uint32_t cmd; /* Cmd ID for driver's use. */
void *add_cdata; /* Additional command specific data..*/
uint32_t add_cdata_sz; /* Additional command specific data size */
struct _crystalhd_ioctl_data *next; /* List/Fifo management */
} crystalhd_ioctl_data;
struct crystalhd_ioctl_data *next; /* List/Fifo management */
};
enum _crystalhd_kmod_ver{
enum crystalhd_kmod_ver{
crystalhd_kmod_major = 0,
crystalhd_kmod_minor = 9,
crystalhd_kmod_rev = 27,
......
drivers/staging/crystalhd/crystalhd_cmds.c
View file @ abfc768d
This diff is collapsed.
drivers/staging/crystalhd/crystalhd_cmds.h
View file @ abfc768d
......@@ -36,7 +36,7 @@
#include "crystalhd_misc.h"
#include "crystalhd_hw.h"
enum _crystalhd_state{
enum crystalhd_state{
BC_LINK_INVALID = 0x00,
BC_LINK_INIT = 0x01,
BC_LINK_CAP_EN = 0x02,
......@@ -66,23 +66,22 @@ struct crystalhd_cmd {
struct crystalhd_hw hw_ctx;
};
typedef BC_STATUS(*crystalhd_cmd_proc)(struct crystalhd_cmd *, crystalhd_ioctl_data *);
typedef enum BC_STATUS(*crystalhd_cmd_proc)(struct crystalhd_cmd *, struct crystalhd_ioctl_data *);
typedef struct _crystalhd_cmd_tbl {
struct crystalhd_cmd_tbl {
uint32_t cmd_id;
const crystalhd_cmd_proc cmd_proc;
uint32_t block_mon;
} crystalhd_cmd_tbl_t;
};
BC_STATUS crystalhd_suspend(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata);
BC_STATUS crystalhd_resume(struct crystalhd_cmd *ctx);
enum BC_STATUS crystalhd_suspend(struct crystalhd_cmd *ctx, struct crystalhd_ioctl_data *idata);
enum BC_STATUS crystalhd_resume(struct crystalhd_cmd *ctx);
crystalhd_cmd_proc crystalhd_get_cmd_proc(struct crystalhd_cmd *ctx, uint32_t cmd,
struct crystalhd_user *uc);
BC_STATUS crystalhd_user_open(struct crystalhd_cmd *ctx, struct crystalhd_user **user_ctx);
BC_STATUS crystalhd_user_close(struct crystalhd_cmd *ctx, struct crystalhd_user *uc);
BC_STATUS crystalhd_setup_cmd_context(struct crystalhd_cmd *ctx, struct crystalhd_adp *adp);
BC_STATUS crystalhd_delete_cmd_context(struct crystalhd_cmd *ctx);
enum BC_STATUS crystalhd_user_open(struct crystalhd_cmd *ctx, struct crystalhd_user **user_ctx);
enum BC_STATUS crystalhd_user_close(struct crystalhd_cmd *ctx, struct crystalhd_user *uc);
enum BC_STATUS crystalhd_setup_cmd_context(struct crystalhd_cmd *ctx, struct crystalhd_adp *adp);
enum BC_STATUS crystalhd_delete_cmd_context(struct crystalhd_cmd *ctx);
bool crystalhd_cmd_interrupt(struct crystalhd_cmd *ctx);
#endif
drivers/staging/crystalhd/crystalhd_fw_if.h
View file @ abfc768d
......@@ -29,21 +29,17 @@
/* TBD: Pull in only required defs into this file.. */
/* User Data Header */
typedef struct user_data {
struct user_data {
struct user_data *next;
uint32_t type;
uint32_t size;
} UD_HDR;
};
/*------------------------------------------------------*
* MPEG Extension to the PPB *
*------------------------------------------------------*/
typedef struct {
struct ppb_mpeg {
uint32_t to_be_defined;
uint32_t valid;
......@@ -61,15 +57,15 @@ typedef struct {
/* MPEG_VALID_USERDATA
User data is in the form of a linked list. */
int32_t userDataSize;
UD_HDR *userData;
struct user_data *userData;
} PPB_MPEG;
};
/*------------------------------------------------------*
* VC1 Extension to the PPB *
*------------------------------------------------------*/
typedef struct {
struct ppb_vc1 {
uint32_t to_be_defined;
uint32_t valid;
......@@ -88,9 +84,9 @@ typedef struct {
/* VC1_VALID_USERDATA
User data is in the form of a linked list. */
int32_t userDataSize;
UD_HDR *userData;
struct user_data *userData;
} PPB_VC1;
};
/*------------------------------------------------------*
* H.264 Extension to the PPB *
......@@ -108,8 +104,8 @@ typedef struct {
/* maximum number of intervals(as many as 256 intervals?) */
#define MAX_FGT_VALUE_INTERVAL (256)
typedef struct FGT_SEI {
struct FGT_SEI *next;
struct fgt_sei {
struct fgt_sei *next;
unsigned char model_values[3][MAX_FGT_VALUE_INTERVAL][MAX_FGT_MODEL_VALUE];
unsigned char upper_bound[3][MAX_FGT_VALUE_INTERVAL];
unsigned char lower_bound[3][MAX_FGT_VALUE_INTERVAL];
......@@ -134,9 +130,9 @@ typedef struct FGT_SEI {
unsigned char num_model_values[3]; /* Number of model values. */
uint16_t repetition_period; /* Repetition period (0-16384) */
} FGT_SEI;
};
typedef struct {
struct ppb_h264 {
/* 'valid' specifies which fields (or sets of
* fields) below are valid. If the corresponding
* bit in 'valid' is NOT set then that field(s)
......@@ -170,14 +166,14 @@ typedef struct {
/* H264_VALID_USER */
uint32_t user_data_size;
UD_HDR *user_data;
struct user_data *user_data;
/* H264 VALID FGT */
FGT_SEI *pfgt;
struct fgt_sei *pfgt;
} PPB_H264;
};
typedef struct {
struct ppb {
/* Common fields. */
uint32_t picture_number; /* Ordinal display number */
uint32_t video_buffer; /* Video (picbuf) number */
......@@ -215,14 +211,14 @@ typedef struct {
/* Protocol-specific extensions. */
union {
PPB_H264 h264;
PPB_MPEG mpeg;
PPB_VC1 vc1;
struct ppb_h264 h264;
struct ppb_mpeg mpeg;
struct ppb_vc1 vc1;
} other;
} PPB;
};
typedef struct {
struct c011_pib {
uint32_t bFormatChange;
uint32_t resolution;
uint32_t channelId;
......@@ -231,13 +227,11 @@ typedef struct {
uint32_t zeroPanscanValid;
uint32_t dramOutBufAddr;
uint32_t yComponent;
PPB ppb;
} C011_PIB;
struct ppb ppb;
};
typedef struct {
struct dec_rsp_channel_start_video {
uint32_t command;
uint32_t sequence;
uint32_t status;
......@@ -251,12 +245,12 @@ typedef struct {
uint32_t transportStreamCaptureAddr;
uint32_t asyncEventQ;
} DecRspChannelStartVideo;
};
#define eCMD_C011_CMD_BASE (0x73763000)
/* host commands */
typedef enum {
enum c011_ts_cmd {
eCMD_TS_GET_NEXT_PIC = 0x7376F100, /* debug get next picture */
eCMD_TS_GET_LAST_PIC = 0x7376F102, /* debug get last pic status */
eCMD_TS_READ_WRITE_MEM = 0x7376F104, /* debug read write memory */
......@@ -364,6 +358,6 @@ typedef enum {
eNOTIFY_C011_ENC_CHAN_EVENT = eCMD_C011_CMD_BASE + 0x210,
} eC011_TS_CMD;
};
#endif
drivers/staging/crystalhd/crystalhd_hw.c
View file @ abfc768d
This diff is collapsed.
drivers/staging/crystalhd/crystalhd_hw.h
View file @ abfc768d
......@@ -109,7 +109,7 @@
#define DecHt_HostSwReset 0x340000
#define BC_DRAM_FW_CFG_ADDR 0x001c2000
typedef union _addr_64_ {
union addr_64 {
struct {
uint32_t low_part;
uint32_t high_part;
......@@ -117,9 +117,9 @@ typedef union _addr_64_ {
uint64_t full_addr;
} addr_64;
};
typedef union _intr_mask_reg_ {
union intr_mask_reg {
struct {
uint32_t mask_tx_done:1;
uint32_t mask_tx_err:1;
......@@ -133,9 +133,9 @@ typedef union _intr_mask_reg_ {
uint32_t whole_reg;
} intr_mask_reg;
};
typedef union _link_misc_perst_deco_ctrl_ {
union link_misc_perst_deco_ctrl {
struct {
uint32_t bcm7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/
uint32_t reserved0:3; /* Reserved.No Effect*/
......@@ -145,9 +145,9 @@ typedef union _link_misc_perst_deco_ctrl_ {
uint32_t whole_reg;
} link_misc_perst_deco_ctrl;
};
typedef union _link_misc_perst_clk_ctrl_ {
union link_misc_perst_clk_ctrl {
struct {
uint32_t sel_alt_clk:1; /* When set, selects a 6.75MHz clock as the source of core_clk */
uint32_t stop_core_clk:1; /* When set, stops the branch of core_clk that is not needed for low power operation */
......@@ -161,10 +161,9 @@ typedef union _link_misc_perst_clk_ctrl_ {
uint32_t whole_reg;
} link_misc_perst_clk_ctrl;
};
typedef union _link_misc_perst_decoder_ctrl_ {
union link_misc_perst_decoder_ctrl {
struct {
uint32_t bcm_7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/
uint32_t res0:3; /* Reserved.No Effect*/
......@@ -174,10 +173,9 @@ typedef union _link_misc_perst_decoder_ctrl_ {
uint32_t whole_reg;
} link_misc_perst_decoder_ctrl;
};
typedef union _desc_low_addr_reg_ {
union desc_low_addr_reg {
struct {
uint32_t list_valid:1;
uint32_t reserved:4;
......@@ -186,9 +184,9 @@ typedef union _desc_low_addr_reg_ {
uint32_t whole_reg;
} desc_low_addr_reg;
};
typedef struct _dma_descriptor_ { /* 8 32-bit values */
struct dma_descriptor { /* 8 32-bit values */
/* 0th u32 */
uint32_t sdram_buff_addr:28; /* bits 0-27: SDRAM Address */
uint32_t res0:4; /* bits 28-31: Reserved */
......@@ -220,24 +218,22 @@ typedef struct _dma_descriptor_ { /* 8 32-bit values */
/* 7th u32 */
uint32_t res8; /* Last 32bits reserved */
} dma_descriptor, *pdma_descriptor;
};
/*
* We will allocate the memory in 4K pages
* the linked list will be a list of 32 byte descriptors.
* The virtual address will determine what should be freed.
*/
typedef struct _dma_desc_mem_ {
pdma_descriptor pdma_desc_start; /* 32-bytes for dma descriptor. should be first element */
struct dma_desc_mem {
struct dma_descriptor *pdma_desc_start; /* 32-bytes for dma descriptor. should be first element */
dma_addr_t phy_addr; /* physical address of each DMA desc */
uint32_t sz;
struct _dma_desc_mem_ *Next; /* points to Next Descriptor in chain */
} dma_desc_mem, *pdma_desc_mem;
};
typedef enum _list_sts_ {
enum list_sts {
sts_free = 0,
/* RX-Y Bits 0:7 */
......@@ -253,30 +249,27 @@ typedef enum _list_sts_ {
rx_y_mask = 0x000000FF,
rx_uv_mask = 0x0000FF00,
};
} list_sts;
typedef struct _tx_dma_pkt_ {
dma_desc_mem desc_mem;
struct tx_dma_pkt {
struct dma_desc_mem desc_mem;
hw_comp_callback call_back;
crystalhd_dio_req *dio_req;
struct crystalhd_dio_req *dio_req;
wait_queue_head_t *cb_event;
uint32_t list_tag;
};
} tx_dma_pkt;
typedef struct _crystalhd_rx_dma_pkt {
dma_desc_mem desc_mem;
crystalhd_dio_req *dio_req;
struct crystalhd_rx_dma_pkt {
struct dma_desc_mem desc_mem;
struct crystalhd_dio_req *dio_req;
uint32_t pkt_tag;
uint32_t flags;
BC_PIC_INFO_BLOCK pib;
struct BC_PIC_INFO_BLOCK pib;
dma_addr_t uv_phy_addr;
struct _crystalhd_rx_dma_pkt *next;
} crystalhd_rx_dma_pkt;
struct crystalhd_rx_dma_pkt *next;
};
struct crystalhd_hw_stats{
struct crystalhd_hw_stats {
uint32_t rx_errors;
uint32_t tx_errors;
uint32_t freeq_count;
......@@ -288,13 +281,13 @@ struct crystalhd_hw_stats{
};
struct crystalhd_hw {
tx_dma_pkt tx_pkt_pool[DMA_ENGINE_CNT];
struct tx_dma_pkt tx_pkt_pool[DMA_ENGINE_CNT];
spinlock_t lock;
uint32_t tx_ioq_tag_seed;
uint32_t tx_list_post_index;
crystalhd_rx_dma_pkt *rx_pkt_pool_head;
struct crystalhd_rx_dma_pkt *rx_pkt_pool_head;
uint32_t rx_pkt_tag_seed;
bool dev_started;
......@@ -306,16 +299,16 @@ struct crystalhd_hw {
uint32_t pib_del_Q_addr;
uint32_t pib_rel_Q_addr;
crystalhd_dioq_t *tx_freeq;
crystalhd_dioq_t *tx_actq;
struct crystalhd_dioq *tx_freeq;
struct crystalhd_dioq *tx_actq;
/* Rx DMA Engine Specific Locks */
spinlock_t rx_lock;
uint32_t rx_list_post_index;
list_sts rx_list_sts[DMA_ENGINE_CNT];
crystalhd_dioq_t *rx_rdyq;
crystalhd_dioq_t *rx_freeq;
crystalhd_dioq_t *rx_actq;
enum list_sts rx_list_sts[DMA_ENGINE_CNT];
struct crystalhd_dioq *rx_rdyq;
struct crystalhd_dioq *rx_freeq;
struct crystalhd_dioq *rx_actq;
uint32_t stop_pending;
/* HW counters.. */
......@@ -364,35 +357,35 @@ struct crystalhd_hw {
/**** API Exposed to the other layers ****/
BC_STATUS crystalhd_download_fw(struct crystalhd_adp *adp,
enum BC_STATUS crystalhd_download_fw(struct crystalhd_adp *adp,
void *buffer, uint32_t sz);
BC_STATUS crystalhd_do_fw_cmd(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd);
enum BC_STATUS crystalhd_do_fw_cmd(struct crystalhd_hw *hw, struct BC_FW_CMD *fw_cmd);
bool crystalhd_hw_interrupt(struct crystalhd_adp *adp, struct crystalhd_hw *hw);
BC_STATUS crystalhd_hw_open(struct crystalhd_hw *, struct crystalhd_adp *);
BC_STATUS crystalhd_hw_close(struct crystalhd_hw *);
BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *);
BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *);
enum BC_STATUS crystalhd_hw_open(struct crystalhd_hw *, struct crystalhd_adp *);
enum BC_STATUS crystalhd_hw_close(struct crystalhd_hw *);
enum BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *);
enum BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *);
BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, crystalhd_dio_req *ioreq,
enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, struct crystalhd_dio_req *ioreq,
hw_comp_callback call_back,
wait_queue_head_t *cb_event,
uint32_t *list_id, uint8_t data_flags);
BC_STATUS crystalhd_hw_pause(struct crystalhd_hw *hw);
BC_STATUS crystalhd_hw_unpause(struct crystalhd_hw *hw);
BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw);
BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, uint32_t list_id);
BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw,
crystalhd_dio_req *ioreq, bool en_post);
BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw,
BC_PIC_INFO_BLOCK *pib,
crystalhd_dio_req **ioreq);
BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw);
BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw);
enum BC_STATUS crystalhd_hw_pause(struct crystalhd_hw *hw);
enum BC_STATUS crystalhd_hw_unpause(struct crystalhd_hw *hw);
enum BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw);
enum BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, uint32_t list_id);
enum BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw,
struct crystalhd_dio_req *ioreq, bool en_post);
enum BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw,
struct BC_PIC_INFO_BLOCK *pib,
struct crystalhd_dio_req **ioreq);
enum BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw);
enum BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw);
void crystalhd_hw_stats(struct crystalhd_hw *hw, struct crystalhd_hw_stats *stats);
/* API to program the core clock on the decoder */
BC_STATUS crystalhd_hw_set_core_clock(struct crystalhd_hw *);
enum BC_STATUS crystalhd_hw_set_core_clock(struct crystalhd_hw *);
#endif
drivers/staging/crystalhd/crystalhd_lnx.c
View file @ abfc768d
......@@ -73,10 +73,10 @@ static int chd_dec_disable_int(struct crystalhd_adp *adp)
return 0;
}
crystalhd_ioctl_data *chd_dec_alloc_iodata(struct crystalhd_adp *adp, bool isr)
struct crystalhd_ioctl_data *chd_dec_alloc_iodata(struct crystalhd_adp *adp, bool isr)
{
unsigned long flags = 0;
crystalhd_ioctl_data *temp;
struct crystalhd_ioctl_data *temp;
if (!adp)
return NULL;
......@@ -93,7 +93,7 @@ crystalhd_ioctl_data *chd_dec_alloc_iodata(struct crystalhd_adp *adp, bool isr)
return temp;
}
void chd_dec_free_iodata(struct crystalhd_adp *adp, crystalhd_ioctl_data *iodata,
void chd_dec_free_iodata(struct crystalhd_adp *adp, struct crystalhd_ioctl_data *iodata,
bool isr)
{
unsigned long flags = 0;
......@@ -129,7 +129,7 @@ static inline int crystalhd_user_data(unsigned long ud, void *dr, int size, int
return rc;
}
static int chd_dec_fetch_cdata(struct crystalhd_adp *adp, crystalhd_ioctl_data *io,
static int chd_dec_fetch_cdata(struct crystalhd_adp *adp, struct crystalhd_ioctl_data *io,
uint32_t m_sz, unsigned long ua)
{
unsigned long ua_off;
......@@ -163,7 +163,7 @@ static int chd_dec_fetch_cdata(struct crystalhd_adp *adp, crystalhd_ioctl_data *
}
static int chd_dec_release_cdata(struct crystalhd_adp *adp,
crystalhd_ioctl_data *io, unsigned long ua)
struct crystalhd_ioctl_data *io, unsigned long ua)
{
unsigned long ua_off;
int rc;
......@@ -193,7 +193,7 @@ static int chd_dec_release_cdata(struct crystalhd_adp *adp,
}
static int chd_dec_proc_user_data(struct crystalhd_adp *adp,
crystalhd_ioctl_data *io,
struct crystalhd_ioctl_data *io,
unsigned long ua, int set)
{
int rc;
......@@ -231,8 +231,8 @@ static int chd_dec_api_cmd(struct crystalhd_adp *adp, unsigned long ua,
uint32_t uid, uint32_t cmd, crystalhd_cmd_proc func)
{
int rc;
crystalhd_ioctl_data *temp;
BC_STATUS sts = BC_STS_SUCCESS;
struct crystalhd_ioctl_data *temp;
enum BC_STATUS sts = BC_STS_SUCCESS;
temp = chd_dec_alloc_iodata(adp, 0);
if (!temp) {
......@@ -296,7 +296,7 @@ static int chd_dec_open(struct inode *in, struct file *fd)
{
struct crystalhd_adp *adp = chd_get_adp();
int rc = 0;
BC_STATUS sts = BC_STS_SUCCESS;
enum BC_STATUS sts = BC_STS_SUCCESS;
struct crystalhd_user *uc = NULL;
BCMLOG_ENTER;
......@@ -356,7 +356,7 @@ static const struct file_operations chd_dec_fops = {
static int __devinit chd_dec_init_chdev(struct crystalhd_adp *adp)
{
crystalhd_ioctl_data *temp;
struct crystalhd_ioctl_data *temp;
struct device *dev;
int rc = -ENODEV, i = 0;
......@@ -394,7 +394,7 @@ static int __devinit chd_dec_init_chdev(struct crystalhd_adp *adp)
/* Allocate general purpose ioctl pool. */
for (i = 0; i < CHD_IODATA_POOL_SZ; i++) {
/* FIXME: jarod: why atomic? */
temp = kzalloc(sizeof(crystalhd_ioctl_data), GFP_ATOMIC);
temp = kzalloc(sizeof(struct crystalhd_ioctl_data), GFP_ATOMIC);
if (!temp) {
BCMLOG_ERR("ioctl data pool kzalloc failed\n");
rc = -ENOMEM;
......@@ -418,7 +418,7 @@ static int __devinit chd_dec_init_chdev(struct crystalhd_adp *adp)
static void __devexit chd_dec_release_chdev(struct crystalhd_adp *adp)
{
crystalhd_ioctl_data *temp = NULL;
struct crystalhd_ioctl_data *temp = NULL;
if (!adp)
return;
......@@ -513,7 +513,7 @@ static void __devexit chd_pci_release_mem(struct crystalhd_adp *pinfo)
static void __devexit chd_dec_pci_remove(struct pci_dev *pdev)
{
struct crystalhd_adp *pinfo;
BC_STATUS sts = BC_STS_SUCCESS;
enum BC_STATUS sts = BC_STS_SUCCESS;
BCMLOG_ENTER;
......@@ -543,7 +543,7 @@ static int __devinit chd_dec_pci_probe(struct pci_dev *pdev,
{
struct crystalhd_adp *pinfo;
int rc;
BC_STATUS sts = BC_STS_SUCCESS;
enum BC_STATUS sts = BC_STS_SUCCESS;
BCMLOG(BCMLOG_DBG, "PCI_INFO: Vendor:0x%04x Device:0x%04x "
"s_vendor:0x%04x s_device: 0x%04x\n",
......@@ -623,8 +623,8 @@ static int __devinit chd_dec_pci_probe(struct pci_dev *pdev,
int chd_dec_pci_suspend(struct pci_dev *pdev, pm_message_t state)
{
struct crystalhd_adp *adp;
crystalhd_ioctl_data *temp;
BC_STATUS sts = BC_STS_SUCCESS;
struct crystalhd_ioctl_data *temp;
enum BC_STATUS sts = BC_STS_SUCCESS;
adp = (struct crystalhd_adp *)pci_get_drvdata(pdev);
if (!adp) {
......@@ -657,7 +657,7 @@ int chd_dec_pci_suspend(struct pci_dev *pdev, pm_message_t state)
int chd_dec_pci_resume(struct pci_dev *pdev)
{
struct crystalhd_adp *adp;
BC_STATUS sts = BC_STS_SUCCESS;
enum BC_STATUS sts = BC_STS_SUCCESS;
int rc;
adp = (struct crystalhd_adp *)pci_get_drvdata(pdev);
......
drivers/staging/crystalhd/crystalhd_lnx.h
View file @ abfc768d
......@@ -79,12 +79,12 @@ struct crystalhd_adp {
unsigned int chd_dec_major;
unsigned int cfg_users;
crystalhd_ioctl_data *idata_free_head; /* ioctl data pool */
crystalhd_elem_t *elem_pool_head; /* Queue element pool */
struct crystalhd_ioctl_data *idata_free_head; /* ioctl data pool */
struct crystalhd_elem *elem_pool_head; /* Queue element pool */
struct crystalhd_cmd cmds;
crystalhd_dio_req *ua_map_free_head;
struct crystalhd_dio_req *ua_map_free_head;
struct pci_pool *fill_byte_pool;
};
......
drivers/staging/crystalhd/crystalhd_misc.c
View file @ abfc768d
......@@ -43,15 +43,15 @@ static inline void crystalhd_dram_wr(struct crystalhd_adp *adp, uint32_t mem_off
bc_dec_reg_wr(adp, (0x00380000 | (mem_off & 0x0007FFFF)), val);
}
static inline BC_STATUS bc_chk_dram_range(struct crystalhd_adp *adp, uint32_t start_off, uint32_t cnt)
static inline enum BC_STATUS bc_chk_dram_range(struct crystalhd_adp *adp, uint32_t start_off, uint32_t cnt)
{
return BC_STS_SUCCESS;
}
static crystalhd_dio_req *crystalhd_alloc_dio(struct crystalhd_adp *adp)
static struct crystalhd_dio_req *crystalhd_alloc_dio(struct crystalhd_adp *adp)
{
unsigned long flags = 0;
crystalhd_dio_req *temp = NULL;
struct crystalhd_dio_req *temp = NULL;
if (!adp) {
BCMLOG_ERR("Invalid Arg!!\n");
......@@ -67,7 +67,7 @@ static crystalhd_dio_req *crystalhd_alloc_dio(struct crystalhd_adp *adp)
return temp;
}
static void crystalhd_free_dio(struct crystalhd_adp *adp, crystalhd_dio_req *dio)
static void crystalhd_free_dio(struct crystalhd_adp *adp, struct crystalhd_dio_req *dio)
{
unsigned long flags = 0;
......@@ -83,10 +83,10 @@ static void crystalhd_free_dio(struct crystalhd_adp *adp, crystalhd_dio_req *dio
spin_unlock_irqrestore(&adp->lock, flags);
}
static crystalhd_elem_t *crystalhd_alloc_elem(struct crystalhd_adp *adp)
static struct crystalhd_elem *crystalhd_alloc_elem(struct crystalhd_adp *adp)
{
unsigned long flags = 0;
crystalhd_elem_t *temp = NULL;
struct crystalhd_elem *temp = NULL;
if (!adp)
return temp;
......@@ -100,7 +100,7 @@ static crystalhd_elem_t *crystalhd_alloc_elem(struct crystalhd_adp *adp)
return temp;
}
static void crystalhd_free_elem(struct crystalhd_adp *adp, crystalhd_elem_t *elem)
static void crystalhd_free_elem(struct crystalhd_adp *adp, struct crystalhd_elem *elem)
{
unsigned long flags = 0;
......@@ -230,7 +230,7 @@ void crystalhd_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val)
*
* 7412's Dram read routine.
*/
BC_STATUS crystalhd_mem_rd(struct crystalhd_adp *adp, uint32_t start_off,
enum BC_STATUS crystalhd_mem_rd(struct crystalhd_adp *adp, uint32_t start_off,
uint32_t dw_cnt, uint32_t *rd_buff)
{
uint32_t ix = 0;
......@@ -258,7 +258,7 @@ BC_STATUS crystalhd_mem_rd(struct crystalhd_adp *adp, uint32_t start_off,
*
* 7412's Dram write routine.
*/
BC_STATUS crystalhd_mem_wr(struct crystalhd_adp *adp, uint32_t start_off,
enum BC_STATUS crystalhd_mem_wr(struct crystalhd_adp *adp, uint32_t start_off,
uint32_t dw_cnt, uint32_t *wr_buff)
{
uint32_t ix = 0;
......@@ -286,10 +286,10 @@ BC_STATUS crystalhd_mem_wr(struct crystalhd_adp *adp, uint32_t start_off,
*
* Get value from Link's PCIe config space.
*/
BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *adp, uint32_t off,
enum BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *adp, uint32_t off,
uint32_t len, uint32_t *val)
{
BC_STATUS sts = BC_STS_SUCCESS;
enum BC_STATUS sts = BC_STS_SUCCESS;
int rc = 0;
if (!adp || !val) {
......@@ -331,10 +331,10 @@ BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *adp, uint32_t off,
*
* Set value to Link's PCIe config space.
*/
BC_STATUS crystalhd_pci_cfg_wr(struct crystalhd_adp *adp, uint32_t off,
enum BC_STATUS crystalhd_pci_cfg_wr(struct crystalhd_adp *adp, uint32_t off,
uint32_t len, uint32_t val)
{
BC_STATUS sts = BC_STS_SUCCESS;
enum BC_STATUS sts = BC_STS_SUCCESS;
int rc = 0;
if (!adp || !val) {
......@@ -429,11 +429,11 @@ void bc_kern_dma_free(struct crystalhd_adp *adp, uint32_t sz, void *ka,
* Initialize Generic DIO queue to hold any data. Callback
* will be used to free elements while deleting the queue.
*/
BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *adp,
crystalhd_dioq_t **dioq_hnd,
enum BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *adp,
struct crystalhd_dioq **dioq_hnd,
crystalhd_data_free_cb cb, void *cbctx)
{
crystalhd_dioq_t *dioq = NULL;
struct crystalhd_dioq *dioq = NULL;
if (!adp || !dioq_hnd) {
BCMLOG_ERR("Invalid arg!!\n");
......@@ -446,8 +446,8 @@ BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *adp,
spin_lock_init(&dioq->lock);
dioq->sig = BC_LINK_DIOQ_SIG;
dioq->head = (crystalhd_elem_t *)&dioq->head;
dioq->tail = (crystalhd_elem_t *)&dioq->head;
dioq->head = (struct crystalhd_elem *)&dioq->head;
dioq->tail = (struct crystalhd_elem *)&dioq->head;
crystalhd_create_event(&dioq->event);
dioq->adp = adp;
dioq->data_rel_cb = cb;
......@@ -470,7 +470,7 @@ BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *adp,
* by calling the call back provided during creation.
*
*/
void crystalhd_delete_dioq(struct crystalhd_adp *adp, crystalhd_dioq_t *dioq)
void crystalhd_delete_dioq(struct crystalhd_adp *adp, struct crystalhd_dioq *dioq)
{
void *temp;
......@@ -498,11 +498,11 @@ void crystalhd_delete_dioq(struct crystalhd_adp *adp, crystalhd_dioq_t *dioq)
*
* Insert new element to Q tail.
*/
BC_STATUS crystalhd_dioq_add(crystalhd_dioq_t *ioq, void *data,
enum BC_STATUS crystalhd_dioq_add(struct crystalhd_dioq *ioq, void *data,
bool wake, uint32_t tag)
{
unsigned long flags = 0;
crystalhd_elem_t *tmp;
struct crystalhd_elem *tmp;
if (!ioq || (ioq->sig != BC_LINK_DIOQ_SIG) || !data) {
BCMLOG_ERR("Invalid arg!!\n");
......@@ -518,7 +518,7 @@ BC_STATUS crystalhd_dioq_add(crystalhd_dioq_t *ioq, void *data,
tmp->data = data;
tmp->tag = tag;
spin_lock_irqsave(&ioq->lock, flags);
tmp->flink = (crystalhd_elem_t *)&ioq->head;
tmp->flink = (struct crystalhd_elem *)&ioq->head;
tmp->blink = ioq->tail;
tmp->flink->blink = tmp;
tmp->blink->flink = tmp;
......@@ -540,11 +540,11 @@ BC_STATUS crystalhd_dioq_add(crystalhd_dioq_t *ioq, void *data,
*
* Remove an element from Queue.
*/
void *crystalhd_dioq_fetch(crystalhd_dioq_t *ioq)
void *crystalhd_dioq_fetch(struct crystalhd_dioq *ioq)
{
unsigned long flags = 0;
crystalhd_elem_t *tmp;
crystalhd_elem_t *ret = NULL;
struct crystalhd_elem *tmp;
struct crystalhd_elem *ret = NULL;
void *data = NULL;
if (!ioq || (ioq->sig != BC_LINK_DIOQ_SIG)) {
......@@ -554,7 +554,7 @@ void *crystalhd_dioq_fetch(crystalhd_dioq_t *ioq)
spin_lock_irqsave(&ioq->lock, flags);
tmp = ioq->head;
if (tmp != (crystalhd_elem_t *)&ioq->head) {
if (tmp != (struct crystalhd_elem *)&ioq->head) {
ret = tmp;
tmp->flink->blink = tmp->blink;
tmp->blink->flink = tmp->flink;
......@@ -578,11 +578,11 @@ void *crystalhd_dioq_fetch(crystalhd_dioq_t *ioq)
*
* Search TAG and remove the element.
*/
void *crystalhd_dioq_find_and_fetch(crystalhd_dioq_t *ioq, uint32_t tag)
void *crystalhd_dioq_find_and_fetch(struct crystalhd_dioq *ioq, uint32_t tag)
{
unsigned long flags = 0;
crystalhd_elem_t *tmp;
crystalhd_elem_t *ret = NULL;
struct crystalhd_elem *tmp;
struct crystalhd_elem *ret = NULL;
void *data = NULL;
if (!ioq || (ioq->sig != BC_LINK_DIOQ_SIG)) {
......@@ -592,7 +592,7 @@ void *crystalhd_dioq_find_and_fetch(crystalhd_dioq_t *ioq, uint32_t tag)
spin_lock_irqsave(&ioq->lock, flags);
tmp = ioq->head;
while (tmp != (crystalhd_elem_t *)&ioq->head) {
while (tmp != (struct crystalhd_elem *)&ioq->head) {
if (tmp->tag == tag) {
ret = tmp;
tmp->flink->blink = tmp->blink;
......@@ -623,7 +623,7 @@ void *crystalhd_dioq_find_and_fetch(crystalhd_dioq_t *ioq, uint32_t tag)
* Return element from head if Q is not empty. Wait for new element
* if Q is empty for Timeout seconds.
*/
void *crystalhd_dioq_fetch_wait(crystalhd_dioq_t *ioq, uint32_t to_secs,
void *crystalhd_dioq_fetch_wait(struct crystalhd_dioq *ioq, uint32_t to_secs,
uint32_t *sig_pend)
{
unsigned long flags = 0;
......@@ -673,12 +673,12 @@ void *crystalhd_dioq_fetch_wait(crystalhd_dioq_t *ioq, uint32_t to_secs,
* This routine maps user address and lock pages for DMA.
*
*/
BC_STATUS crystalhd_map_dio(struct crystalhd_adp *adp, void *ubuff,
enum BC_STATUS crystalhd_map_dio(struct crystalhd_adp *adp, void *ubuff,
uint32_t ubuff_sz, uint32_t uv_offset,
bool en_422mode, bool dir_tx,
crystalhd_dio_req **dio_hnd)
struct crystalhd_dio_req **dio_hnd)
{
crystalhd_dio_req *dio;
struct crystalhd_dio_req *dio;
/* FIXME: jarod: should some of these unsigned longs be uint32_t or uintptr_t? */
unsigned long start = 0, end = 0, uaddr = 0, count = 0;
unsigned long spsz = 0, uv_start = 0;
......@@ -820,7 +820,7 @@ BC_STATUS crystalhd_map_dio(struct crystalhd_adp *adp, void *ubuff,
*
* This routine is to unmap the user buffer pages.
*/
BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *adp, crystalhd_dio_req *dio)
enum BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *adp, struct crystalhd_dio_req *dio)
{
struct page *page = NULL;
int j = 0;
......@@ -864,7 +864,7 @@ int crystalhd_create_dio_pool(struct crystalhd_adp *adp, uint32_t max_pages)
{
uint32_t asz = 0, i = 0;
uint8_t *temp;
crystalhd_dio_req *dio;
struct crystalhd_dio_req *dio;
if (!adp || !max_pages) {
BCMLOG_ERR("Invalid Arg!!\n");
......@@ -893,7 +893,7 @@ int crystalhd_create_dio_pool(struct crystalhd_adp *adp, uint32_t max_pages)
return -ENOMEM;
}
dio = (crystalhd_dio_req *)temp;
dio = (struct crystalhd_dio_req *)temp;
temp += sizeof(*dio);
dio->pages = (struct page **)temp;
temp += (sizeof(*dio->pages) * max_pages);
......@@ -923,7 +923,7 @@ int crystalhd_create_dio_pool(struct crystalhd_adp *adp, uint32_t max_pages)
*/
void crystalhd_destroy_dio_pool(struct crystalhd_adp *adp)
{
crystalhd_dio_req *dio;
struct crystalhd_dio_req *dio;
int count = 0;
if (!adp) {
......@@ -965,7 +965,7 @@ int __devinit crystalhd_create_elem_pool(struct crystalhd_adp *adp,
uint32_t pool_size)
{
uint32_t i;
crystalhd_elem_t *temp;
struct crystalhd_elem *temp;
if (!adp || !pool_size)
return -EINVAL;
......@@ -993,7 +993,7 @@ int __devinit crystalhd_create_elem_pool(struct crystalhd_adp *adp,
*/
void crystalhd_delete_elem_pool(struct crystalhd_adp *adp)
{
crystalhd_elem_t *temp;
struct crystalhd_elem *temp;
int dbg_cnt = 0;
if (!adp)
......
drivers/staging/crystalhd/crystalhd_misc.h
View file @ abfc768d
......@@ -54,7 +54,7 @@ extern uint32_t g_linklog_level;
/* Scatter Gather memory pool size for Tx and Rx */
#define BC_LINK_SG_POOL_SZ (BC_TX_LIST_CNT + BC_RX_LIST_CNT)
enum _crystalhd_dio_sig {
enum crystalhd_dio_sig {
crystalhd_dio_inv = 0,
crystalhd_dio_locked,
crystalhd_dio_sg_mapped,
......@@ -76,7 +76,7 @@ struct crystalhd_dio_user_info {
bool b422mode;
};
typedef struct _crystalhd_dio_req {
struct crystalhd_dio_req {
uint32_t sig;
uint32_t max_pages;
struct page **pages;
......@@ -88,34 +88,34 @@ typedef struct _crystalhd_dio_req {
void *fb_va;
uint32_t fb_size;
dma_addr_t fb_pa;
struct _crystalhd_dio_req *next;
} crystalhd_dio_req;
struct crystalhd_dio_req *next;
};
#define BC_LINK_DIOQ_SIG (0x09223280)
typedef struct _crystalhd_elem_s {
struct _crystalhd_elem_s *flink;
struct _crystalhd_elem_s *blink;
struct crystalhd_elem {
struct crystalhd_elem *flink;
struct crystalhd_elem *blink;
void *data;
uint32_t tag;
} crystalhd_elem_t;
};
typedef void (*crystalhd_data_free_cb)(void *context, void *data);
typedef struct _crystalhd_dioq_s {
struct crystalhd_dioq {
uint32_t sig;
struct crystalhd_adp *adp;
crystalhd_elem_t *head;
crystalhd_elem_t *tail;
struct crystalhd_elem *head;
struct crystalhd_elem *tail;
uint32_t count;
spinlock_t lock;
wait_queue_head_t event;
crystalhd_data_free_cb data_rel_cb;
void *cb_context;
} crystalhd_dioq_t;
};
typedef void (*hw_comp_callback)(crystalhd_dio_req *,
wait_queue_head_t *event, BC_STATUS sts);
typedef void (*hw_comp_callback)(struct crystalhd_dio_req *,
wait_queue_head_t *event, enum BC_STATUS sts);
/*========= Decoder (7412) register access routines.================= */
uint32_t bc_dec_reg_rd(struct crystalhd_adp *, uint32_t);
......@@ -126,12 +126,12 @@ uint32_t crystalhd_reg_rd(struct crystalhd_adp *, uint32_t);
void crystalhd_reg_wr(struct crystalhd_adp *, uint32_t, uint32_t);
/*========= Decoder (7412) memory access routines..=================*/
BC_STATUS crystalhd_mem_rd(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t *);
BC_STATUS crystalhd_mem_wr(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t *);
enum BC_STATUS crystalhd_mem_rd(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t *);
enum BC_STATUS crystalhd_mem_wr(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t *);
/*==========Link (70012) PCIe Config access routines.================*/
BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t *);
BC_STATUS crystalhd_pci_cfg_wr(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t);
enum BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t *);
enum BC_STATUS crystalhd_pci_cfg_wr(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t);
/*========= Linux Kernel Interface routines. ======================= */
void *bc_kern_dma_alloc(struct crystalhd_adp *, uint32_t, dma_addr_t *);
......@@ -167,20 +167,20 @@ do { \
/*================ Direct IO mapping routines ==================*/
extern int crystalhd_create_dio_pool(struct crystalhd_adp *, uint32_t);
extern void crystalhd_destroy_dio_pool(struct crystalhd_adp *);
extern BC_STATUS crystalhd_map_dio(struct crystalhd_adp *, void *, uint32_t,
uint32_t, bool, bool, crystalhd_dio_req**);
extern enum BC_STATUS crystalhd_map_dio(struct crystalhd_adp *, void *, uint32_t,
uint32_t, bool, bool, struct crystalhd_dio_req**);
extern BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *, crystalhd_dio_req*);
extern enum BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *, struct crystalhd_dio_req*);
#define crystalhd_get_sgle_paddr(_dio, _ix) (cpu_to_le64(sg_dma_address(&_dio->sg[_ix])))
#define crystalhd_get_sgle_len(_dio, _ix) (cpu_to_le32(sg_dma_len(&_dio->sg[_ix])))
/*================ General Purpose Queues ==================*/
extern BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *, crystalhd_dioq_t **, crystalhd_data_free_cb , void *);
extern void crystalhd_delete_dioq(struct crystalhd_adp *, crystalhd_dioq_t *);
extern BC_STATUS crystalhd_dioq_add(crystalhd_dioq_t *ioq, void *data, bool wake, uint32_t tag);
extern void *crystalhd_dioq_fetch(crystalhd_dioq_t *ioq);
extern void *crystalhd_dioq_find_and_fetch(crystalhd_dioq_t *ioq, uint32_t tag);
extern void *crystalhd_dioq_fetch_wait(crystalhd_dioq_t *ioq, uint32_t to_secs, uint32_t *sig_pend);
extern enum BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *, struct crystalhd_dioq **, crystalhd_data_free_cb , void *);
extern void crystalhd_delete_dioq(struct crystalhd_adp *, struct crystalhd_dioq *);
extern enum BC_STATUS crystalhd_dioq_add(struct crystalhd_dioq *ioq, void *data, bool wake, uint32_t tag);
extern void *crystalhd_dioq_fetch(struct crystalhd_dioq *ioq);
extern void *crystalhd_dioq_find_and_fetch(struct crystalhd_dioq *ioq, uint32_t tag);
extern void *crystalhd_dioq_fetch_wait(struct crystalhd_dioq *ioq, uint32_t to_secs, uint32_t *sig_pend);
#define crystalhd_dioq_count(_ioq) ((_ioq) ? _ioq->count : 0)
......
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