Commit ac81c2a7 authored by Joseph Gravenor's avatar Joseph Gravenor Committed by Alex Deucher

drm/amd/display: add guard for SMU ver, for 48mhz clk

[why]
dp_48m_refclk_driver_pwdn is persistent through S3 and S5.
This was worked arround in SMU FW 55.21.0. Earlier FW don't have this fix
so we will hang on reboot

[how]
add a guard for smu versions before SMU FW 55.21.0
Signed-off-by: default avatarJoseph Gravenor <joseph.gravenor@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 57133a28
...@@ -649,7 +649,7 @@ void rn_clk_mgr_construct( ...@@ -649,7 +649,7 @@ void rn_clk_mgr_construct(
pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges); pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges);
} }
if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) {
/* enable powerfeatures when displaycount goes to 0 */ /* enable powerfeatures when displaycount goes to 0 */
rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn); rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
} }
......
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