Commit afd7350a authored by Stefan Agner's avatar Stefan Agner Committed by Shawn Guo

clk: imx: vf610: add TCON ipg clock

Add the ipg (bus) clock for the TCON modules (Timing Controller). This
module is required by the new DCU DRM driver, since the display signals
pass through TCON.
Signed-off-by: default avatarStefan Agner <stefan@agner.ch>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 3218b21a
...@@ -378,6 +378,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) ...@@ -378,6 +378,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3); clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3);
clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(8)); clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(8));
clk[VF610_CLK_TCON0] = imx_clk_gate2("tcon0", "platform_bus", CCM_CCGR1, CCM_CCGRx_CGn(13));
clk[VF610_CLK_TCON1] = imx_clk_gate2("tcon1", "platform_bus", CCM_CCGR7, CCM_CCGRx_CGn(13));
clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4); clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4);
clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30); clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30);
clk[VF610_CLK_ESAI_DIV] = imx_clk_divider("esai_div", "esai_en", CCM_CSCDR2, 24, 4); clk[VF610_CLK_ESAI_DIV] = imx_clk_divider("esai_div", "esai_en", CCM_CSCDR2, 24, 4);
......
...@@ -197,6 +197,8 @@ ...@@ -197,6 +197,8 @@
#define VF610_CLK_OCOTP 184 #define VF610_CLK_OCOTP 184
#define VF610_CLK_DDRMC 185 #define VF610_CLK_DDRMC 185
#define VF610_CLK_WKPU 186 #define VF610_CLK_WKPU 186
#define VF610_CLK_END 187 #define VF610_CLK_TCON0 187
#define VF610_CLK_TCON1 188
#define VF610_CLK_END 189
#endif /* __DT_BINDINGS_CLOCK_VF610_H */ #endif /* __DT_BINDINGS_CLOCK_VF610_H */
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