Commit b0dc465f authored by Chris Wilson's avatar Chris Wilson

drm/i915: Tidy up flush cpu/gtt write domains

Since we know the write domain, we can drop the local variable and make
the code look a tiny bit simpler.
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20160818161718.27187-12-chris@chris-wilson.co.uk
parent 9764951e
...@@ -3182,7 +3182,6 @@ static void ...@@ -3182,7 +3182,6 @@ static void
i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
{ {
struct drm_i915_private *dev_priv = to_i915(obj->base.dev); struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
uint32_t old_write_domain;
if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
return; return;
...@@ -3206,36 +3205,30 @@ i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) ...@@ -3206,36 +3205,30 @@ i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv))
POSTING_READ(RING_ACTHD(dev_priv->engine[RCS].mmio_base)); POSTING_READ(RING_ACTHD(dev_priv->engine[RCS].mmio_base));
old_write_domain = obj->base.write_domain;
obj->base.write_domain = 0;
intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT)); intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT));
obj->base.write_domain = 0;
trace_i915_gem_object_change_domain(obj, trace_i915_gem_object_change_domain(obj,
obj->base.read_domains, obj->base.read_domains,
old_write_domain); I915_GEM_DOMAIN_GTT);
} }
/** Flushes the CPU write domain for the object if it's dirty. */ /** Flushes the CPU write domain for the object if it's dirty. */
static void static void
i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
{ {
uint32_t old_write_domain;
if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
return; return;
if (i915_gem_clflush_object(obj, obj->pin_display)) if (i915_gem_clflush_object(obj, obj->pin_display))
i915_gem_chipset_flush(to_i915(obj->base.dev)); i915_gem_chipset_flush(to_i915(obj->base.dev));
old_write_domain = obj->base.write_domain;
obj->base.write_domain = 0;
intel_fb_obj_flush(obj, false, ORIGIN_CPU); intel_fb_obj_flush(obj, false, ORIGIN_CPU);
obj->base.write_domain = 0;
trace_i915_gem_object_change_domain(obj, trace_i915_gem_object_change_domain(obj,
obj->base.read_domains, obj->base.read_domains,
old_write_domain); I915_GEM_DOMAIN_CPU);
} }
/** /**
......
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