drm/nouveau/fb: cosmetic changes

This is purely preparation for upcoming commits, there should be no
code changes here.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h

@@ -46,7 +46,7 @@ struct nvkm_fb_tile {
 };
 
 struct nvkm_fb {
-	struct nvkm_subdev base;
+	struct nvkm_subdev subdev;
 
 	bool (*memtype_valid)(struct nvkm_fb *, u32 memtype);
 

drivers/gpu/drm/nouveau/nouveau_bo.c

@@ -48,23 +48,23 @@ nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
 {
 	struct nouveau_drm *drm = nouveau_drm(dev);
 	int i = reg - drm->tile.reg;
-	struct nvkm_fb *pfb = nvxx_fb(&drm->device);
-	struct nvkm_fb_tile *tile = &pfb->tile.region[i];
+	struct nvkm_fb *fb = nvxx_fb(&drm->device);
+	struct nvkm_fb_tile *tile = &fb->tile.region[i];
 	struct nvkm_engine *engine;
 
 	nouveau_fence_unref(&reg->fence);
 
 	if (tile->pitch)
-		pfb->tile.fini(pfb, i, tile);
+		fb->tile.fini(fb, i, tile);
 
 	if (pitch)
-		pfb->tile.init(pfb, i, addr, size, pitch, flags, tile);
+		fb->tile.init(fb, i, addr, size, pitch, flags, tile);
 
-	pfb->tile.prog(pfb, i, tile);
+	fb->tile.prog(fb, i, tile);
 
-	if ((engine = nvkm_engine(pfb, NVDEV_ENGINE_GR)))
+	if ((engine = nvkm_engine(fb, NVDEV_ENGINE_GR)))
 		engine->tile_prog(engine, i);
-	if ((engine = nvkm_engine(pfb, NVDEV_ENGINE_MPEG)))
+	if ((engine = nvkm_engine(fb, NVDEV_ENGINE_MPEG)))
 		engine->tile_prog(engine, i);
 }
 
@@ -105,18 +105,18 @@ nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
 		   u32 size, u32 pitch, u32 flags)
 {
 	struct nouveau_drm *drm = nouveau_drm(dev);
-	struct nvkm_fb *pfb = nvxx_fb(&drm->device);
+	struct nvkm_fb *fb = nvxx_fb(&drm->device);
 	struct nouveau_drm_tile *tile, *found = NULL;
 	int i;
 
-	for (i = 0; i < pfb->tile.regions; i++) {
+	for (i = 0; i < fb->tile.regions; i++) {
 		tile = nv10_bo_get_tile_region(dev, i);
 
 		if (pitch && !found) {
 			found = tile;
 			continue;
 
-		} else if (tile && pfb->tile.region[i].pitch) {
+		} else if (tile && fb->tile.region[i].pitch) {
 			/* Kill an unused tile region. */
 			nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
 		}

drivers/gpu/drm/nouveau/nouveau_gem.c

@@ -254,12 +254,12 @@ nouveau_gem_ioctl_new(struct drm_device *dev, void *data,
 {
 	struct nouveau_drm *drm = nouveau_drm(dev);
 	struct nouveau_cli *cli = nouveau_cli(file_priv);
-	struct nvkm_fb *pfb = nvxx_fb(&drm->device);
+	struct nvkm_fb *fb = nvxx_fb(&drm->device);
 	struct drm_nouveau_gem_new *req = data;
 	struct nouveau_bo *nvbo = NULL;
 	int ret = 0;
 
-	if (!pfb->memtype_valid(pfb, req->info.tile_flags)) {
+	if (!fb->memtype_valid(fb, req->info.tile_flags)) {
 		NV_PRINTK(error, cli, "bad page flags: 0x%08x\n", req->info.tile_flags);
 		return -EINVAL;
 	}

drivers/gpu/drm/nouveau/nouveau_ttm.c

@@ -33,8 +33,8 @@ static int
 nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
 {
 	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
-	struct nvkm_fb *pfb = nvxx_fb(&drm->device);
-	man->priv = pfb;
+	struct nvkm_fb *fb = nvxx_fb(&drm->device);
+	man->priv = fb;
 	return 0;
 }
 
@@ -64,9 +64,9 @@ nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
 			 struct ttm_mem_reg *mem)
 {
 	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
-	struct nvkm_fb *pfb = nvxx_fb(&drm->device);
+	struct nvkm_fb *fb = nvxx_fb(&drm->device);
 	nvkm_mem_node_cleanup(mem->mm_node);
-	pfb->ram->put(pfb, (struct nvkm_mem **)&mem->mm_node);
+	fb->ram->put(fb, (struct nvkm_mem **)&mem->mm_node);
 }
 
 static int
@@ -76,7 +76,7 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
 			 struct ttm_mem_reg *mem)
 {
 	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
-	struct nvkm_fb *pfb = nvxx_fb(&drm->device);
+	struct nvkm_fb *fb = nvxx_fb(&drm->device);
 	struct nouveau_bo *nvbo = nouveau_bo(bo);
 	struct nvkm_mem *node;
 	u32 size_nc = 0;
@@ -88,7 +88,7 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
 	if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
 		size_nc = 1 << nvbo->page_shift;
 
-	ret = pfb->ram->get(pfb, mem->num_pages << PAGE_SHIFT,
+	ret = fb->ram->get(fb, mem->num_pages << PAGE_SHIFT,
 			   mem->page_alignment << PAGE_SHIFT, size_nc,
 			   (nvbo->tile_flags >> 8) & 0x3ff, &node);
 	if (ret) {
@@ -106,12 +106,12 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
 static void
 nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
 {
-	struct nvkm_fb *pfb = man->priv;
-	struct nvkm_mm *mm = &pfb->vram;
+	struct nvkm_fb *fb = man->priv;
+	struct nvkm_mm *mm = &fb->vram;
 	struct nvkm_mm_node *r;
 	u32 total = 0, free = 0;
 
-	mutex_lock(&nv_subdev(pfb)->mutex);
+	mutex_lock(&nv_subdev(fb)->mutex);
 	list_for_each_entry(r, &mm->nodes, nl_entry) {
 		printk(KERN_DEBUG "%s %d: 0x%010llx 0x%010llx\n",
 		       prefix, r->type, ((u64)r->offset << 12),
@@ -121,7 +121,7 @@ nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
 		if (!r->type)
 			free += r->length;
 	}
-	mutex_unlock(&nv_subdev(pfb)->mutex);
+	mutex_unlock(&nv_subdev(fb)->mutex);
 
 	printk(KERN_DEBUG "%s  total: 0x%010llx free: 0x%010llx\n",
 	       prefix, (u64)total << 12, (u64)free << 12);

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

@@ -80,7 +80,7 @@ static int
 nvkm_devobj_info(struct nvkm_object *object, void *data, u32 size)
 {
 	struct nvkm_device *device = nv_device(object);
-	struct nvkm_fb *pfb = nvkm_fb(device);
+	struct nvkm_fb *fb = nvkm_fb(device);
 	struct nvkm_instmem *imem = nvkm_instmem(device);
 	union {
 		struct nv_device_info_v0 v0;
@@ -139,8 +139,8 @@ nvkm_devobj_info(struct nvkm_object *object, void *data, u32 size)
 
 	args->v0.chipset  = device->chipset;
 	args->v0.revision = device->chiprev;
-	if (pfb && pfb->ram)
-		args->v0.ram_size = args->v0.ram_user = pfb->ram->size;
+	if (fb && fb->ram)
+		args->v0.ram_size = args->v0.ram_user = fb->ram->size;
 	else
 		args->v0.ram_size = args->v0.ram_user = 0;
 	if (imem && args->v0.ram_size > 0)

drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c

@@ -64,7 +64,7 @@ nvkm_dmaobj_create_(struct nvkm_object *parent,
 	struct nvkm_instmem *instmem = nvkm_instmem(parent);
 	struct nvkm_client *client = nvkm_client(parent);
 	struct nvkm_device *device = nv_device(parent);
-	struct nvkm_fb *pfb = nvkm_fb(parent);
+	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nvkm_dmaobj *dmaobj;
 	void *data = *pdata;
 	u32 size = *psize;
@@ -100,7 +100,7 @@ nvkm_dmaobj_create_(struct nvkm_object *parent,
 		break;
 	case NV_DMA_V0_TARGET_VRAM:
 		if (!client->super) {
-			if (dmaobj->limit >= pfb->ram->size - instmem->reserved)
+			if (dmaobj->limit >= fb->ram->size - instmem->reserved)
 				return -EACCES;
 			if (device->card_type >= NV_50)
 				return -EACCES;

drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c

@@ -295,7 +295,7 @@ static int
 nv40_fifo_init(struct nvkm_object *object)
 {
 	struct nv04_fifo_priv *priv = (void *)object;
-	struct nvkm_fb *pfb = nvkm_fb(object);
+	struct nvkm_fb *fb = nvkm_fb(object);
 	int ret;
 
 	ret = nvkm_fifo_init(&priv->base);
@@ -326,7 +326,7 @@ nv40_fifo_init(struct nvkm_object *object)
 		break;
 	default:
 		nv_wr32(priv, 0x002230, 0x00000000);
-		nv_wr32(priv, 0x002220, ((pfb->ram->size - 512 * 1024 +
+		nv_wr32(priv, 0x002220, ((fb->ram->size - 512 * 1024 +
 					 priv->ramfc->addr) >> 16) |
 					0x00030000);
 		break;

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c

@@ -1249,7 +1249,7 @@ static int
 nv10_gr_init(struct nvkm_object *object)
 {
 	struct nvkm_engine *engine = nv_engine(object);
-	struct nvkm_fb *pfb = nvkm_fb(object);
+	struct nvkm_fb *fb = nvkm_fb(object);
 	struct nv10_gr_priv *priv = (void *)engine;
 	int ret, i;
 
@@ -1279,7 +1279,7 @@ nv10_gr_init(struct nvkm_object *object)
 	}
 
 	/* Turn all the tiling regions off. */
-	for (i = 0; i < pfb->tile.regions; i++)
+	for (i = 0; i < fb->tile.regions; i++)
 		engine->tile_prog(engine, i);
 
 	nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c

@@ -271,7 +271,7 @@ nv20_gr_init(struct nvkm_object *object)
 {
 	struct nvkm_engine *engine = nv_engine(object);
 	struct nv20_gr_priv *priv = (void *)engine;
-	struct nvkm_fb *pfb = nvkm_fb(object);
+	struct nvkm_fb *fb = nvkm_fb(object);
 	u32 tmp, vramsz;
 	int ret, i;
 
@@ -324,7 +324,7 @@ nv20_gr_init(struct nvkm_object *object)
 	}
 
 	/* Turn all the tiling regions off. */
-	for (i = 0; i < pfb->tile.regions; i++)
+	for (i = 0; i < fb->tile.regions; i++)
 		engine->tile_prog(engine, i);
 
 	nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324));

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c

@@ -153,7 +153,7 @@ nv30_gr_init(struct nvkm_object *object)
 {
 	struct nvkm_engine *engine = nv_engine(object);
 	struct nv20_gr_priv *priv = (void *)engine;
-	struct nvkm_fb *pfb = nvkm_fb(object);
+	struct nvkm_fb *fb = nvkm_fb(object);
 	int ret, i;
 
 	ret = nvkm_gr_init(&priv->base);
@@ -198,7 +198,7 @@ nv30_gr_init(struct nvkm_object *object)
 	nv_wr32(priv, 0x4000c0, 0x00000016);
 
 	/* Turn all the tiling regions off. */
-	for (i = 0; i < pfb->tile.regions; i++)
+	for (i = 0; i < fb->tile.regions; i++)
 		engine->tile_prog(engine, i);
 
 	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);

drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c

@@ -366,7 +366,7 @@ static int
 nv40_gr_init(struct nvkm_object *object)
 {
 	struct nvkm_engine *engine = nv_engine(object);
-	struct nvkm_fb *pfb = nvkm_fb(object);
+	struct nvkm_fb *fb = nvkm_fb(object);
 	struct nv40_gr_priv *priv = (void *)engine;
 	int ret, i, j;
 	u32 vramsz;
@@ -470,7 +470,7 @@ nv40_gr_init(struct nvkm_object *object)
 	}
 
 	/* Turn all the tiling regions off. */
-	for (i = 0; i < pfb->tile.regions; i++)
+	for (i = 0; i < fb->tile.regions; i++)
 		engine->tile_prog(engine, i);
 
 	/* begin RAM config */

drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c

@@ -260,7 +260,7 @@ nv31_mpeg_init(struct nvkm_object *object)
 {
 	struct nvkm_engine *engine = nv_engine(object);
 	struct nv31_mpeg_priv *priv = (void *)object;
-	struct nvkm_fb *pfb = nvkm_fb(object);
+	struct nvkm_fb *fb = nvkm_fb(object);
 	int ret, i;
 
 	ret = nvkm_mpeg_init(&priv->base);
@@ -271,7 +271,7 @@ nv31_mpeg_init(struct nvkm_object *object)
 	nv_wr32(priv, 0x00b0e0, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
 	nv_wr32(priv, 0x00b0e8, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
 
-	for (i = 0; i < pfb->tile.regions; i++)
+	for (i = 0; i < fb->tile.regions; i++)
 		engine->tile_prog(engine, i);
 
 	/* PMPEG init */

drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c

@@ -171,7 +171,7 @@ nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate)
 static int
 nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei)
 {
-	struct nvkm_fb *pfb = nvkm_fb(clk);
+	struct nvkm_fb *fb = nvkm_fb(clk);
 	struct nvkm_pstate *pstate;
 	int ret, idx = 0;
 
@@ -183,14 +183,14 @@ nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei)
 	nv_debug(clk, "setting performance state %d\n", pstatei);
 	clk->pstate = pstatei;
 
-	if (pfb->ram && pfb->ram->calc) {
+	if (fb->ram && fb->ram->calc) {
 		int khz = pstate->base.domain[nv_clk_src_mem];
 		do {
-			ret = pfb->ram->calc(pfb, khz);
+			ret = fb->ram->calc(fb, khz);
 			if (ret == 0)
-				ret = pfb->ram->prog(pfb);
+				ret = fb->ram->prog(fb);
 		} while (ret > 0);
-		pfb->ram->tidy(pfb);
+		fb->ram->tidy(fb);
 	}
 
 	return nvkm_cstate_prog(clk, pstate, 0);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c

@@ -52,36 +52,36 @@ nvkm_fb_bios_memtype(struct nvkm_bios *bios)
 int
 _nvkm_fb_fini(struct nvkm_object *object, bool suspend)
 {
-	struct nvkm_fb *pfb = (void *)object;
+	struct nvkm_fb *fb = (void *)object;
 	int ret;
 
-	if (pfb->ram) {
-		ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend);
+	if (fb->ram) {
+		ret = nv_ofuncs(fb->ram)->fini(nv_object(fb->ram), suspend);
 		if (ret && suspend)
 			return ret;
 	}
 
-	return nvkm_subdev_fini(&pfb->base, suspend);
+	return nvkm_subdev_fini(&fb->subdev, suspend);
 }
 
 int
 _nvkm_fb_init(struct nvkm_object *object)
 {
-	struct nvkm_fb *pfb = (void *)object;
+	struct nvkm_fb *fb = (void *)object;
 	int ret, i;
 
-	ret = nvkm_subdev_init(&pfb->base);
+	ret = nvkm_subdev_init(&fb->subdev);
 	if (ret)
 		return ret;
 
-	if (pfb->ram) {
-		ret = nv_ofuncs(pfb->ram)->init(nv_object(pfb->ram));
+	if (fb->ram) {
+		ret = nv_ofuncs(fb->ram)->init(nv_object(fb->ram));
 		if (ret)
 			return ret;
 	}
 
-	for (i = 0; i < pfb->tile.regions; i++)
-		pfb->tile.prog(pfb, i, &pfb->tile.region[i]);
+	for (i = 0; i < fb->tile.regions; i++)
+		fb->tile.prog(fb, i, &fb->tile.region[i]);
 
 	return 0;
 }
@@ -89,19 +89,19 @@ _nvkm_fb_init(struct nvkm_object *object)
 void
 _nvkm_fb_dtor(struct nvkm_object *object)
 {
-	struct nvkm_fb *pfb = (void *)object;
+	struct nvkm_fb *fb = (void *)object;
 	int i;
 
-	for (i = 0; i < pfb->tile.regions; i++)
-		pfb->tile.fini(pfb, i, &pfb->tile.region[i]);
-	nvkm_mm_fini(&pfb->tags);
+	for (i = 0; i < fb->tile.regions; i++)
+		fb->tile.fini(fb, i, &fb->tile.region[i]);
+	nvkm_mm_fini(&fb->tags);
 
-	if (pfb->ram) {
-		nvkm_mm_fini(&pfb->vram);
-		nvkm_object_ref(NULL, (struct nvkm_object **)&pfb->ram);
+	if (fb->ram) {
+		nvkm_mm_fini(&fb->vram);
+		nvkm_object_ref(NULL, (struct nvkm_object **)&fb->ram);
 	}
 
-	nvkm_subdev_destroy(&pfb->base);
+	nvkm_subdev_destroy(&fb->subdev);
 }
 
 int
@@ -123,43 +123,43 @@ nvkm_fb_create_(struct nvkm_object *parent, struct nvkm_object *engine,
 		[NV_MEM_TYPE_GDDR5  ] = "GDDR5",
 	};
 	struct nvkm_object *ram;
-	struct nvkm_fb *pfb;
+	struct nvkm_fb *fb;
 	int ret;
 
 	ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PFB", "fb",
 				  length, pobject);
-	pfb = *pobject;
+	fb = *pobject;
 	if (ret)
 		return ret;
 
-	pfb->memtype_valid = impl->memtype;
+	fb->memtype_valid = impl->memtype;
 
 	if (!impl->ram)
 		return 0;
 
-	ret = nvkm_object_ctor(nv_object(pfb), NULL, impl->ram, NULL, 0, &ram);
+	ret = nvkm_object_ctor(nv_object(fb), NULL, impl->ram, NULL, 0, &ram);
 	if (ret) {
-		nv_fatal(pfb, "error detecting memory configuration!!\n");
+		nv_fatal(fb, "error detecting memory configuration!!\n");
 		return ret;
 	}
 
-	pfb->ram = (void *)ram;
+	fb->ram = (void *)ram;
 
-	if (!nvkm_mm_initialised(&pfb->vram)) {
-		ret = nvkm_mm_init(&pfb->vram, 0, pfb->ram->size >> 12, 1);
+	if (!nvkm_mm_initialised(&fb->vram)) {
+		ret = nvkm_mm_init(&fb->vram, 0, fb->ram->size >> 12, 1);
 		if (ret)
 			return ret;
 	}
 
-	if (!nvkm_mm_initialised(&pfb->tags)) {
-		ret = nvkm_mm_init(&pfb->tags, 0, pfb->ram->tags ?
-				   ++pfb->ram->tags : 0, 1);
+	if (!nvkm_mm_initialised(&fb->tags)) {
+		ret = nvkm_mm_init(&fb->tags, 0, fb->ram->tags ?
+				   ++fb->ram->tags : 0, 1);
 		if (ret)
 			return ret;
 	}
 
-	nv_info(pfb, "RAM type: %s\n", name[pfb->ram->type]);
-	nv_info(pfb, "RAM size: %d MiB\n", (int)(pfb->ram->size >> 20));
-	nv_info(pfb, "   ZCOMP: %d tags\n", pfb->ram->tags);
+	nv_info(fb, "RAM type: %s\n", name[fb->ram->type]);
+	nv_info(fb, "RAM size: %d MiB\n", (int)(fb->ram->size >> 20));
+	nv_info(fb, "   ZCOMP: %d tags\n", fb->ram->tags);
 	return 0;
 }

drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c

@@ -26,7 +26,7 @@
 extern const u8 gf100_pte_storage_type_map[256];
 
 bool
-gf100_fb_memtype_valid(struct nvkm_fb *pfb, u32 tile_flags)
+gf100_fb_memtype_valid(struct nvkm_fb *fb, u32 tile_flags)
 {
 	u8 memtype = (tile_flags & 0x0000ff00) >> 8;
 	return likely((gf100_pte_storage_type_map[memtype] != 0xff));
@@ -35,32 +35,28 @@ gf100_fb_memtype_valid(struct nvkm_fb *pfb, u32 tile_flags)
 static void
 gf100_fb_intr(struct nvkm_subdev *subdev)
 {
-	struct gf100_fb_priv *priv = (void *)subdev;
-	u32 intr = nv_rd32(priv, 0x000100);
-	if (intr & 0x08000000) {
-		nv_debug(priv, "PFFB intr\n");
-		intr &= ~0x08000000;
-	}
-	if (intr & 0x00002000) {
-		nv_debug(priv, "PBFB intr\n");
-		intr &= ~0x00002000;
-	}
+	struct gf100_fb *fb = (void *)subdev;
+	u32 intr = nv_rd32(fb, 0x000100);
+	if (intr & 0x08000000)
+		nv_debug(fb, "PFFB intr\n");
+	if (intr & 0x00002000)
+		nv_debug(fb, "PBFB intr\n");
 }
 
 int
 gf100_fb_init(struct nvkm_object *object)
 {
-	struct gf100_fb_priv *priv = (void *)object;
+	struct gf100_fb *fb = (void *)object;
 	int ret;
 
-	ret = nvkm_fb_init(&priv->base);
+	ret = nvkm_fb_init(&fb->base);
 	if (ret)
 		return ret;
 
-	if (priv->r100c10_page)
-		nv_wr32(priv, 0x100c10, priv->r100c10 >> 8);
+	if (fb->r100c10_page)
+		nv_wr32(fb, 0x100c10, fb->r100c10 >> 8);
 
-	nv_mask(priv, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */
+	nv_mask(fb, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */
 	return 0;
 }
 
@@ -68,15 +64,15 @@ void
 gf100_fb_dtor(struct nvkm_object *object)
 {
 	struct nvkm_device *device = nv_device(object);
-	struct gf100_fb_priv *priv = (void *)object;
+	struct gf100_fb *fb = (void *)object;
 
-	if (priv->r100c10_page) {
-		dma_unmap_page(nv_device_base(device), priv->r100c10, PAGE_SIZE,
+	if (fb->r100c10_page) {
+		dma_unmap_page(nv_device_base(device), fb->r100c10, PAGE_SIZE,
 			       DMA_BIDIRECTIONAL);
-		__free_page(priv->r100c10_page);
+		__free_page(fb->r100c10_page);
 	}
 
-	nvkm_fb_destroy(&priv->base);
+	nvkm_fb_destroy(&fb->base);
 }
 
 int
@@ -85,24 +81,24 @@ gf100_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	      struct nvkm_object **pobject)
 {
 	struct nvkm_device *device = nv_device(parent);
-	struct gf100_fb_priv *priv;
+	struct gf100_fb *fb;
 	int ret;
 
-	ret = nvkm_fb_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
+	ret = nvkm_fb_create(parent, engine, oclass, &fb);
+	*pobject = nv_object(fb);
 	if (ret)
 		return ret;
 
-	priv->r100c10_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
-	if (priv->r100c10_page) {
-		priv->r100c10 = dma_map_page(nv_device_base(device),
-					     priv->r100c10_page, 0, PAGE_SIZE,
+	fb->r100c10_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
+	if (fb->r100c10_page) {
+		fb->r100c10 = dma_map_page(nv_device_base(device),
+					     fb->r100c10_page, 0, PAGE_SIZE,
 					     DMA_BIDIRECTIONAL);
-		if (dma_mapping_error(nv_device_base(device), priv->r100c10))
+		if (dma_mapping_error(nv_device_base(device), fb->r100c10))
 			return -EFAULT;
 	}
 
-	nv_subdev(priv)->intr = gf100_fb_intr;
+	nv_subdev(fb)->intr = gf100_fb_intr;
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h

@@ -3,7 +3,7 @@
 #include "priv.h"
 #include "nv50.h"
 
-struct gf100_fb_priv {
+struct gf100_fb {
 	struct nvkm_fb base;
 	struct page *r100c10_page;
 	dma_addr_t r100c10;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c

@@ -21,21 +21,17 @@
  */
 #include "gf100.h"
 
-struct gk20a_fb_priv {
-	struct nvkm_fb base;
-};
-
 static int
 gk20a_fb_init(struct nvkm_object *object)
 {
-	struct gk20a_fb_priv *priv = (void *)object;
+	struct nvkm_fb *fb = (void *)object;
 	int ret;
 
-	ret = nvkm_fb_init(&priv->base);
+	ret = nvkm_fb_init(fb);
 	if (ret)
 		return ret;
 
-	nv_mask(priv, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */
+	nv_mask(fb, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */
 	return 0;
 }
 
@@ -44,11 +40,11 @@ gk20a_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	      struct nvkm_oclass *oclass, void *data, u32 size,
 	      struct nvkm_object **pobject)
 {
-	struct gk20a_fb_priv *priv;
+	struct nvkm_fb *fb;
 	int ret;
 
-	ret = nvkm_fb_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
+	ret = nvkm_fb_create(parent, engine, oclass, &fb);
+	*pobject = nv_object(fb);
 	if (ret)
 		return ret;
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c

@@ -25,7 +25,7 @@
 #include "regsnv04.h"
 
 bool
-nv04_fb_memtype_valid(struct nvkm_fb *pfb, u32 tile_flags)
+nv04_fb_memtype_valid(struct nvkm_fb *fb, u32 tile_flags)
 {
 	if (!(tile_flags & 0xff00))
 		return true;
@@ -36,10 +36,10 @@ nv04_fb_memtype_valid(struct nvkm_fb *pfb, u32 tile_flags)
 static int
 nv04_fb_init(struct nvkm_object *object)
 {
-	struct nv04_fb_priv *priv = (void *)object;
+	struct nvkm_fb *fb = (void *)object;
 	int ret;
 
-	ret = nvkm_fb_init(&priv->base);
+	ret = nvkm_fb_init(fb);
 	if (ret)
 		return ret;
 
@@ -47,7 +47,7 @@ nv04_fb_init(struct nvkm_object *object)
 	 * nvidia reading PFB_CFG_0, then writing back its original value.
 	 * (which was 0x701114 in this case)
 	 */
-	nv_wr32(priv, NV04_PFB_CFG0, 0x1114);
+	nv_wr32(fb, NV04_PFB_CFG0, 0x1114);
 	return 0;
 }
 
@@ -57,19 +57,19 @@ nv04_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	     struct nvkm_object **pobject)
 {
 	struct nv04_fb_impl *impl = (void *)oclass;
-	struct nv04_fb_priv *priv;
+	struct nvkm_fb *fb;
 	int ret;
 
-	ret = nvkm_fb_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
+	ret = nvkm_fb_create(parent, engine, oclass, &fb);
+	*pobject = nv_object(fb);
 	if (ret)
 		return ret;
 
-	priv->base.tile.regions = impl->tile.regions;
-	priv->base.tile.init = impl->tile.init;
-	priv->base.tile.comp = impl->tile.comp;
-	priv->base.tile.fini = impl->tile.fini;
-	priv->base.tile.prog = impl->tile.prog;
+	fb->tile.regions = impl->tile.regions;
+	fb->tile.init = impl->tile.init;
+	fb->tile.comp = impl->tile.comp;
+	fb->tile.fini = impl->tile.fini;
+	fb->tile.prog = impl->tile.prog;
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h

@@ -2,10 +2,6 @@
 #define __NVKM_FB_NV04_H__
 #include "priv.h"
 
-struct nv04_fb_priv {
-	struct nvkm_fb base;
-};
-
 int  nv04_fb_ctor(struct nvkm_object *, struct nvkm_object *,
 		  struct nvkm_oclass *, void *, u32,
 		  struct nvkm_object **);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c

@@ -26,7 +26,7 @@
 #include "nv04.h"
 
 void
-nv10_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
+nv10_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch,
 		  u32 flags, struct nvkm_fb_tile *tile)
 {
 	tile->addr  = 0x80000000 | addr;
@@ -35,7 +35,7 @@ nv10_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
 }
 
 void
-nv10_fb_tile_fini(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
+nv10_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
 {
 	tile->addr  = 0;
 	tile->limit = 0;
@@ -44,12 +44,12 @@ nv10_fb_tile_fini(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
 }
 
 void
-nv10_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
+nv10_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
 {
-	nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit);
-	nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch);
-	nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr);
-	nv_rd32(pfb, 0x100240 + (i * 0x10));
+	nv_wr32(fb, 0x100244 + (i * 0x10), tile->limit);
+	nv_wr32(fb, 0x100248 + (i * 0x10), tile->pitch);
+	nv_wr32(fb, 0x100240 + (i * 0x10), tile->addr);
+	nv_rd32(fb, 0x100240 + (i * 0x10));
 }
 
 struct nvkm_oclass *

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

@@ -26,25 +26,25 @@
 #include "nv04.h"
 
 void
-nv20_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
+nv20_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch,
 		  u32 flags, struct nvkm_fb_tile *tile)
 {
 	tile->addr  = 0x00000001 | addr;
 	tile->limit = max(1u, addr + size) - 1;
 	tile->pitch = pitch;
 	if (flags & 4) {
-		pfb->tile.comp(pfb, i, size, flags, tile);
+		fb->tile.comp(fb, i, size, flags, tile);
 		tile->addr |= 2;
 	}
 }
 
 static void
-nv20_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags,
+nv20_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags,
 		  struct nvkm_fb_tile *tile)
 {
 	u32 tiles = DIV_ROUND_UP(size, 0x40);
-	u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
-	if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
+	u32 tags  = round_up(tiles / fb->ram->parts, 0x40);
+	if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
 		if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */
 		else              tile->zcomp = 0x04000000; /* Z24S8 */
 		tile->zcomp |= tile->tag->offset;
@@ -56,23 +56,23 @@ nv20_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags,
 }
 
 void
-nv20_fb_tile_fini(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
+nv20_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
 {
 	tile->addr  = 0;
 	tile->limit = 0;
 	tile->pitch = 0;
 	tile->zcomp = 0;
-	nvkm_mm_free(&pfb->tags, &tile->tag);
+	nvkm_mm_free(&fb->tags, &tile->tag);
 }
 
 void
-nv20_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
+nv20_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
 {
-	nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit);
-	nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch);
-	nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr);
-	nv_rd32(pfb, 0x100240 + (i * 0x10));
-	nv_wr32(pfb, 0x100300 + (i * 0x04), tile->zcomp);
+	nv_wr32(fb, 0x100244 + (i * 0x10), tile->limit);
+	nv_wr32(fb, 0x100248 + (i * 0x10), tile->pitch);
+	nv_wr32(fb, 0x100240 + (i * 0x10), tile->addr);
+	nv_rd32(fb, 0x100240 + (i * 0x10));
+	nv_wr32(fb, 0x100300 + (i * 0x04), tile->zcomp);
 }
 
 struct nvkm_oclass *

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c

@@ -26,12 +26,12 @@
 #include "nv04.h"
 
 static void
-nv25_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags,
+nv25_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags,
 		  struct nvkm_fb_tile *tile)
 {
 	u32 tiles = DIV_ROUND_UP(size, 0x40);
-	u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
-	if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
+	u32 tags  = round_up(tiles / fb->ram->parts, 0x40);
+	if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
 		if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */
 		else              tile->zcomp = 0x00200000; /* Z24S8 */
 		tile->zcomp |= tile->tag->offset;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

@@ -26,15 +26,15 @@
 #include "nv04.h"
 
 void
-nv30_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
+nv30_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch,
 		  u32 flags, struct nvkm_fb_tile *tile)
 {
 	/* for performance, select alternate bank offset for zeta */
 	if (!(flags & 4)) {
 		tile->addr = (0 << 4);
 	} else {
-		if (pfb->tile.comp) /* z compression */
-			pfb->tile.comp(pfb, i, size, flags, tile);
+		if (fb->tile.comp) /* z compression */
+			fb->tile.comp(fb, i, size, flags, tile);
 		tile->addr = (1 << 4);
 	}
 
@@ -45,12 +45,12 @@ nv30_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
 }
 
 static void
-nv30_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags,
+nv30_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags,
 		  struct nvkm_fb_tile *tile)
 {
 	u32 tiles = DIV_ROUND_UP(size, 0x40);
-	u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
-	if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
+	u32 tags  = round_up(tiles / fb->ram->parts, 0x40);
+	if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
 		if (flags & 2) tile->zcomp |= 0x01000000; /* Z16 */
 		else           tile->zcomp |= 0x02000000; /* Z24S8 */
 		tile->zcomp |= ((tile->tag->offset           ) >> 6);
@@ -62,23 +62,23 @@ nv30_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags,
 }
 
 static int
-calc_bias(struct nv04_fb_priv *priv, int k, int i, int j)
+calc_bias(struct nvkm_fb *fb, int k, int i, int j)
 {
-	struct nvkm_device *device = nv_device(priv);
+	struct nvkm_device *device = nv_device(fb);
 	int b = (device->chipset > 0x30 ?
-		 nv_rd32(priv, 0x122c + 0x10 * k + 0x4 * j) >> (4 * (i ^ 1)) :
+		 nv_rd32(fb, 0x122c + 0x10 * k + 0x4 * j) >> (4 * (i ^ 1)) :
 		 0) & 0xf;
 
 	return 2 * (b & 0x8 ? b - 0x10 : b);
 }
 
 static int
-calc_ref(struct nv04_fb_priv *priv, int l, int k, int i)
+calc_ref(struct nvkm_fb *fb, int l, int k, int i)
 {
 	int j, x = 0;
 
 	for (j = 0; j < 4; j++) {
-		int m = (l >> (8 * i) & 0xff) + calc_bias(priv, k, i, j);
+		int m = (l >> (8 * i) & 0xff) + calc_bias(fb, k, i, j);
 
 		x |= (0x80 | clamp(m, 0, 0x1f)) << (8 * j);
 	}
@@ -90,10 +90,10 @@ int
 nv30_fb_init(struct nvkm_object *object)
 {
 	struct nvkm_device *device = nv_device(object);
-	struct nv04_fb_priv *priv = (void *)object;
+	struct nvkm_fb *fb = (void *)object;
 	int ret, i, j;
 
-	ret = nvkm_fb_init(&priv->base);
+	ret = nvkm_fb_init(fb);
 	if (ret)
 		return ret;
 
@@ -103,16 +103,16 @@ nv30_fb_init(struct nvkm_object *object)
 	    device->chipset == 0x35) {
 		/* Related to ROP count */
 		int n = (device->chipset == 0x31 ? 2 : 4);
-		int l = nv_rd32(priv, 0x1003d0);
+		int l = nv_rd32(fb, 0x1003d0);
 
 		for (i = 0; i < n; i++) {
 			for (j = 0; j < 3; j++)
-				nv_wr32(priv, 0x10037c + 0xc * i + 0x4 * j,
-					calc_ref(priv, l, 0, j));
+				nv_wr32(fb, 0x10037c + 0xc * i + 0x4 * j,
+					calc_ref(fb, l, 0, j));
 
 			for (j = 0; j < 2; j++)
-				nv_wr32(priv, 0x1003ac + 0x8 * i + 0x4 * j,
-					calc_ref(priv, l, 1, j));
+				nv_wr32(fb, 0x1003ac + 0x8 * i + 0x4 * j,
+					calc_ref(fb, l, 1, j));
 		}
 	}
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c

@@ -26,12 +26,12 @@
 #include "nv04.h"
 
 static void
-nv35_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags,
+nv35_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags,
 		  struct nvkm_fb_tile *tile)
 {
 	u32 tiles = DIV_ROUND_UP(size, 0x40);
-	u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
-	if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
+	u32 tags  = round_up(tiles / fb->ram->parts, 0x40);
+	if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
 		if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */
 		else           tile->zcomp |= 0x08000000; /* Z24S8 */
 		tile->zcomp |= ((tile->tag->offset           ) >> 6);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c

@@ -26,12 +26,12 @@
 #include "nv04.h"
 
 static void
-nv36_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags,
+nv36_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags,
 		  struct nvkm_fb_tile *tile)
 {
 	u32 tiles = DIV_ROUND_UP(size, 0x40);
-	u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
-	if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
+	u32 tags  = round_up(tiles / fb->ram->parts, 0x40);
+	if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
 		if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */
 		else           tile->zcomp |= 0x20000000; /* Z24S8 */
 		tile->zcomp |= ((tile->tag->offset           ) >> 6);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c

@@ -26,13 +26,13 @@
 #include "nv04.h"
 
 void
-nv40_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags,
+nv40_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags,
 		  struct nvkm_fb_tile *tile)
 {
 	u32 tiles = DIV_ROUND_UP(size, 0x80);
-	u32 tags  = round_up(tiles / pfb->ram->parts, 0x100);
+	u32 tags  = round_up(tiles / fb->ram->parts, 0x100);
 	if ( (flags & 2) &&
-	    !nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
+	    !nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
 		tile->zcomp  = 0x28000000; /* Z24S8_SPLIT_GRAD */
 		tile->zcomp |= ((tile->tag->offset           ) >> 8);
 		tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13;
@@ -45,14 +45,14 @@ nv40_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags,
 static int
 nv40_fb_init(struct nvkm_object *object)
 {
-	struct nv04_fb_priv *priv = (void *)object;
+	struct nvkm_fb *fb = (void *)object;
 	int ret;
 
-	ret = nvkm_fb_init(&priv->base);
+	ret = nvkm_fb_init(fb);
 	if (ret)
 		return ret;
 
-	nv_mask(priv, 0x10033c, 0x00008000, 0x00000000);
+	nv_mask(fb, 0x10033c, 0x00008000, 0x00000000);
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c

@@ -26,26 +26,26 @@
 #include "nv04.h"
 
 void
-nv41_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
+nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
 {
-	nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit);
-	nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch);
-	nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr);
-	nv_rd32(pfb, 0x100600 + (i * 0x10));
-	nv_wr32(pfb, 0x100700 + (i * 0x04), tile->zcomp);
+	nv_wr32(fb, 0x100604 + (i * 0x10), tile->limit);
+	nv_wr32(fb, 0x100608 + (i * 0x10), tile->pitch);
+	nv_wr32(fb, 0x100600 + (i * 0x10), tile->addr);
+	nv_rd32(fb, 0x100600 + (i * 0x10));
+	nv_wr32(fb, 0x100700 + (i * 0x04), tile->zcomp);
 }
 
 int
 nv41_fb_init(struct nvkm_object *object)
 {
-	struct nv04_fb_priv *priv = (void *)object;
+	struct nvkm_fb *fb = (void *)object;
 	int ret;
 
-	ret = nvkm_fb_init(&priv->base);
+	ret = nvkm_fb_init(fb);
 	if (ret)
 		return ret;
 
-	nv_wr32(priv, 0x100800, 0x00000001);
+	nv_wr32(fb, 0x100800, 0x00000001);
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c

@@ -26,7 +26,7 @@
 #include "nv04.h"
 
 static void
-nv44_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
+nv44_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch,
 		  u32 flags, struct nvkm_fb_tile *tile)
 {
 	tile->addr  = 0x00000001; /* mode = vram */
@@ -36,26 +36,26 @@ nv44_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
 }
 
 void
-nv44_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
+nv44_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
 {
-	nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit);
-	nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch);
-	nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr);
-	nv_rd32(pfb, 0x100600 + (i * 0x10));
+	nv_wr32(fb, 0x100604 + (i * 0x10), tile->limit);
+	nv_wr32(fb, 0x100608 + (i * 0x10), tile->pitch);
+	nv_wr32(fb, 0x100600 + (i * 0x10), tile->addr);
+	nv_rd32(fb, 0x100600 + (i * 0x10));
 }
 
 int
 nv44_fb_init(struct nvkm_object *object)
 {
-	struct nv04_fb_priv *priv = (void *)object;
+	struct nvkm_fb *fb = (void *)object;
 	int ret;
 
-	ret = nvkm_fb_init(&priv->base);
+	ret = nvkm_fb_init(fb);
 	if (ret)
 		return ret;
 
-	nv_wr32(priv, 0x100850, 0x80000000);
-	nv_wr32(priv, 0x100800, 0x00000001);
+	nv_wr32(fb, 0x100850, 0x80000000);
+	nv_wr32(fb, 0x100800, 0x00000001);
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c

@@ -26,7 +26,7 @@
 #include "nv04.h"
 
 void
-nv46_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
+nv46_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch,
 		  u32 flags, struct nvkm_fb_tile *tile)
 {
 	/* for performance, select alternate bank offset for zeta */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c

@@ -40,7 +40,7 @@ nv50_fb_memtype[0x80] = {
 };
 
 bool
-nv50_fb_memtype_valid(struct nvkm_fb *pfb, u32 memtype)
+nv50_fb_memtype_valid(struct nvkm_fb *fb, u32 memtype)
 {
 	return nv50_fb_memtype[(memtype & 0xff00) >> 8] != 0;
 }
@@ -146,23 +146,23 @@ nv50_fb_intr(struct nvkm_subdev *subdev)
 {
 	struct nvkm_device *device = nv_device(subdev);
 	struct nvkm_engine *engine;
-	struct nv50_fb_priv *priv = (void *)subdev;
+	struct nv50_fb *fb = (void *)subdev;
 	const struct nvkm_enum *en, *cl;
 	struct nvkm_object *engctx = NULL;
 	u32 trap[6], idx, chan;
 	u8 st0, st1, st2, st3;
 	int i;
 
-	idx = nv_rd32(priv, 0x100c90);
+	idx = nv_rd32(fb, 0x100c90);
 	if (!(idx & 0x80000000))
 		return;
 	idx &= 0x00ffffff;
 
 	for (i = 0; i < 6; i++) {
-		nv_wr32(priv, 0x100c90, idx | i << 24);
-		trap[i] = nv_rd32(priv, 0x100c94);
+		nv_wr32(fb, 0x100c90, idx | i << 24);
+		trap[i] = nv_rd32(fb, 0x100c94);
 	}
-	nv_wr32(priv, 0x100c90, idx | 0x80000000);
+	nv_wr32(fb, 0x100c90, idx | 0x80000000);
 
 	/* decode status bits into something more useful */
 	if (device->chipset  < 0xa3 ||
@@ -203,7 +203,7 @@ nv50_fb_intr(struct nvkm_subdev *subdev)
 			en = orig_en;
 	}
 
-	nv_error(priv, "trapped %s at 0x%02x%04x%04x on channel 0x%08x [%s] ",
+	nv_error(fb, "trapped %s at 0x%02x%04x%04x on channel 0x%08x [%s] ",
 		 (trap[5] & 0x00000100) ? "read" : "write",
 		 trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, chan,
 		 nvkm_client_name(engctx));
@@ -243,26 +243,26 @@ nv50_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	     struct nvkm_object **pobject)
 {
 	struct nvkm_device *device = nv_device(parent);
-	struct nv50_fb_priv *priv;
+	struct nv50_fb *fb;
 	int ret;
 
-	ret = nvkm_fb_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
+	ret = nvkm_fb_create(parent, engine, oclass, &fb);
+	*pobject = nv_object(fb);
 	if (ret)
 		return ret;
 
-	priv->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
-	if (priv->r100c08_page) {
-		priv->r100c08 = dma_map_page(nv_device_base(device),
-					     priv->r100c08_page, 0, PAGE_SIZE,
+	fb->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
+	if (fb->r100c08_page) {
+		fb->r100c08 = dma_map_page(nv_device_base(device),
+					     fb->r100c08_page, 0, PAGE_SIZE,
 					     DMA_BIDIRECTIONAL);
-		if (dma_mapping_error(nv_device_base(device), priv->r100c08))
+		if (dma_mapping_error(nv_device_base(device), fb->r100c08))
 			return -EFAULT;
 	} else {
-		nv_warn(priv, "failed 0x100c08 page alloc\n");
+		nv_warn(fb, "failed 0x100c08 page alloc\n");
 	}
 
-	nv_subdev(priv)->intr = nv50_fb_intr;
+	nv_subdev(fb)->intr = nv50_fb_intr;
 	return 0;
 }
 
@@ -270,25 +270,25 @@ void
 nv50_fb_dtor(struct nvkm_object *object)
 {
 	struct nvkm_device *device = nv_device(object);
-	struct nv50_fb_priv *priv = (void *)object;
+	struct nv50_fb *fb = (void *)object;
 
-	if (priv->r100c08_page) {
-		dma_unmap_page(nv_device_base(device), priv->r100c08, PAGE_SIZE,
+	if (fb->r100c08_page) {
+		dma_unmap_page(nv_device_base(device), fb->r100c08, PAGE_SIZE,
 			       DMA_BIDIRECTIONAL);
-		__free_page(priv->r100c08_page);
+		__free_page(fb->r100c08_page);
 	}
 
-	nvkm_fb_destroy(&priv->base);
+	nvkm_fb_destroy(&fb->base);
 }
 
 int
 nv50_fb_init(struct nvkm_object *object)
 {
 	struct nv50_fb_impl *impl = (void *)object->oclass;
-	struct nv50_fb_priv *priv = (void *)object;
+	struct nv50_fb *fb = (void *)object;
 	int ret;
 
-	ret = nvkm_fb_init(&priv->base);
+	ret = nvkm_fb_init(&fb->base);
 	if (ret)
 		return ret;
 
@@ -296,11 +296,11 @@ nv50_fb_init(struct nvkm_object *object)
 	 * scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
 	 * cause IOMMU "read from address 0" errors (rh#561267)
 	 */
-	nv_wr32(priv, 0x100c08, priv->r100c08 >> 8);
+	nv_wr32(fb, 0x100c08, fb->r100c08 >> 8);
 
 	/* This is needed to get meaningful information from 100c90
 	 * on traps. No idea what these values mean exactly. */
-	nv_wr32(priv, 0x100c90, impl->trap);
+	nv_wr32(fb, 0x100c90, impl->trap);
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h

@@ -2,7 +2,7 @@
 #define __NVKM_FB_NV50_H__
 #include "priv.h"
 
-struct nv50_fb_priv {
+struct nv50_fb {
 	struct nvkm_fb base;
 	struct page *r100c08_page;
 	dma_addr_t r100c08;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h

@@ -42,16 +42,16 @@ int nvkm_gddr5_calc(struct nvkm_ram *ram, bool nuts);
 #define nvkm_fb_create(p,e,c,d)                                             \
 	nvkm_fb_create_((p), (e), (c), sizeof(**d), (void **)d)
 #define nvkm_fb_destroy(p) ({                                               \
-	struct nvkm_fb *pfb = (p);                                          \
-	_nvkm_fb_dtor(nv_object(pfb));                                      \
+	struct nvkm_fb *_fb = (p);                                          \
+	_nvkm_fb_dtor(nv_object(_fb));                                      \
 })
 #define nvkm_fb_init(p) ({                                                  \
-	struct nvkm_fb *pfb = (p);                                          \
-	_nvkm_fb_init(nv_object(pfb));                                      \
+	struct nvkm_fb *_fb = (p);                                          \
+	_nvkm_fb_init(nv_object(_fb));                                      \
 })
 #define nvkm_fb_fini(p,s) ({                                                \
-	struct nvkm_fb *pfb = (p);                                          \
-	_nvkm_fb_fini(nv_object(pfb), (s));                                 \
+	struct nvkm_fb *_fb = (p);                                          \
+	_nvkm_fb_fini(nv_object(_fb), (s));                                 \
 })
 
 int nvkm_fb_create_(struct nvkm_object *, struct nvkm_object *,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h

@@ -4,7 +4,7 @@
 
 struct ramfuc {
 	struct nvkm_memx *memx;
-	struct nvkm_fb *pfb;
+	struct nvkm_fb *fb;
 	int sequence;
 };
 
@@ -54,9 +54,9 @@ ramfuc_reg(u32 addr)
 }
 
 static inline int
-ramfuc_init(struct ramfuc *ram, struct nvkm_fb *pfb)
+ramfuc_init(struct ramfuc *ram, struct nvkm_fb *fb)
 {
-	struct nvkm_pmu *pmu = nvkm_pmu(pfb);
+	struct nvkm_pmu *pmu = nvkm_pmu(fb);
 	int ret;
 
 	ret = nvkm_memx_init(pmu, &ram->memx);
@@ -64,7 +64,7 @@ ramfuc_init(struct ramfuc *ram, struct nvkm_fb *pfb)
 		return ret;
 
 	ram->sequence++;
-	ram->pfb = pfb;
+	ram->fb = fb;
 	return 0;
 }
 
@@ -72,9 +72,9 @@ static inline int
 ramfuc_exec(struct ramfuc *ram, bool exec)
 {
 	int ret = 0;
-	if (ram->pfb) {
+	if (ram->fb) {
 		ret = nvkm_memx_fini(&ram->memx, exec);
-		ram->pfb = NULL;
+		ram->fb = NULL;
 	}
 	return ret;
 }
@@ -83,7 +83,7 @@ static inline u32
 ramfuc_rd32(struct ramfuc *ram, struct ramfuc_reg *reg)
 {
 	if (reg->sequence != ram->sequence)
-		reg->data = nv_rd32(ram->pfb, reg->addr);
+		reg->data = nv_rd32(ram->fb, reg->addr);
 	return reg->data;
 }
 
@@ -144,9 +144,9 @@ ramfuc_train(struct ramfuc *ram)
 }
 
 static inline int
-ramfuc_train_result(struct nvkm_fb *pfb, u32 *result, u32 rsize)
+ramfuc_train_result(struct nvkm_fb *fb, u32 *result, u32 rsize)
 {
-	struct nvkm_pmu *pmu = nvkm_pmu(pfb);
+	struct nvkm_pmu *pmu = nvkm_pmu(fb);
 
 	return nvkm_memx_train_result(pmu, result, rsize);
 }

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c

@@ -107,9 +107,9 @@ static void
 gf100_ram_train(struct gf100_ramfuc *fuc, u32 magic)
 {
 	struct gf100_ram *ram = container_of(fuc, typeof(*ram), fuc);
-	struct nvkm_fb *pfb = nvkm_fb(ram);
-	u32 part = nv_rd32(pfb, 0x022438), i;
-	u32 mask = nv_rd32(pfb, 0x022554);
+	struct nvkm_fb *fb = nvkm_fb(ram);
+	u32 part = nv_rd32(fb, 0x022438), i;
+	u32 mask = nv_rd32(fb, 0x022554);
 	u32 addr = 0x110974;
 
 	ram_wr32(fuc, 0x10f910, magic);
@@ -123,11 +123,11 @@ gf100_ram_train(struct gf100_ramfuc *fuc, u32 magic)
 }
 
 static int
-gf100_ram_calc(struct nvkm_fb *pfb, u32 freq)
+gf100_ram_calc(struct nvkm_fb *fb, u32 freq)
 {
-	struct nvkm_clk *clk = nvkm_clk(pfb);
-	struct nvkm_bios *bios = nvkm_bios(pfb);
-	struct gf100_ram *ram = (void *)pfb->ram;
+	struct nvkm_clk *clk = nvkm_clk(fb);
+	struct nvkm_bios *bios = nvkm_bios(fb);
+	struct gf100_ram *ram = (void *)fb->ram;
 	struct gf100_ramfuc *fuc = &ram->fuc;
 	struct nvbios_ramcfg cfg;
 	u8  ver, cnt, len, strap;
@@ -144,20 +144,20 @@ gf100_ram_calc(struct nvkm_fb *pfb, u32 freq)
 	rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size,
 				      &cnt, &ramcfg.size, &cfg);
 	if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) {
-		nv_error(pfb, "invalid/missing rammap entry\n");
+		nv_error(fb, "invalid/missing rammap entry\n");
 		return -EINVAL;
 	}
 
 	/* locate specific data set for the attached memory */
-	strap = nvbios_ramcfg_index(nv_subdev(pfb));
+	strap = nvbios_ramcfg_index(nv_subdev(fb));
 	if (strap >= cnt) {
-		nv_error(pfb, "invalid ramcfg strap\n");
+		nv_error(fb, "invalid ramcfg strap\n");
 		return -EINVAL;
 	}
 
 	ramcfg.data = rammap.data + rammap.size + (strap * ramcfg.size);
 	if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) {
-		nv_error(pfb, "invalid/missing ramcfg entry\n");
+		nv_error(fb, "invalid/missing ramcfg entry\n");
 		return -EINVAL;
 	}
 
@@ -167,14 +167,14 @@ gf100_ram_calc(struct nvkm_fb *pfb, u32 freq)
 		timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size,
 					      &cnt, &len);
 		if (!timing.data || ver != 0x10 || timing.size < 0x19) {
-			nv_error(pfb, "invalid/missing timing entry\n");
+			nv_error(fb, "invalid/missing timing entry\n");
 			return -EINVAL;
 		}
 	} else {
 		timing.data = 0;
 	}
 
-	ret = ram_init(fuc, pfb);
+	ret = ram_init(fuc, fb);
 	if (ret)
 		return ret;
 
@@ -209,10 +209,10 @@ gf100_ram_calc(struct nvkm_fb *pfb, u32 freq)
 
 	if (mode == 1 && from == 0) {
 		/* calculate refpll */
-		ret = gt215_pll_calc(nv_subdev(pfb), &ram->refpll,
+		ret = gt215_pll_calc(nv_subdev(fb), &ram->refpll,
 				     ram->mempll.refclk, &N1, NULL, &M1, &P);
 		if (ret <= 0) {
-			nv_error(pfb, "unable to calc refpll\n");
+			nv_error(fb, "unable to calc refpll\n");
 			return ret ? ret : -ERANGE;
 		}
 
@@ -224,10 +224,10 @@ gf100_ram_calc(struct nvkm_fb *pfb, u32 freq)
 		ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
 
 		/* calculate mempll */
-		ret = gt215_pll_calc(nv_subdev(pfb), &ram->mempll, freq,
+		ret = gt215_pll_calc(nv_subdev(fb), &ram->mempll, freq,
 				     &N1, NULL, &M1, &P);
 		if (ret <= 0) {
-			nv_error(pfb, "unable to calc refpll\n");
+			nv_error(fb, "unable to calc refpll\n");
 			return ret ? ret : -ERANGE;
 		}
 
@@ -401,19 +401,19 @@ gf100_ram_calc(struct nvkm_fb *pfb, u32 freq)
 }
 
 static int
-gf100_ram_prog(struct nvkm_fb *pfb)
+gf100_ram_prog(struct nvkm_fb *fb)
 {
-	struct nvkm_device *device = nv_device(pfb);
-	struct gf100_ram *ram = (void *)pfb->ram;
+	struct nvkm_device *device = nv_device(fb);
+	struct gf100_ram *ram = (void *)fb->ram;
 	struct gf100_ramfuc *fuc = &ram->fuc;
 	ram_exec(fuc, nvkm_boolopt(device->cfgopt, "NvMemExec", true));
 	return 0;
 }
 
 static void
-gf100_ram_tidy(struct nvkm_fb *pfb)
+gf100_ram_tidy(struct nvkm_fb *fb)
 {
-	struct gf100_ram *ram = (void *)pfb->ram;
+	struct gf100_ram *ram = (void *)fb->ram;
 	struct gf100_ramfuc *fuc = &ram->fuc;
 	ram_exec(fuc, false);
 }
@@ -421,29 +421,29 @@ gf100_ram_tidy(struct nvkm_fb *pfb)
 extern const u8 gf100_pte_storage_type_map[256];
 
 void
-gf100_ram_put(struct nvkm_fb *pfb, struct nvkm_mem **pmem)
+gf100_ram_put(struct nvkm_fb *fb, struct nvkm_mem **pmem)
 {
-	struct nvkm_ltc *ltc = nvkm_ltc(pfb);
+	struct nvkm_ltc *ltc = nvkm_ltc(fb);
 	struct nvkm_mem *mem = *pmem;
 
 	*pmem = NULL;
 	if (unlikely(mem == NULL))
 		return;
 
-	mutex_lock(&pfb->base.mutex);
+	mutex_lock(&fb->subdev.mutex);
 	if (mem->tag)
 		ltc->tags_free(ltc, &mem->tag);
-	__nv50_ram_put(pfb, mem);
-	mutex_unlock(&pfb->base.mutex);
+	__nv50_ram_put(fb, mem);
+	mutex_unlock(&fb->subdev.mutex);
 
 	kfree(mem);
 }
 
 int
-gf100_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin,
+gf100_ram_get(struct nvkm_fb *fb, u64 size, u32 align, u32 ncmin,
 	      u32 memtype, struct nvkm_mem **pmem)
 {
-	struct nvkm_mm *mm = &pfb->vram;
+	struct nvkm_mm *mm = &fb->vram;
 	struct nvkm_mm_node *r;
 	struct nvkm_mem *mem;
 	int type = (memtype & 0x0ff);
@@ -464,9 +464,9 @@ gf100_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin,
 	INIT_LIST_HEAD(&mem->regions);
 	mem->size = size;
 
-	mutex_lock(&pfb->base.mutex);
+	mutex_lock(&fb->subdev.mutex);
 	if (comp) {
-		struct nvkm_ltc *ltc = nvkm_ltc(pfb);
+		struct nvkm_ltc *ltc = nvkm_ltc(fb);
 
 		/* compression only works with lpages */
 		if (align == (1 << (17 - 12))) {
@@ -485,15 +485,15 @@ gf100_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin,
 		else
 			ret = nvkm_mm_head(mm, 0, 1, size, ncmin, align, &r);
 		if (ret) {
-			mutex_unlock(&pfb->base.mutex);
-			pfb->ram->put(pfb, &mem);
+			mutex_unlock(&fb->subdev.mutex);
+			fb->ram->put(fb, &mem);
 			return ret;
 		}
 
 		list_add_tail(&r->rl_entry, &mem->regions);
 		size -= r->length;
 	} while (size);
-	mutex_unlock(&pfb->base.mutex);
+	mutex_unlock(&fb->subdev.mutex);
 
 	r = list_first_entry(&mem->regions, struct nvkm_mm_node, rl_entry);
 	mem->offset = (u64)r->offset << 12;
@@ -506,14 +506,14 @@ gf100_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine,
 		  struct nvkm_oclass *oclass, u32 maskaddr, int size,
 		  void **pobject)
 {
-	struct nvkm_fb *pfb = nvkm_fb(parent);
-	struct nvkm_bios *bios = nvkm_bios(pfb);
+	struct nvkm_fb *fb = nvkm_fb(parent);
+	struct nvkm_bios *bios = nvkm_bios(fb);
 	struct nvkm_ram *ram;
 	const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
 	const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
-	u32 parts = nv_rd32(pfb, 0x022438);
-	u32 pmask = nv_rd32(pfb, maskaddr);
-	u32 bsize = nv_rd32(pfb, 0x10f20c);
+	u32 parts = nv_rd32(fb, 0x022438);
+	u32 pmask = nv_rd32(fb, maskaddr);
+	u32 bsize = nv_rd32(fb, 0x10f20c);
 	u32 offset, length;
 	bool uniform = true;
 	int ret, part;
@@ -523,23 +523,23 @@ gf100_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine,
 	if (ret)
 		return ret;
 
-	nv_debug(pfb, "0x100800: 0x%08x\n", nv_rd32(pfb, 0x100800));
-	nv_debug(pfb, "parts 0x%08x mask 0x%08x\n", parts, pmask);
+	nv_debug(fb, "0x100800: 0x%08x\n", nv_rd32(fb, 0x100800));
+	nv_debug(fb, "parts 0x%08x mask 0x%08x\n", parts, pmask);
 
 	ram->type = nvkm_fb_bios_memtype(bios);
-	ram->ranks = (nv_rd32(pfb, 0x10f200) & 0x00000004) ? 2 : 1;
+	ram->ranks = (nv_rd32(fb, 0x10f200) & 0x00000004) ? 2 : 1;
 
 	/* read amount of vram attached to each memory controller */
 	for (part = 0; part < parts; part++) {
 		if (!(pmask & (1 << part))) {
-			u32 psize = nv_rd32(pfb, 0x11020c + (part * 0x1000));
+			u32 psize = nv_rd32(fb, 0x11020c + (part * 0x1000));
 			if (psize != bsize) {
 				if (psize < bsize)
 					bsize = psize;
 				uniform = false;
 			}
 
-			nv_debug(pfb, "%d: mem_amount 0x%08x\n", part, psize);
+			nv_debug(fb, "%d: mem_amount 0x%08x\n", part, psize);
 			ram->size += (u64)psize << 20;
 		}
 	}
@@ -548,10 +548,10 @@ gf100_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine,
 	if (uniform) {
 		offset = rsvd_head;
 		length = (ram->size >> 12) - rsvd_head - rsvd_tail;
-		ret = nvkm_mm_init(&pfb->vram, offset, length, 1);
+		ret = nvkm_mm_init(&fb->vram, offset, length, 1);
 	} else {
 		/* otherwise, address lowest common amount from 0GiB */
-		ret = nvkm_mm_init(&pfb->vram, rsvd_head,
+		ret = nvkm_mm_init(&fb->vram, rsvd_head,
 				   (bsize << 8) * parts - rsvd_head, 1);
 		if (ret)
 			return ret;
@@ -560,9 +560,9 @@ gf100_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine,
 		offset = (0x0200000000ULL >> 12) + (bsize << 8);
 		length = (ram->size >> 12) - ((bsize * parts) << 8) - rsvd_tail;
 
-		ret = nvkm_mm_init(&pfb->vram, offset, length, 1);
+		ret = nvkm_mm_init(&fb->vram, offset, length, 1);
 		if (ret)
-			nvkm_mm_fini(&pfb->vram);
+			nvkm_mm_fini(&fb->vram);
 	}
 
 	if (ret)
@@ -576,7 +576,7 @@ gf100_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine,
 static int
 gf100_ram_init(struct nvkm_object *object)
 {
-	struct nvkm_fb *pfb = (void *)object->parent;
+	struct nvkm_fb *fb = (void *)object->parent;
 	struct gf100_ram *ram = (void *)object;
 	int ret, i;
 
@@ -601,16 +601,16 @@ gf100_ram_init(struct nvkm_object *object)
 		};
 
 		for (i = 0; i < 0x30; i++) {
-			nv_wr32(pfb, 0x10f968, 0x00000000 | (i << 8));
-			nv_wr32(pfb, 0x10f96c, 0x00000000 | (i << 8));
-			nv_wr32(pfb, 0x10f920, 0x00000100 | train0[i % 12]);
-			nv_wr32(pfb, 0x10f924, 0x00000100 | train0[i % 12]);
-			nv_wr32(pfb, 0x10f918,              train1[i % 12]);
-			nv_wr32(pfb, 0x10f91c,              train1[i % 12]);
-			nv_wr32(pfb, 0x10f920, 0x00000000 | train0[i % 12]);
-			nv_wr32(pfb, 0x10f924, 0x00000000 | train0[i % 12]);
-			nv_wr32(pfb, 0x10f918,              train1[i % 12]);
-			nv_wr32(pfb, 0x10f91c,              train1[i % 12]);
+			nv_wr32(fb, 0x10f968, 0x00000000 | (i << 8));
+			nv_wr32(fb, 0x10f96c, 0x00000000 | (i << 8));
+			nv_wr32(fb, 0x10f920, 0x00000100 | train0[i % 12]);
+			nv_wr32(fb, 0x10f924, 0x00000100 | train0[i % 12]);
+			nv_wr32(fb, 0x10f918,              train1[i % 12]);
+			nv_wr32(fb, 0x10f91c,              train1[i % 12]);
+			nv_wr32(fb, 0x10f920, 0x00000000 | train0[i % 12]);
+			nv_wr32(fb, 0x10f924, 0x00000000 | train0[i % 12]);
+			nv_wr32(fb, 0x10f918,              train1[i % 12]);
+			nv_wr32(fb, 0x10f91c,              train1[i % 12]);
 		}
 	}	break;
 	default:

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c

@@ -23,16 +23,12 @@
  */
 #include "gf100.h"
 
-struct gm107_ram {
-	struct nvkm_ram base;
-};
-
 static int
 gm107_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	       struct nvkm_oclass *oclass, void *data, u32 size,
 	       struct nvkm_object **pobject)
 {
-	struct gm107_ram *ram;
+	struct nvkm_ram *ram;
 	int ret;
 
 	ret = gf100_ram_create(parent, engine, oclass, 0x021c14, &ram);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c

@@ -23,7 +23,7 @@
  */
 #include "nv50.h"
 
-struct mcp77_ram_priv {
+struct mcp77_ram {
 	struct nvkm_ram base;
 	u64 poller_base;
 };
@@ -35,58 +35,58 @@ mcp77_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 {
 	u32 rsvd_head = ( 256 * 1024); /* vga memory */
 	u32 rsvd_tail = (1024 * 1024); /* vbios etc */
-	struct nvkm_fb *pfb = nvkm_fb(parent);
-	struct mcp77_ram_priv *priv;
+	struct nvkm_fb *fb = nvkm_fb(parent);
+	struct mcp77_ram *ram;
 	int ret;
 
-	ret = nvkm_ram_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
+	ret = nvkm_ram_create(parent, engine, oclass, &ram);
+	*pobject = nv_object(fb);
 	if (ret)
 		return ret;
 
-	priv->base.type   = NV_MEM_TYPE_STOLEN;
-	priv->base.stolen = (u64)nv_rd32(pfb, 0x100e10) << 12;
-	priv->base.size   = (u64)nv_rd32(pfb, 0x100e14) << 12;
+	ram->base.type   = NV_MEM_TYPE_STOLEN;
+	ram->base.stolen = (u64)nv_rd32(fb, 0x100e10) << 12;
+	ram->base.size   = (u64)nv_rd32(fb, 0x100e14) << 12;
 
 	rsvd_tail += 0x1000;
-	priv->poller_base = priv->base.size - rsvd_tail;
+	ram->poller_base = ram->base.size - rsvd_tail;
 
-	ret = nvkm_mm_init(&pfb->vram, rsvd_head >> 12,
-			   (priv->base.size  - (rsvd_head + rsvd_tail)) >> 12,
+	ret = nvkm_mm_init(&fb->vram, rsvd_head >> 12,
+			   (ram->base.size  - (rsvd_head + rsvd_tail)) >> 12,
 			   1);
 	if (ret)
 		return ret;
 
-	priv->base.get = nv50_ram_get;
-	priv->base.put = nv50_ram_put;
+	ram->base.get = nv50_ram_get;
+	ram->base.put = nv50_ram_put;
 	return 0;
 }
 
 static int
 mcp77_ram_init(struct nvkm_object *object)
 {
-	struct nvkm_fb *pfb = nvkm_fb(object);
-	struct mcp77_ram_priv *priv = (void *)object;
+	struct nvkm_fb *fb = nvkm_fb(object);
+	struct mcp77_ram *ram = (void *)object;
 	int ret;
 	u64 dniso, hostnb, flush;
 
-	ret = nvkm_ram_init(&priv->base);
+	ret = nvkm_ram_init(&ram->base);
 	if (ret)
 		return ret;
 
-	dniso  = ((priv->base.size - (priv->poller_base + 0x00)) >> 5) - 1;
-	hostnb = ((priv->base.size - (priv->poller_base + 0x20)) >> 5) - 1;
-	flush  = ((priv->base.size - (priv->poller_base + 0x40)) >> 5) - 1;
+	dniso  = ((ram->base.size - (ram->poller_base + 0x00)) >> 5) - 1;
+	hostnb = ((ram->base.size - (ram->poller_base + 0x20)) >> 5) - 1;
+	flush  = ((ram->base.size - (ram->poller_base + 0x40)) >> 5) - 1;
 
 	/* Enable NISO poller for various clients and set their associated
 	 * read address, only for MCP77/78 and MCP79/7A. (fd#25701)
 	 */
-	nv_wr32(pfb, 0x100c18, dniso);
-	nv_mask(pfb, 0x100c14, 0x00000000, 0x00000001);
-	nv_wr32(pfb, 0x100c1c, hostnb);
-	nv_mask(pfb, 0x100c14, 0x00000000, 0x00000002);
-	nv_wr32(pfb, 0x100c24, flush);
-	nv_mask(pfb, 0x100c14, 0x00000000, 0x00010000);
+	nv_wr32(fb, 0x100c18, dniso);
+	nv_mask(fb, 0x100c14, 0x00000000, 0x00000001);
+	nv_wr32(fb, 0x100c1c, hostnb);
+	nv_mask(fb, 0x100c14, 0x00000000, 0x00000002);
+	nv_wr32(fb, 0x100c24, flush);
+	nv_mask(fb, 0x100c14, 0x00000000, 0x00010000);
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c

@@ -29,9 +29,9 @@ nv04_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 		struct nvkm_oclass *oclass, void *data, u32 size,
 		struct nvkm_object **pobject)
 {
-	struct nvkm_fb *pfb = nvkm_fb(parent);
+	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nvkm_ram *ram;
-	u32 boot0 = nv_rd32(pfb, NV04_PFB_BOOT_0);
+	u32 boot0 = nv_rd32(fb, NV04_PFB_BOOT_0);
 	int ret;
 
 	ret = nvkm_ram_create(parent, engine, oclass, &ram);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c

@@ -28,9 +28,9 @@ nv10_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 		struct nvkm_oclass *oclass, void *data, u32 size,
 		struct nvkm_object **pobject)
 {
-	struct nvkm_fb *pfb = nvkm_fb(parent);
+	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nvkm_ram *ram;
-	u32 cfg0 = nv_rd32(pfb, 0x100200);
+	u32 cfg0 = nv_rd32(fb, 0x100200);
 	int ret;
 
 	ret = nvkm_ram_create(parent, engine, oclass, &ram);
@@ -43,7 +43,7 @@ nv10_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 	else
 		ram->type = NV_MEM_TYPE_SDRAM;
 
-	ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000;
+	ram->size = nv_rd32(fb, 0x10020c) & 0xff000000;
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c

@@ -28,7 +28,7 @@ nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 		struct nvkm_oclass *oclass, void *data, u32 size,
 		struct nvkm_object **pobject)
 {
-	struct nvkm_fb *pfb = nvkm_fb(parent);
+	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nvkm_ram *ram;
 	struct pci_dev *bridge;
 	u32 mem, mib;
@@ -36,7 +36,7 @@ nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 
 	bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
 	if (!bridge) {
-		nv_fatal(pfb, "no bridge device\n");
+		nv_fatal(fb, "no bridge device\n");
 		return -ENODEV;
 	}
 
@@ -45,7 +45,7 @@ nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 	if (ret)
 		return ret;
 
-	if (nv_device(pfb)->chipset == 0x1a) {
+	if (nv_device(fb)->chipset == 0x1a) {
 		pci_read_config_dword(bridge, 0x7c, &mem);
 		mib = ((mem >> 6) & 31) + 1;
 	} else {

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c

@@ -28,9 +28,9 @@ nv20_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 		struct nvkm_oclass *oclass, void *data, u32 size,
 		struct nvkm_object **pobject)
 {
-	struct nvkm_fb *pfb = nvkm_fb(parent);
+	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nvkm_ram *ram;
-	u32 pbus1218 = nv_rd32(pfb, 0x001218);
+	u32 pbus1218 = nv_rd32(fb, 0x001218);
 	int ret;
 
 	ret = nvkm_ram_create(parent, engine, oclass, &ram);
@@ -44,9 +44,9 @@ nv20_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 	case 0x00000200: ram->type = NV_MEM_TYPE_GDDR3; break;
 	case 0x00000300: ram->type = NV_MEM_TYPE_GDDR2; break;
 	}
-	ram->size  = (nv_rd32(pfb, 0x10020c) & 0xff000000);
-	ram->parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
-	ram->tags  = nv_rd32(pfb, 0x100320);
+	ram->size  = (nv_rd32(fb, 0x10020c) & 0xff000000);
+	ram->parts = (nv_rd32(fb, 0x100200) & 0x00000003) + 1;
+	ram->tags  = nv_rd32(fb, 0x100320);
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c

@@ -31,21 +31,21 @@
 #include <subdev/timer.h>
 
 int
-nv40_ram_calc(struct nvkm_fb *pfb, u32 freq)
+nv40_ram_calc(struct nvkm_fb *fb, u32 freq)
 {
-	struct nvkm_bios *bios = nvkm_bios(pfb);
-	struct nv40_ram *ram = (void *)pfb->ram;
+	struct nvkm_bios *bios = nvkm_bios(fb);
+	struct nv40_ram *ram = (void *)fb->ram;
 	struct nvbios_pll pll;
 	int N1, M1, N2, M2;
 	int log2P, ret;
 
 	ret = nvbios_pll_parse(bios, 0x04, &pll);
 	if (ret) {
-		nv_error(pfb, "mclk pll data not found\n");
+		nv_error(fb, "mclk pll data not found\n");
 		return ret;
 	}
 
-	ret = nv04_pll_calc(nv_subdev(pfb), &pll, freq,
+	ret = nv04_pll_calc(nv_subdev(fb), &pll, freq,
 			    &N1, &M1, &N2, &M2, &log2P);
 	if (ret < 0)
 		return ret;
@@ -64,10 +64,10 @@ nv40_ram_calc(struct nvkm_fb *pfb, u32 freq)
 }
 
 int
-nv40_ram_prog(struct nvkm_fb *pfb)
+nv40_ram_prog(struct nvkm_fb *fb)
 {
-	struct nvkm_bios *bios = nvkm_bios(pfb);
-	struct nv40_ram *ram = (void *)pfb->ram;
+	struct nvkm_bios *bios = nvkm_bios(fb);
+	struct nv40_ram *ram = (void *)fb->ram;
 	struct bit_entry M;
 	u32 crtc_mask = 0;
 	u8  sr1[2];
@@ -75,12 +75,12 @@ nv40_ram_prog(struct nvkm_fb *pfb)
 
 	/* determine which CRTCs are active, fetch VGA_SR1 for each */
 	for (i = 0; i < 2; i++) {
-		u32 vbl = nv_rd32(pfb, 0x600808 + (i * 0x2000));
+		u32 vbl = nv_rd32(fb, 0x600808 + (i * 0x2000));
 		u32 cnt = 0;
 		do {
-			if (vbl != nv_rd32(pfb, 0x600808 + (i * 0x2000))) {
-				nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01);
-				sr1[i] = nv_rd08(pfb, 0x0c03c5 + (i * 0x2000));
+			if (vbl != nv_rd32(fb, 0x600808 + (i * 0x2000))) {
+				nv_wr08(fb, 0x0c03c4 + (i * 0x2000), 0x01);
+				sr1[i] = nv_rd08(fb, 0x0c03c5 + (i * 0x2000));
 				if (!(sr1[i] & 0x20))
 					crtc_mask |= (1 << i);
 				break;
@@ -93,53 +93,53 @@ nv40_ram_prog(struct nvkm_fb *pfb)
 	for (i = 0; i < 2; i++) {
 		if (!(crtc_mask & (1 << i)))
 			continue;
-		nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000);
-		nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
-		nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01);
-		nv_wr08(pfb, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20);
+		nv_wait(fb, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000);
+		nv_wait(fb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
+		nv_wr08(fb, 0x0c03c4 + (i * 0x2000), 0x01);
+		nv_wr08(fb, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20);
 	}
 
 	/* prepare ram for reclocking */
-	nv_wr32(pfb, 0x1002d4, 0x00000001); /* precharge */
-	nv_wr32(pfb, 0x1002d0, 0x00000001); /* refresh */
-	nv_wr32(pfb, 0x1002d0, 0x00000001); /* refresh */
-	nv_mask(pfb, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */
-	nv_wr32(pfb, 0x1002dc, 0x00000001); /* enable self-refresh */
+	nv_wr32(fb, 0x1002d4, 0x00000001); /* precharge */
+	nv_wr32(fb, 0x1002d0, 0x00000001); /* refresh */
+	nv_wr32(fb, 0x1002d0, 0x00000001); /* refresh */
+	nv_mask(fb, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */
+	nv_wr32(fb, 0x1002dc, 0x00000001); /* enable self-refresh */
 
 	/* change the PLL of each memory partition */
-	nv_mask(pfb, 0x00c040, 0x0000c000, 0x00000000);
-	switch (nv_device(pfb)->chipset) {
+	nv_mask(fb, 0x00c040, 0x0000c000, 0x00000000);
+	switch (nv_device(fb)->chipset) {
 	case 0x40:
 	case 0x45:
 	case 0x41:
 	case 0x42:
 	case 0x47:
-		nv_mask(pfb, 0x004044, 0xc0771100, ram->ctrl);
-		nv_mask(pfb, 0x00402c, 0xc0771100, ram->ctrl);
-		nv_wr32(pfb, 0x004048, ram->coef);
-		nv_wr32(pfb, 0x004030, ram->coef);
+		nv_mask(fb, 0x004044, 0xc0771100, ram->ctrl);
+		nv_mask(fb, 0x00402c, 0xc0771100, ram->ctrl);
+		nv_wr32(fb, 0x004048, ram->coef);
+		nv_wr32(fb, 0x004030, ram->coef);
 	case 0x43:
 	case 0x49:
 	case 0x4b:
-		nv_mask(pfb, 0x004038, 0xc0771100, ram->ctrl);
-		nv_wr32(pfb, 0x00403c, ram->coef);
+		nv_mask(fb, 0x004038, 0xc0771100, ram->ctrl);
+		nv_wr32(fb, 0x00403c, ram->coef);
 	default:
-		nv_mask(pfb, 0x004020, 0xc0771100, ram->ctrl);
-		nv_wr32(pfb, 0x004024, ram->coef);
+		nv_mask(fb, 0x004020, 0xc0771100, ram->ctrl);
+		nv_wr32(fb, 0x004024, ram->coef);
 		break;
 	}
 	udelay(100);
-	nv_mask(pfb, 0x00c040, 0x0000c000, 0x0000c000);
+	nv_mask(fb, 0x00c040, 0x0000c000, 0x0000c000);
 
 	/* re-enable normal operation of memory controller */
-	nv_wr32(pfb, 0x1002dc, 0x00000000);
-	nv_mask(pfb, 0x100210, 0x80000000, 0x80000000);
+	nv_wr32(fb, 0x1002dc, 0x00000000);
+	nv_mask(fb, 0x100210, 0x80000000, 0x80000000);
 	udelay(100);
 
 	/* execute memory reset script from vbios */
 	if (!bit_entry(bios, 'M', &M)) {
 		struct nvbios_init init = {
-			.subdev = nv_subdev(pfb),
+			.subdev = nv_subdev(fb),
 			.bios = bios,
 			.offset = nv_ro16(bios, M.offset + 0x00),
 			.execute = 1,
@@ -154,16 +154,16 @@ nv40_ram_prog(struct nvkm_fb *pfb)
 	for (i = 0; i < 2; i++) {
 		if (!(crtc_mask & (1 << i)))
 			continue;
-		nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
-		nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01);
-		nv_wr08(pfb, 0x0c03c5 + (i * 0x2000), sr1[i]);
+		nv_wait(fb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
+		nv_wr08(fb, 0x0c03c4 + (i * 0x2000), 0x01);
+		nv_wr08(fb, 0x0c03c5 + (i * 0x2000), sr1[i]);
 	}
 
 	return 0;
 }
 
 void
-nv40_ram_tidy(struct nvkm_fb *pfb)
+nv40_ram_tidy(struct nvkm_fb *fb)
 {
 }
 
@@ -172,9 +172,9 @@ nv40_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 		struct nvkm_oclass *oclass, void *data, u32 size,
 		struct nvkm_object **pobject)
 {
-	struct nvkm_fb *pfb = nvkm_fb(parent);
+	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nv40_ram *ram;
-	u32 pbus1218 = nv_rd32(pfb, 0x001218);
+	u32 pbus1218 = nv_rd32(fb, 0x001218);
 	int ret;
 
 	ret = nvkm_ram_create(parent, engine, oclass, &ram);
@@ -189,9 +189,9 @@ nv40_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 	case 0x00000300: ram->base.type = NV_MEM_TYPE_DDR2; break;
 	}
 
-	ram->base.size  =  nv_rd32(pfb, 0x10020c) & 0xff000000;
-	ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
-	ram->base.tags  =  nv_rd32(pfb, 0x100320);
+	ram->base.size  =  nv_rd32(fb, 0x10020c) & 0xff000000;
+	ram->base.parts = (nv_rd32(fb, 0x100200) & 0x00000003) + 1;
+	ram->base.tags  =  nv_rd32(fb, 0x100320);
 	ram->base.calc = nv40_ram_calc;
 	ram->base.prog = nv40_ram_prog;
 	ram->base.tidy = nv40_ram_tidy;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c

@@ -28,9 +28,9 @@ nv41_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 		struct nvkm_oclass *oclass, void *data, u32 size,
 		struct nvkm_object **pobject)
 {
-	struct nvkm_fb *pfb = nvkm_fb(parent);
+	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nv40_ram *ram;
-	u32 pfb474 = nv_rd32(pfb, 0x100474);
+	u32 fb474 = nv_rd32(fb, 0x100474);
 	int ret;
 
 	ret = nvkm_ram_create(parent, engine, oclass, &ram);
@@ -38,16 +38,16 @@ nv41_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 	if (ret)
 		return ret;
 
-	if (pfb474 & 0x00000004)
+	if (fb474 & 0x00000004)
 		ram->base.type = NV_MEM_TYPE_GDDR3;
-	if (pfb474 & 0x00000002)
+	if (fb474 & 0x00000002)
 		ram->base.type = NV_MEM_TYPE_DDR2;
-	if (pfb474 & 0x00000001)
+	if (fb474 & 0x00000001)
 		ram->base.type = NV_MEM_TYPE_DDR1;
 
-	ram->base.size  =  nv_rd32(pfb, 0x10020c) & 0xff000000;
-	ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
-	ram->base.tags  =  nv_rd32(pfb, 0x100320);
+	ram->base.size  =  nv_rd32(fb, 0x10020c) & 0xff000000;
+	ram->base.parts = (nv_rd32(fb, 0x100200) & 0x00000003) + 1;
+	ram->base.tags  =  nv_rd32(fb, 0x100320);
 	ram->base.calc = nv40_ram_calc;
 	ram->base.prog = nv40_ram_prog;
 	ram->base.tidy = nv40_ram_tidy;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c

@@ -28,9 +28,9 @@ nv44_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 		struct nvkm_oclass *oclass, void *data, u32 size,
 		struct nvkm_object **pobject)
 {
-	struct nvkm_fb *pfb = nvkm_fb(parent);
+	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nv40_ram *ram;
-	u32 pfb474 = nv_rd32(pfb, 0x100474);
+	u32 fb474 = nv_rd32(fb, 0x100474);
 	int ret;
 
 	ret = nvkm_ram_create(parent, engine, oclass, &ram);
@@ -38,14 +38,14 @@ nv44_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 	if (ret)
 		return ret;
 
-	if (pfb474 & 0x00000004)
+	if (fb474 & 0x00000004)
 		ram->base.type = NV_MEM_TYPE_GDDR3;
-	if (pfb474 & 0x00000002)
+	if (fb474 & 0x00000002)
 		ram->base.type = NV_MEM_TYPE_DDR2;
-	if (pfb474 & 0x00000001)
+	if (fb474 & 0x00000001)
 		ram->base.type = NV_MEM_TYPE_DDR1;
 
-	ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000;
+	ram->base.size = nv_rd32(fb, 0x10020c) & 0xff000000;
 	ram->base.calc = nv40_ram_calc;
 	ram->base.prog = nv40_ram_prog;
 	ram->base.tidy = nv40_ram_tidy;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c

@@ -28,9 +28,9 @@ nv49_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 		struct nvkm_oclass *oclass, void *data, u32 size,
 		struct nvkm_object **pobject)
 {
-	struct nvkm_fb *pfb = nvkm_fb(parent);
+	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nv40_ram *ram;
-	u32 pfb914 = nv_rd32(pfb, 0x100914);
+	u32 fb914 = nv_rd32(fb, 0x100914);
 	int ret;
 
 	ret = nvkm_ram_create(parent, engine, oclass, &ram);
@@ -38,16 +38,16 @@ nv49_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 	if (ret)
 		return ret;
 
-	switch (pfb914 & 0x00000003) {
+	switch (fb914 & 0x00000003) {
 	case 0x00000000: ram->base.type = NV_MEM_TYPE_DDR1; break;
 	case 0x00000001: ram->base.type = NV_MEM_TYPE_DDR2; break;
 	case 0x00000002: ram->base.type = NV_MEM_TYPE_GDDR3; break;
 	case 0x00000003: break;
 	}
 
-	ram->base.size  =  nv_rd32(pfb, 0x10020c) & 0xff000000;
-	ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
-	ram->base.tags  =  nv_rd32(pfb, 0x100320);
+	ram->base.size  =  nv_rd32(fb, 0x10020c) & 0xff000000;
+	ram->base.parts = (nv_rd32(fb, 0x100200) & 0x00000003) + 1;
+	ram->base.tags  =  nv_rd32(fb, 0x100320);
 	ram->base.calc = nv40_ram_calc;
 	ram->base.prog = nv40_ram_prog;
 	ram->base.tidy = nv40_ram_tidy;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c

@@ -28,7 +28,7 @@ nv4e_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 		struct nvkm_oclass *oclass, void *data, u32 size,
 		struct nvkm_object **pobject)
 {
-	struct nvkm_fb *pfb = nvkm_fb(parent);
+	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nvkm_ram *ram;
 	int ret;
 
@@ -37,7 +37,7 @@ nv4e_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 	if (ret)
 		return ret;
 
-	ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000;
+	ram->size = nv_rd32(fb, 0x10020c) & 0xff000000;
 	ram->type = NV_MEM_TYPE_STOLEN;
 	return 0;
 }

drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c

@@ -82,8 +82,8 @@ static void
 nv50_instobj_dtor(struct nvkm_object *object)
 {
 	struct nv50_instobj_priv *node = (void *)object;
-	struct nvkm_fb *pfb = nvkm_fb(object);
-	pfb->ram->put(pfb, &node->mem);
+	struct nvkm_fb *fb = nvkm_fb(object);
+	fb->ram->put(fb, &node->mem);
 	nvkm_instobj_destroy(&node->base);
 }
 
@@ -92,7 +92,7 @@ nv50_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 		  struct nvkm_oclass *oclass, void *data, u32 size,
 		  struct nvkm_object **pobject)
 {
-	struct nvkm_fb *pfb = nvkm_fb(parent);
+	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nvkm_instobj_args *args = data;
 	struct nv50_instobj_priv *node;
 	int ret;
@@ -105,7 +105,7 @@ nv50_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	if (ret)
 		return ret;
 
-	ret = pfb->ram->get(pfb, args->size, args->align, 0, 0x800, &node->mem);
+	ret = fb->ram->get(fb, args->size, args->align, 0, 0x800, &node->mem);
 	if (ret)
 		return ret;
 

drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c

@@ -132,12 +132,12 @@ gf100_ltc_init(struct nvkm_object *object)
 void
 gf100_ltc_dtor(struct nvkm_object *object)
 {
-	struct nvkm_fb *pfb = nvkm_fb(object);
+	struct nvkm_fb *fb = nvkm_fb(object);
 	struct nvkm_ltc_priv *priv = (void *)object;
 
 	nvkm_mm_fini(&priv->tags);
-	if (pfb->ram)
-		nvkm_mm_free(&pfb->vram, &priv->tag_ram);
+	if (fb->ram)
+		nvkm_mm_free(&fb->vram, &priv->tag_ram);
 
 	nvkm_ltc_destroy(priv);
 }
@@ -145,19 +145,19 @@ gf100_ltc_dtor(struct nvkm_object *object)
 /* TODO: Figure out tag memory details and drop the over-cautious allocation.
  */
 int
-gf100_ltc_init_tag_ram(struct nvkm_fb *pfb, struct nvkm_ltc_priv *priv)
+gf100_ltc_init_tag_ram(struct nvkm_fb *fb, struct nvkm_ltc_priv *priv)
 {
 	u32 tag_size, tag_margin, tag_align;
 	int ret;
 
 	/* No VRAM, no tags for now. */
-	if (!pfb->ram) {
+	if (!fb->ram) {
 		priv->num_tags = 0;
 		goto mm_init;
 	}
 
 	/* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */
-	priv->num_tags = (pfb->ram->size >> 17) / 4;
+	priv->num_tags = (fb->ram->size >> 17) / 4;
 	if (priv->num_tags > (1 << 17))
 		priv->num_tags = 1 << 17; /* we have 17 bits in PTE */
 	priv->num_tags = (priv->num_tags + 63) & ~63; /* round up to 64 */
@@ -177,7 +177,7 @@ gf100_ltc_init_tag_ram(struct nvkm_fb *pfb, struct nvkm_ltc_priv *priv)
 	tag_size += tag_align;
 	tag_size  = (tag_size + 0xfff) >> 12; /* round up */
 
-	ret = nvkm_mm_tail(&pfb->vram, 1, 1, tag_size, tag_size, 1,
+	ret = nvkm_mm_tail(&fb->vram, 1, 1, tag_size, tag_size, 1,
 			   &priv->tag_ram);
 	if (ret) {
 		priv->num_tags = 0;
@@ -200,7 +200,7 @@ gf100_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	       struct nvkm_oclass *oclass, void *data, u32 size,
 	       struct nvkm_object **pobject)
 {
-	struct nvkm_fb *pfb = nvkm_fb(parent);
+	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nvkm_ltc_priv *priv;
 	u32 parts, mask;
 	int ret, i;
@@ -218,7 +218,7 @@ gf100_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	}
 	priv->lts_nr = nv_rd32(priv, 0x17e8dc) >> 28;
 
-	ret = gf100_ltc_init_tag_ram(pfb, priv);
+	ret = gf100_ltc_init_tag_ram(fb, priv);
 	if (ret)
 		return ret;
 

drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c

@@ -110,7 +110,7 @@ gm107_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	       struct nvkm_oclass *oclass, void *data, u32 size,
 	       struct nvkm_object **pobject)
 {
-	struct nvkm_fb *pfb = nvkm_fb(parent);
+	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nvkm_ltc_priv *priv;
 	u32 parts, mask;
 	int ret, i;
@@ -128,7 +128,7 @@ gm107_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	}
 	priv->lts_nr = nv_rd32(priv, 0x17e280) >> 28;
 
-	ret = gf100_ltc_init_tag_ram(pfb, priv);
+	ret = gf100_ltc_init_tag_ram(fb, priv);
 	if (ret)
 		return ret;