Commit b2ffec46 authored by Arend van Spriel's avatar Arend van Spriel Committed by John W. Linville

brcm80211: smac: use inline access functions for struct si_pub fields

Instead of directly accessing the fields in struct si_pub the driver
now uses inline access functions. This is in preparation of the bcma
integration as a lot of information will be provided by bcma module.
Reviewed-by: default avatarPieter-Paul Giesberts <pieterpg@broadcom.com>
Reviewed-by: default avatarAlwin Beukers <alwin@broadcom.com>
Reviewed-by: default avatarRoland Vossen <rvossen@broadcom.com>
Signed-off-by: default avatarArend van Spriel <arend@broadcom.com>
Signed-off-by: default avatarFranky Lin <frankyl@broadcom.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 2e397c30
...@@ -292,4 +292,50 @@ extern void ai_chipcontrl_epa4331(struct si_pub *sih, bool on); ...@@ -292,4 +292,50 @@ extern void ai_chipcontrl_epa4331(struct si_pub *sih, bool on);
/* Enable Ex-PA for 4313 */ /* Enable Ex-PA for 4313 */
extern void ai_epa_4313war(struct si_pub *sih); extern void ai_epa_4313war(struct si_pub *sih);
static inline uint ai_get_buscoretype(struct si_pub *sih)
{
return sih->buscoretype;
}
static inline uint ai_get_buscorerev(struct si_pub *sih)
{
return sih->buscorerev;
}
static inline int ai_get_ccrev(struct si_pub *sih)
{
return sih->ccrev;
}
static inline u32 ai_get_cccaps(struct si_pub *sih)
{
return sih->cccaps;
}
static inline int ai_get_pmurev(struct si_pub *sih)
{
return sih->pmurev;
}
static inline u32 ai_get_pmucaps(struct si_pub *sih)
{
return sih->pmucaps;
}
static inline uint ai_get_boardtype(struct si_pub *sih)
{
return sih->boardtype;
}
static inline uint ai_get_boardvendor(struct si_pub *sih)
{
return sih->boardvendor;
}
static inline uint ai_get_chip_id(struct si_pub *sih)
{
return sih->chip;
}
static inline uint ai_get_chiprev(struct si_pub *sih)
{
return sih->chiprev;
}
static inline uint ai_get_chippkg(struct si_pub *sih)
{
return sih->chippkg;
}
#endif /* _BRCM_AIUTILS_H_ */ #endif /* _BRCM_AIUTILS_H_ */
...@@ -1205,7 +1205,7 @@ static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw) ...@@ -1205,7 +1205,7 @@ static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
/* control chip clock to save power, enable dynamic clock or force fast clock */ /* control chip clock to save power, enable dynamic clock or force fast clock */
static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode) static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode)
{ {
if (wlc_hw->sih->cccaps & CC_CAP_PMU) { if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
/* new chips with PMU, CCS_FORCEHT will distribute the HT clock /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
* on backplane, but mac core will still run on ALP(not HT) when * on backplane, but mac core will still run on ALP(not HT) when
* it enters powersave mode, which means the FCA bit may not be * it enters powersave mode, which means the FCA bit may not be
...@@ -1227,7 +1227,7 @@ static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode) ...@@ -1227,7 +1227,7 @@ static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode)
(&wlc_hw->regs-> (&wlc_hw->regs->
clk_ctl_st) & CCS_HTAVAIL)); clk_ctl_st) & CCS_HTAVAIL));
} else { } else {
if ((wlc_hw->sih->pmurev == 0) && if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
(R_REG (R_REG
(&wlc_hw->regs-> (&wlc_hw->regs->
clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ))) clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
...@@ -1843,7 +1843,7 @@ static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw) ...@@ -1843,7 +1843,7 @@ static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
uint b2 = boardrev & 0xf; uint b2 = boardrev & 0xf;
/* voards from other vendors are always considered valid */ /* voards from other vendors are always considered valid */
if (wlc_hw->sih->boardvendor != PCI_VENDOR_ID_BROADCOM) if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
return true; return true;
/* do some boardrev sanity checks when boardvendor is Broadcom */ /* do some boardrev sanity checks when boardvendor is Broadcom */
...@@ -1935,8 +1935,8 @@ static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw) ...@@ -1935,8 +1935,8 @@ static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
* AI chip doesn't restore bar0win2 on * AI chip doesn't restore bar0win2 on
* hibernation/resume, need sw fixup * hibernation/resume, need sw fixup
*/ */
if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) || if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) ||
(wlc_hw->sih->chip == BCM43225_CHIP_ID)) (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID))
wlc_hw->regs = (struct d11regs __iomem *) wlc_hw->regs = (struct d11regs __iomem *)
ai_setcore(wlc_hw->sih, D11_CORE_ID, 0); ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
ai_core_reset(wlc_hw->sih, flags, resetbits); ai_core_reset(wlc_hw->sih, flags, resetbits);
...@@ -2034,7 +2034,7 @@ void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags) ...@@ -2034,7 +2034,7 @@ void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
brcms_c_mctrl_reset(wlc_hw); brcms_c_mctrl_reset(wlc_hw);
if (wlc_hw->sih->cccaps & CC_CAP_PMU) if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
brcms_b_clkctl_clk(wlc_hw, CLK_FAST); brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
brcms_b_phy_reset(wlc_hw); brcms_b_phy_reset(wlc_hw);
...@@ -2117,8 +2117,8 @@ void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode) ...@@ -2117,8 +2117,8 @@ void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
{ {
struct d11regs __iomem *regs = wlc_hw->regs; struct d11regs __iomem *regs = wlc_hw->regs;
if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) || if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) ||
(wlc_hw->sih->chip == BCM43225_CHIP_ID)) { (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID)) {
if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */ if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
W_REG(&regs->tsf_clk_frac_l, 0x2082); W_REG(&regs->tsf_clk_frac_l, 0x2082);
W_REG(&regs->tsf_clk_frac_h, 0x8); W_REG(&regs->tsf_clk_frac_h, 0x8);
...@@ -2805,7 +2805,7 @@ void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on) ...@@ -2805,7 +2805,7 @@ void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
regs = wlc_hw->regs; regs = wlc_hw->regs;
if (on) { if (on) {
if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) { if ((ai_get_chip_id(wlc_hw->sih) == BCM4313_CHIP_ID)) {
OR_REG(&regs->clk_ctl_st, OR_REG(&regs->clk_ctl_st,
(CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL | (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
CCS_ERSRC_REQ_PHYPLL)); CCS_ERSRC_REQ_PHYPLL));
...@@ -4531,7 +4531,8 @@ static int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device, ...@@ -4531,7 +4531,8 @@ static int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device,
if (!brcms_c_validboardtype(wlc_hw)) { if (!brcms_c_validboardtype(wlc_hw)) {
wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom " wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
"board type (0x%x)" " or revision level (0x%x)\n", "board type (0x%x)" " or revision level (0x%x)\n",
unit, wlc_hw->sih->boardtype, wlc_hw->boardrev); unit, ai_get_boardtype(wlc_hw->sih),
wlc_hw->boardrev);
err = 15; err = 15;
goto fail; goto fail;
} }
...@@ -4552,7 +4553,7 @@ static int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device, ...@@ -4552,7 +4553,7 @@ static int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device,
else else
wlc_hw->_nbands = 1; wlc_hw->_nbands = 1;
if ((wlc_hw->sih->chip == BCM43225_CHIP_ID)) if ((ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID))
wlc_hw->_nbands = 1; wlc_hw->_nbands = 1;
/* BMAC_NOTE: remove init of pub values when brcms_c_attach() /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
...@@ -4584,16 +4585,14 @@ static int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device, ...@@ -4584,16 +4585,14 @@ static int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device,
sha_params.corerev = wlc_hw->corerev; sha_params.corerev = wlc_hw->corerev;
sha_params.vid = wlc_hw->vendorid; sha_params.vid = wlc_hw->vendorid;
sha_params.did = wlc_hw->deviceid; sha_params.did = wlc_hw->deviceid;
sha_params.chip = wlc_hw->sih->chip; sha_params.chip = ai_get_chip_id(wlc_hw->sih);
sha_params.chiprev = wlc_hw->sih->chiprev; sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
sha_params.chippkg = wlc_hw->sih->chippkg; sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
sha_params.sromrev = wlc_hw->sromrev; sha_params.sromrev = wlc_hw->sromrev;
sha_params.boardtype = wlc_hw->sih->boardtype; sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
sha_params.boardrev = wlc_hw->boardrev; sha_params.boardrev = wlc_hw->boardrev;
sha_params.boardvendor = wlc_hw->sih->boardvendor;
sha_params.boardflags = wlc_hw->boardflags; sha_params.boardflags = wlc_hw->boardflags;
sha_params.boardflags2 = wlc_hw->boardflags2; sha_params.boardflags2 = wlc_hw->boardflags2;
sha_params.buscorerev = wlc_hw->sih->buscorerev;
/* alloc and save pointer to shared phy state area */ /* alloc and save pointer to shared phy state area */
wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params); wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
...@@ -4734,10 +4733,9 @@ static int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device, ...@@ -4734,10 +4733,9 @@ static int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device,
goto fail; goto fail;
} }
BCMMSG(wlc->wiphy, BCMMSG(wlc->wiphy, "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
"deviceid 0x%x nbands %d board 0x%x macaddr: %s\n", wlc_hw->deviceid, wlc_hw->_nbands, ai_get_boardtype(wlc_hw->sih),
wlc_hw->deviceid, wlc_hw->_nbands, macaddr);
wlc_hw->sih->boardtype, macaddr);
return err; return err;
...@@ -5073,8 +5071,8 @@ static void brcms_b_hw_up(struct brcms_hardware *wlc_hw) ...@@ -5073,8 +5071,8 @@ static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
* AI chip doesn't restore bar0win2 on * AI chip doesn't restore bar0win2 on
* hibernation/resume, need sw fixup * hibernation/resume, need sw fixup
*/ */
if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) || if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) ||
(wlc_hw->sih->chip == BCM43225_CHIP_ID)) (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID))
wlc_hw->regs = (struct d11regs __iomem *) wlc_hw->regs = (struct d11regs __iomem *)
ai_setcore(wlc_hw->sih, D11_CORE_ID, 0); ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
...@@ -5088,7 +5086,7 @@ static void brcms_b_hw_up(struct brcms_hardware *wlc_hw) ...@@ -5088,7 +5086,7 @@ static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
wlc_hw->wlc->pub->hw_up = true; wlc_hw->wlc->pub->hw_up = true;
if ((wlc_hw->boardflags & BFL_FEM) if ((wlc_hw->boardflags & BFL_FEM)
&& (wlc_hw->sih->chip == BCM4313_CHIP_ID)) { && (ai_get_chip_id(wlc_hw->sih) == BCM4313_CHIP_ID)) {
if (! if (!
(wlc_hw->boardrev >= 0x1250 (wlc_hw->boardrev >= 0x1250
&& (wlc_hw->boardflags & BFL_FEM_BT))) && (wlc_hw->boardflags & BFL_FEM_BT)))
...@@ -5183,7 +5181,7 @@ int brcms_c_up(struct brcms_c_info *wlc) ...@@ -5183,7 +5181,7 @@ int brcms_c_up(struct brcms_c_info *wlc)
} }
if ((wlc->pub->boardflags & BFL_FEM) if ((wlc->pub->boardflags & BFL_FEM)
&& (wlc->pub->sih->chip == BCM4313_CHIP_ID)) { && (ai_get_chip_id(wlc->hw->sih) == BCM4313_CHIP_ID)) {
if (wlc->pub->boardrev >= 0x1250 if (wlc->pub->boardrev >= 0x1250
&& (wlc->pub->boardflags & BFL_FEM_BT)) && (wlc->pub->boardflags & BFL_FEM_BT))
brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL, brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
...@@ -8213,8 +8211,8 @@ bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded) ...@@ -8213,8 +8211,8 @@ bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
"(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now); "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n", printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
__func__, wlc_hw->sih->chip, __func__, ai_get_chip_id(wlc_hw->sih),
wlc_hw->sih->chiprev); ai_get_chiprev(wlc_hw->sih));
brcms_fatal_error(wlc_hw->wlc->wl); brcms_fatal_error(wlc_hw->wlc->wl);
} }
......
...@@ -224,9 +224,9 @@ struct pcicore_info { ...@@ -224,9 +224,9 @@ struct pcicore_info {
}; };
#define PCIE_ASPM(sih) \ #define PCIE_ASPM(sih) \
(((sih)->buscoretype == PCIE_CORE_ID) && \ ((ai_get_buscoretype(sih) == PCIE_CORE_ID) && \
(((sih)->buscorerev >= 3) && \ ((ai_get_buscorerev(sih) >= 3) && \
((sih)->buscorerev <= 5))) (ai_get_buscorerev(sih) <= 5)))
/* delay needed between the mdio control/ mdiodata register data access */ /* delay needed between the mdio control/ mdiodata register data access */
...@@ -251,7 +251,7 @@ struct pcicore_info *pcicore_init(struct si_pub *sih, struct pci_dev *pdev, ...@@ -251,7 +251,7 @@ struct pcicore_info *pcicore_init(struct si_pub *sih, struct pci_dev *pdev,
pi->sih = sih; pi->sih = sih;
pi->dev = pdev; pi->dev = pdev;
if (sih->buscoretype == PCIE_CORE_ID) { if (ai_get_buscoretype(sih) == PCIE_CORE_ID) {
u8 cap_ptr; u8 cap_ptr;
pi->regs.pcieregs = regs; pi->regs.pcieregs = regs;
cap_ptr = pcicore_find_pci_capability(pi->dev, PCI_CAP_ID_EXP, cap_ptr = pcicore_find_pci_capability(pi->dev, PCI_CAP_ID_EXP,
...@@ -504,7 +504,8 @@ static void pcie_extendL1timer(struct pcicore_info *pi, bool extend) ...@@ -504,7 +504,8 @@ static void pcie_extendL1timer(struct pcicore_info *pi, bool extend)
struct si_pub *sih = pi->sih; struct si_pub *sih = pi->sih;
struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs; struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs;
if (sih->buscoretype != PCIE_CORE_ID || sih->buscorerev < 7) if (ai_get_buscoretype(sih) != PCIE_CORE_ID ||
ai_get_buscorerev(sih) < 7)
return; return;
w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG); w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
...@@ -527,7 +528,8 @@ static void pcie_clkreq_upd(struct pcicore_info *pi, uint state) ...@@ -527,7 +528,8 @@ static void pcie_clkreq_upd(struct pcicore_info *pi, uint state)
pcie_clkreq(pi, 1, 0); pcie_clkreq(pi, 1, 0);
break; break;
case SI_PCIDOWN: case SI_PCIDOWN:
if (sih->buscorerev == 6) { /* turn on serdes PLL down */ /* turn on serdes PLL down */
if (ai_get_buscorerev(sih) == 6) {
ai_corereg(sih, SI_CC_IDX, ai_corereg(sih, SI_CC_IDX,
offsetof(struct chipcregs, chipcontrol_addr), offsetof(struct chipcregs, chipcontrol_addr),
~0, 0); ~0, 0);
...@@ -539,7 +541,8 @@ static void pcie_clkreq_upd(struct pcicore_info *pi, uint state) ...@@ -539,7 +541,8 @@ static void pcie_clkreq_upd(struct pcicore_info *pi, uint state)
} }
break; break;
case SI_PCIUP: case SI_PCIUP:
if (sih->buscorerev == 6) { /* turn off serdes PLL down */ /* turn off serdes PLL down */
if (ai_get_buscorerev(sih) == 6) {
ai_corereg(sih, SI_CC_IDX, ai_corereg(sih, SI_CC_IDX,
offsetof(struct chipcregs, chipcontrol_addr), offsetof(struct chipcregs, chipcontrol_addr),
~0, 0); ~0, 0);
...@@ -678,7 +681,7 @@ static void pcie_war_pci_setup(struct pcicore_info *pi) ...@@ -678,7 +681,7 @@ static void pcie_war_pci_setup(struct pcicore_info *pi)
struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs; struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs;
u32 w; u32 w;
if (sih->buscorerev == 0 || sih->buscorerev == 1) { if (ai_get_buscorerev(sih) == 0 || ai_get_buscorerev(sih) == 1) {
w = pcie_readreg(pcieregs, PCIE_PCIEREGS, w = pcie_readreg(pcieregs, PCIE_PCIEREGS,
PCIE_TLP_WORKAROUNDSREG); PCIE_TLP_WORKAROUNDSREG);
w |= 0x8; w |= 0x8;
...@@ -686,13 +689,13 @@ static void pcie_war_pci_setup(struct pcicore_info *pi) ...@@ -686,13 +689,13 @@ static void pcie_war_pci_setup(struct pcicore_info *pi)
PCIE_TLP_WORKAROUNDSREG, w); PCIE_TLP_WORKAROUNDSREG, w);
} }
if (sih->buscorerev == 1) { if (ai_get_buscorerev(sih) == 1) {
w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG); w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG);
w |= 0x40; w |= 0x40;
pcie_writereg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG, w); pcie_writereg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG, w);
} }
if (sih->buscorerev == 0) { if (ai_get_buscorerev(sih) == 0) {
pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128); pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100); pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466); pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
...@@ -708,13 +711,13 @@ static void pcie_war_pci_setup(struct pcicore_info *pi) ...@@ -708,13 +711,13 @@ static void pcie_war_pci_setup(struct pcicore_info *pi)
pcie_war_serdes(pi); pcie_war_serdes(pi);
pcie_war_aspm_clkreq(pi); pcie_war_aspm_clkreq(pi);
} else if (pi->sih->buscorerev == 7) } else if (ai_get_buscorerev(pi->sih) == 7)
pcie_war_noplldown(pi); pcie_war_noplldown(pi);
/* Note that the fix is actually in the SROM, /* Note that the fix is actually in the SROM,
* that's why this is open-ended * that's why this is open-ended
*/ */
if (pi->sih->buscorerev >= 6) if (ai_get_buscorerev(pi->sih) >= 6)
pcie_misc_config_fixup(pi); pcie_misc_config_fixup(pi);
} }
...@@ -745,7 +748,7 @@ void pcicore_attach(struct pcicore_info *pi, int state) ...@@ -745,7 +748,7 @@ void pcicore_attach(struct pcicore_info *pi, int state)
void pcicore_hwup(struct pcicore_info *pi) void pcicore_hwup(struct pcicore_info *pi)
{ {
if (!pi || pi->sih->buscoretype != PCIE_CORE_ID) if (!pi || ai_get_buscoretype(pi->sih) != PCIE_CORE_ID)
return; return;
pcie_war_pci_setup(pi); pcie_war_pci_setup(pi);
...@@ -753,7 +756,7 @@ void pcicore_hwup(struct pcicore_info *pi) ...@@ -753,7 +756,7 @@ void pcicore_hwup(struct pcicore_info *pi)
void pcicore_up(struct pcicore_info *pi, int state) void pcicore_up(struct pcicore_info *pi, int state)
{ {
if (!pi || pi->sih->buscoretype != PCIE_CORE_ID) if (!pi || ai_get_buscoretype(pi->sih) != PCIE_CORE_ID)
return; return;
/* Restore L1 timer for better performance */ /* Restore L1 timer for better performance */
...@@ -781,7 +784,7 @@ void pcicore_sleep(struct pcicore_info *pi) ...@@ -781,7 +784,7 @@ void pcicore_sleep(struct pcicore_info *pi)
void pcicore_down(struct pcicore_info *pi, int state) void pcicore_down(struct pcicore_info *pi, int state)
{ {
if (!pi || pi->sih->buscoretype != PCIE_CORE_ID) if (!pi || ai_get_buscoretype(pi->sih) != PCIE_CORE_ID)
return; return;
pcie_clkreq_upd(pi, state); pcie_clkreq_upd(pi, state);
...@@ -826,7 +829,7 @@ pcicore_pci_setup(struct pcicore_info *pi, struct sbpciregs __iomem *pciregs) ...@@ -826,7 +829,7 @@ pcicore_pci_setup(struct pcicore_info *pi, struct sbpciregs __iomem *pciregs)
OR_REG(&pciregs->sbtopci2, SBTOPCI_PREF | SBTOPCI_BURST); OR_REG(&pciregs->sbtopci2, SBTOPCI_PREF | SBTOPCI_BURST);
if (((struct si_info *)(pi->sih))->pub.buscorerev >= 11) { if (ai_get_buscorerev(pi->sih) >= 11) {
OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI); OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
w = R_REG(&pciregs->clkrun); w = R_REG(&pciregs->clkrun);
W_REG(&pciregs->clkrun, w | PCI_CLKRUN_DSBL); W_REG(&pciregs->clkrun, w | PCI_CLKRUN_DSBL);
......
...@@ -146,7 +146,7 @@ static int ipxotp_max_rgnsz(struct si_pub *sih, int osizew) ...@@ -146,7 +146,7 @@ static int ipxotp_max_rgnsz(struct si_pub *sih, int osizew)
{ {
int ret = 0; int ret = 0;
switch (sih->chip) { switch (ai_get_chip_id(sih)) {
case BCM43224_CHIP_ID: case BCM43224_CHIP_ID:
case BCM43225_CHIP_ID: case BCM43225_CHIP_ID:
ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM; ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM;
...@@ -170,10 +170,10 @@ static void _ipxotp_init(struct otpinfo *oi, struct chipcregs __iomem *cc) ...@@ -170,10 +170,10 @@ static void _ipxotp_init(struct otpinfo *oi, struct chipcregs __iomem *cc)
* record word offset of General Use Region * record word offset of General Use Region
* for various chipcommon revs * for various chipcommon revs
*/ */
if (oi->sih->ccrev == 21 || oi->sih->ccrev == 24 if (oi->ccrev == 21 || oi->ccrev == 24
|| oi->sih->ccrev == 27) { || oi->ccrev == 27) {
oi->otpgu_base = REVA4_OTPGU_BASE; oi->otpgu_base = REVA4_OTPGU_BASE;
} else if (oi->sih->ccrev == 36) { } else if (oi->ccrev == 36) {
/* /*
* OTP size greater than equal to 2KB (128 words), * OTP size greater than equal to 2KB (128 words),
* otpgu_base is similar to rev23 * otpgu_base is similar to rev23
...@@ -182,7 +182,7 @@ static void _ipxotp_init(struct otpinfo *oi, struct chipcregs __iomem *cc) ...@@ -182,7 +182,7 @@ static void _ipxotp_init(struct otpinfo *oi, struct chipcregs __iomem *cc)
oi->otpgu_base = REVB8_OTPGU_BASE; oi->otpgu_base = REVB8_OTPGU_BASE;
else else
oi->otpgu_base = REV36_OTPGU_BASE; oi->otpgu_base = REV36_OTPGU_BASE;
} else if (oi->sih->ccrev == 23 || oi->sih->ccrev >= 25) { } else if (oi->ccrev == 23 || oi->ccrev >= 25) {
oi->otpgu_base = REVB8_OTPGU_BASE; oi->otpgu_base = REVB8_OTPGU_BASE;
} }
...@@ -201,8 +201,8 @@ static void _ipxotp_init(struct otpinfo *oi, struct chipcregs __iomem *cc) ...@@ -201,8 +201,8 @@ static void _ipxotp_init(struct otpinfo *oi, struct chipcregs __iomem *cc)
/* Read OTP lock bits and subregion programmed indication bits */ /* Read OTP lock bits and subregion programmed indication bits */
oi->status = R_REG(&cc->otpstatus); oi->status = R_REG(&cc->otpstatus);
if ((oi->sih->chip == BCM43224_CHIP_ID) if ((ai_get_chip_id(oi->sih) == BCM43224_CHIP_ID)
|| (oi->sih->chip == BCM43225_CHIP_ID)) { || (ai_get_chip_id(oi->sih) == BCM43225_CHIP_ID)) {
u32 p_bits; u32 p_bits;
p_bits = p_bits =
(ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_P_OFF) & (ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_P_OFF) &
...@@ -244,7 +244,7 @@ static int ipxotp_init(struct si_pub *sih, struct otpinfo *oi) ...@@ -244,7 +244,7 @@ static int ipxotp_init(struct si_pub *sih, struct otpinfo *oi)
struct chipcregs __iomem *cc; struct chipcregs __iomem *cc;
/* Make sure we're running IPX OTP */ /* Make sure we're running IPX OTP */
if (!OTPTYPE_IPX(sih->ccrev)) if (!OTPTYPE_IPX(oi->ccrev))
return -EBADE; return -EBADE;
/* Make sure OTP is not disabled */ /* Make sure OTP is not disabled */
...@@ -252,7 +252,7 @@ static int ipxotp_init(struct si_pub *sih, struct otpinfo *oi) ...@@ -252,7 +252,7 @@ static int ipxotp_init(struct si_pub *sih, struct otpinfo *oi)
return -EBADE; return -EBADE;
/* Check for otp size */ /* Check for otp size */
switch ((sih->cccaps & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT) { switch ((ai_get_cccaps(sih) & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT) {
case 0: case 0:
/* Nothing there */ /* Nothing there */
return -EBADE; return -EBADE;
...@@ -389,7 +389,7 @@ static int otp_init(struct si_pub *sih, struct otpinfo *oi) ...@@ -389,7 +389,7 @@ static int otp_init(struct si_pub *sih, struct otpinfo *oi)
memset(oi, 0, sizeof(struct otpinfo)); memset(oi, 0, sizeof(struct otpinfo));
oi->ccrev = sih->ccrev; oi->ccrev = ai_get_ccrev(sih);
if (OTPTYPE_IPX(oi->ccrev)) if (OTPTYPE_IPX(oi->ccrev))
oi->fn = &ipxotp_fn; oi->fn = &ipxotp_fn;
......
...@@ -404,10 +404,8 @@ struct shared_phy *wlc_phy_shared_attach(struct shared_phy_params *shp) ...@@ -404,10 +404,8 @@ struct shared_phy *wlc_phy_shared_attach(struct shared_phy_params *shp)
sh->sromrev = shp->sromrev; sh->sromrev = shp->sromrev;
sh->boardtype = shp->boardtype; sh->boardtype = shp->boardtype;
sh->boardrev = shp->boardrev; sh->boardrev = shp->boardrev;
sh->boardvendor = shp->boardvendor;
sh->boardflags = shp->boardflags; sh->boardflags = shp->boardflags;
sh->boardflags2 = shp->boardflags2; sh->boardflags2 = shp->boardflags2;
sh->buscorerev = shp->buscorerev;
sh->fast_timer = PHY_SW_TIMER_FAST; sh->fast_timer = PHY_SW_TIMER_FAST;
sh->slow_timer = PHY_SW_TIMER_SLOW; sh->slow_timer = PHY_SW_TIMER_SLOW;
......
...@@ -166,7 +166,6 @@ struct shared_phy_params { ...@@ -166,7 +166,6 @@ struct shared_phy_params {
struct phy_shim_info *physhim; struct phy_shim_info *physhim;
uint unit; uint unit;
uint corerev; uint corerev;
uint buscorerev;
u16 vid; u16 vid;
u16 did; u16 did;
uint chip; uint chip;
...@@ -175,7 +174,6 @@ struct shared_phy_params { ...@@ -175,7 +174,6 @@ struct shared_phy_params {
uint sromrev; uint sromrev;
uint boardtype; uint boardtype;
uint boardrev; uint boardrev;
uint boardvendor;
u32 boardflags; u32 boardflags;
u32 boardflags2; u32 boardflags2;
}; };
......
...@@ -503,10 +503,8 @@ struct shared_phy { ...@@ -503,10 +503,8 @@ struct shared_phy {
uint sromrev; uint sromrev;
uint boardtype; uint boardtype;
uint boardrev; uint boardrev;
uint boardvendor;
u32 boardflags; u32 boardflags;
u32 boardflags2; u32 boardflags2;
uint buscorerev;
uint fast_timer; uint fast_timer;
uint slow_timer; uint slow_timer;
uint glacial_timer; uint glacial_timer;
......
...@@ -115,10 +115,10 @@ static void si_pmu_res_masks(struct si_pub *sih, u32 * pmin, u32 * pmax) ...@@ -115,10 +115,10 @@ static void si_pmu_res_masks(struct si_pub *sih, u32 * pmin, u32 * pmax)
uint rsrcs; uint rsrcs;
/* # resources */ /* # resources */
rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT; rsrcs = (ai_get_pmucaps(sih) & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
/* determine min/max rsrc masks */ /* determine min/max rsrc masks */
switch (sih->chip) { switch (ai_get_chip_id(sih)) {
case BCM43224_CHIP_ID: case BCM43224_CHIP_ID:
case BCM43225_CHIP_ID: case BCM43225_CHIP_ID:
/* ??? */ /* ??? */
...@@ -145,7 +145,7 @@ si_pmu_spuravoid_pllupdate(struct si_pub *sih, struct chipcregs __iomem *cc, ...@@ -145,7 +145,7 @@ si_pmu_spuravoid_pllupdate(struct si_pub *sih, struct chipcregs __iomem *cc,
{ {
u32 tmp = 0; u32 tmp = 0;
switch (sih->chip) { switch (ai_get_chip_id(sih)) {
case BCM43224_CHIP_ID: case BCM43224_CHIP_ID:
case BCM43225_CHIP_ID: case BCM43225_CHIP_ID:
if (spuravoid == 1) { if (spuravoid == 1) {
...@@ -207,7 +207,7 @@ u16 si_pmu_fast_pwrup_delay(struct si_pub *sih) ...@@ -207,7 +207,7 @@ u16 si_pmu_fast_pwrup_delay(struct si_pub *sih)
{ {
uint delay = PMU_MAX_TRANSITION_DLY; uint delay = PMU_MAX_TRANSITION_DLY;
switch (sih->chip) { switch (ai_get_chip_id(sih)) {
case BCM43224_CHIP_ID: case BCM43224_CHIP_ID:
case BCM43225_CHIP_ID: case BCM43225_CHIP_ID:
case BCM4313_CHIP_ID: case BCM4313_CHIP_ID:
...@@ -276,10 +276,10 @@ u32 si_pmu_alp_clock(struct si_pub *sih) ...@@ -276,10 +276,10 @@ u32 si_pmu_alp_clock(struct si_pub *sih)
u32 clock = ALP_CLOCK; u32 clock = ALP_CLOCK;
/* bail out with default */ /* bail out with default */
if (!(sih->cccaps & CC_CAP_PMU)) if (!(ai_get_cccaps(sih) & CC_CAP_PMU))
return clock; return clock;
switch (sih->chip) { switch (ai_get_chip_id(sih)) {
case BCM43224_CHIP_ID: case BCM43224_CHIP_ID:
case BCM43225_CHIP_ID: case BCM43225_CHIP_ID:
case BCM4313_CHIP_ID: case BCM4313_CHIP_ID:
...@@ -319,9 +319,9 @@ void si_pmu_init(struct si_pub *sih) ...@@ -319,9 +319,9 @@ void si_pmu_init(struct si_pub *sih)
origidx = ai_coreidx(sih); origidx = ai_coreidx(sih);
cc = ai_setcoreidx(sih, SI_CC_IDX); cc = ai_setcoreidx(sih, SI_CC_IDX);
if (sih->pmurev == 1) if (ai_get_pmurev(sih) == 1)
AND_REG(&cc->pmucontrol, ~PCTL_NOILP_ON_WAIT); AND_REG(&cc->pmucontrol, ~PCTL_NOILP_ON_WAIT);
else if (sih->pmurev >= 2) else if (ai_get_pmurev(sih) >= 2)
OR_REG(&cc->pmucontrol, PCTL_NOILP_ON_WAIT); OR_REG(&cc->pmucontrol, PCTL_NOILP_ON_WAIT);
/* Return to original core */ /* Return to original core */
...@@ -358,7 +358,7 @@ void si_pmu_pll_init(struct si_pub *sih, uint xtalfreq) ...@@ -358,7 +358,7 @@ void si_pmu_pll_init(struct si_pub *sih, uint xtalfreq)
origidx = ai_coreidx(sih); origidx = ai_coreidx(sih);
cc = ai_setcoreidx(sih, SI_CC_IDX); cc = ai_setcoreidx(sih, SI_CC_IDX);
switch (sih->chip) { switch (ai_get_chip_id(sih)) {
case BCM4313_CHIP_ID: case BCM4313_CHIP_ID:
case BCM43224_CHIP_ID: case BCM43224_CHIP_ID:
case BCM43225_CHIP_ID: case BCM43225_CHIP_ID:
...@@ -411,7 +411,7 @@ u32 si_pmu_measure_alpclk(struct si_pub *sih) ...@@ -411,7 +411,7 @@ u32 si_pmu_measure_alpclk(struct si_pub *sih)
uint origidx; uint origidx;
u32 alp_khz; u32 alp_khz;
if (sih->pmurev < 10) if (ai_get_pmurev(sih) < 10)
return 0; return 0;
/* Remember original core before switch to chipc */ /* Remember original core before switch to chipc */
......
...@@ -589,9 +589,9 @@ static u8 brcms_srom_crc8_table[CRC8_TABLE_SIZE]; ...@@ -589,9 +589,9 @@ static u8 brcms_srom_crc8_table[CRC8_TABLE_SIZE];
static u8 __iomem * static u8 __iomem *
srom_window_address(struct si_pub *sih, u8 __iomem *curmap) srom_window_address(struct si_pub *sih, u8 __iomem *curmap)
{ {
if (sih->ccrev < 32) if (ai_get_ccrev(sih) < 32)
return curmap + PCI_BAR0_SPROM_OFFSET; return curmap + PCI_BAR0_SPROM_OFFSET;
if (sih->cccaps & CC_CAP_SROM) if (ai_get_cccaps(sih) & CC_CAP_SROM)
return curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP; return curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP;
return NULL; return NULL;
......
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