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Commit b4915da3 authored by Grant Grundler's avatar Grant Grundler Committed by David S. Miller
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[TIGON3]: Consolidate MMIO write flushing using tg3_f() macro.

parent dc49a382
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Showing with 96 additions and 168 deletions
drivers/net/tg3.c
View file @ b4915da3
...@@ -215,6 +215,21 @@ static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) ...@@ -215,6 +215,21 @@ static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
} }
} }
static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
{
if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
unsigned long flags;
spin_lock_irqsave(&tp->indirect_lock, flags);
pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
spin_unlock_irqrestore(&tp->indirect_lock, flags);
} else {
unsigned long dest = tp->regs + off;
writel(val, dest);
readl(dest); /* always flush PCI write */
}
}
static inline void _tw32_rx_mbox(struct tg3 *tp, u32 off, u32 val) static inline void _tw32_rx_mbox(struct tg3 *tp, u32 off, u32 val)
{ {
...@@ -239,6 +254,7 @@ static inline void _tw32_tx_mbox(struct tg3 *tp, u32 off, u32 val) ...@@ -239,6 +254,7 @@ static inline void _tw32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
#define tw32_tx_mbox(reg, val) _tw32_tx_mbox(tp, reg, val) #define tw32_tx_mbox(reg, val) _tw32_tx_mbox(tp, reg, val)
#define tw32(reg,val) tg3_write_indirect_reg32(tp,(reg),(val)) #define tw32(reg,val) tg3_write_indirect_reg32(tp,(reg),(val))
#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val))
#define tw16(reg,val) writew(((val) & 0xffff), tp->regs + (reg)) #define tw16(reg,val) writew(((val) & 0xffff), tp->regs + (reg))
#define tw8(reg,val) writeb(((val) & 0xff), tp->regs + (reg)) #define tw8(reg,val) writeb(((val) & 0xff), tp->regs + (reg))
#define tr32(reg) readl(tp->regs + (reg)) #define tr32(reg) readl(tp->regs + (reg))
...@@ -325,18 +341,15 @@ static void tg3_switch_clocks(struct tg3 *tp) ...@@ -325,18 +341,15 @@ static void tg3_switch_clocks(struct tg3 *tp)
if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
(orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { (orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
tw32(TG3PCI_CLOCK_CTRL, tw32_f(TG3PCI_CLOCK_CTRL,
clock_ctrl | clock_ctrl |
(CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK)); (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
tr32(TG3PCI_CLOCK_CTRL);
udelay(40); udelay(40);
tw32(TG3PCI_CLOCK_CTRL, tw32_f(TG3PCI_CLOCK_CTRL,
clock_ctrl | (CLOCK_CTRL_ALTCLK)); clock_ctrl | (CLOCK_CTRL_ALTCLK));
tr32(TG3PCI_CLOCK_CTRL);
udelay(40); udelay(40);
} }
tw32(TG3PCI_CLOCK_CTRL, clock_ctrl); tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
tr32(TG3PCI_CLOCK_CTRL);
udelay(40); udelay(40);
} }
...@@ -348,9 +361,8 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) ...@@ -348,9 +361,8 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
int loops, ret; int loops, ret;
if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
tw32(MAC_MI_MODE, tw32_f(MAC_MI_MODE,
(tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
tr32(MAC_MI_MODE);
udelay(40); udelay(40);
} }
...@@ -362,8 +374,7 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) ...@@ -362,8 +374,7 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
MI_COM_REG_ADDR_MASK); MI_COM_REG_ADDR_MASK);
frame_val |= (MI_COM_CMD_READ | MI_COM_START); frame_val |= (MI_COM_CMD_READ | MI_COM_START);
tw32(MAC_MI_COM, frame_val); tw32_f(MAC_MI_COM, frame_val);
tr32(MAC_MI_COM);
loops = PHY_BUSY_LOOPS; loops = PHY_BUSY_LOOPS;
while (loops-- > 0) { while (loops-- > 0) {
...@@ -384,8 +395,7 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) ...@@ -384,8 +395,7 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
} }
if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
tw32(MAC_MI_MODE, tp->mi_mode); tw32_f(MAC_MI_MODE, tp->mi_mode);
tr32(MAC_MI_MODE);
udelay(40); udelay(40);
} }
...@@ -398,9 +408,8 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val) ...@@ -398,9 +408,8 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
int loops, ret; int loops, ret;
if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
tw32(MAC_MI_MODE, tw32_f(MAC_MI_MODE,
(tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
tr32(MAC_MI_MODE);
udelay(40); udelay(40);
} }
...@@ -411,8 +420,7 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val) ...@@ -411,8 +420,7 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
frame_val |= (val & MI_COM_DATA_MASK); frame_val |= (val & MI_COM_DATA_MASK);
frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
tw32(MAC_MI_COM, frame_val); tw32_f(MAC_MI_COM, frame_val);
tr32(MAC_MI_COM);
loops = PHY_BUSY_LOOPS; loops = PHY_BUSY_LOOPS;
while (loops-- > 0) { while (loops-- > 0) {
...@@ -430,8 +438,7 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val) ...@@ -430,8 +438,7 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
ret = 0; ret = 0;
if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
tw32(MAC_MI_MODE, tp->mi_mode); tw32_f(MAC_MI_MODE, tp->mi_mode);
tr32(MAC_MI_MODE);
udelay(40); udelay(40);
} }
...@@ -714,45 +721,41 @@ static void tg3_frob_aux_power(struct tg3 *tp) ...@@ -714,45 +721,41 @@ static void tg3_frob_aux_power(struct tg3 *tp)
(tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) { (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) {
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
(GRC_LCLCTRL_GPIO_OE0 | (GRC_LCLCTRL_GPIO_OE0 |
GRC_LCLCTRL_GPIO_OE1 | GRC_LCLCTRL_GPIO_OE1 |
GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OE2 |
GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT0 |
GRC_LCLCTRL_GPIO_OUTPUT1)); GRC_LCLCTRL_GPIO_OUTPUT1));
tr32(GRC_LOCAL_CTRL);
udelay(100); udelay(100);
} else { } else {
if (tp_peer != tp && if (tp_peer != tp &&
(tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0) (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
return; return;
tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
(GRC_LCLCTRL_GPIO_OE0 | (GRC_LCLCTRL_GPIO_OE0 |
GRC_LCLCTRL_GPIO_OE1 | GRC_LCLCTRL_GPIO_OE1 |
GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OE2 |
GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT1 |
GRC_LCLCTRL_GPIO_OUTPUT2)); GRC_LCLCTRL_GPIO_OUTPUT2));
tr32(GRC_LOCAL_CTRL);
udelay(100); udelay(100);
tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
(GRC_LCLCTRL_GPIO_OE0 | (GRC_LCLCTRL_GPIO_OE0 |
GRC_LCLCTRL_GPIO_OE1 | GRC_LCLCTRL_GPIO_OE1 |
GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OE2 |
GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT0 |
GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT1 |
GRC_LCLCTRL_GPIO_OUTPUT2)); GRC_LCLCTRL_GPIO_OUTPUT2));
tr32(GRC_LOCAL_CTRL);
udelay(100); udelay(100);
tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
(GRC_LCLCTRL_GPIO_OE0 | (GRC_LCLCTRL_GPIO_OE0 |
GRC_LCLCTRL_GPIO_OE1 | GRC_LCLCTRL_GPIO_OE1 |
GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OE2 |
GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT0 |
GRC_LCLCTRL_GPIO_OUTPUT1)); GRC_LCLCTRL_GPIO_OUTPUT1));
tr32(GRC_LOCAL_CTRL);
udelay(100); udelay(100);
} }
} else { } else {
...@@ -762,21 +765,18 @@ static void tg3_frob_aux_power(struct tg3 *tp) ...@@ -762,21 +765,18 @@ static void tg3_frob_aux_power(struct tg3 *tp)
(tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0) (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
return; return;
tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
(GRC_LCLCTRL_GPIO_OE1 | (GRC_LCLCTRL_GPIO_OE1 |
GRC_LCLCTRL_GPIO_OUTPUT1)); GRC_LCLCTRL_GPIO_OUTPUT1));
tr32(GRC_LOCAL_CTRL);
udelay(100); udelay(100);
tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
(GRC_LCLCTRL_GPIO_OE1)); (GRC_LCLCTRL_GPIO_OE1));
tr32(GRC_LOCAL_CTRL);
udelay(100); udelay(100);
tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
(GRC_LCLCTRL_GPIO_OE1 | (GRC_LCLCTRL_GPIO_OE1 |
GRC_LCLCTRL_GPIO_OUTPUT1)); GRC_LCLCTRL_GPIO_OUTPUT1));
tr32(GRC_LOCAL_CTRL);
udelay(100); udelay(100);
} }
} }
...@@ -808,8 +808,7 @@ static int tg3_set_power_state(struct tg3 *tp, int state) ...@@ -808,8 +808,7 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
pci_write_config_word(tp->pdev, pci_write_config_word(tp->pdev,
pm + PCI_PM_CTRL, pm + PCI_PM_CTRL,
power_control); power_control);
tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
tr32(GRC_LOCAL_CTRL);
udelay(100); udelay(100);
return 0; return 0;
...@@ -876,12 +875,10 @@ static int tg3_set_power_state(struct tg3 *tp, int state) ...@@ -876,12 +875,10 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
(tp->tg3_flags & TG3_FLAG_WOL_ENABLE))) (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
tw32(MAC_MODE, mac_mode); tw32_f(MAC_MODE, mac_mode);
tr32(MAC_MODE);
udelay(100); udelay(100);
tw32(MAC_RX_MODE, RX_MODE_ENABLE); tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
tr32(MAC_RX_MODE);
udelay(10); udelay(10);
} }
...@@ -894,10 +891,9 @@ static int tg3_set_power_state(struct tg3 *tp, int state) ...@@ -894,10 +891,9 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
base_val |= (CLOCK_CTRL_RXCLK_DISABLE | base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
CLOCK_CTRL_TXCLK_DISABLE); CLOCK_CTRL_TXCLK_DISABLE);
tw32(TG3PCI_CLOCK_CTRL, base_val | tw32_f(TG3PCI_CLOCK_CTRL, base_val |
CLOCK_CTRL_ALTCLK | CLOCK_CTRL_ALTCLK |
CLOCK_CTRL_PWRDOWN_PLL133); CLOCK_CTRL_PWRDOWN_PLL133);
tr32(TG3PCI_CLOCK_CTRL);
udelay(40); udelay(40);
} else { } else {
u32 newbits1, newbits2; u32 newbits1, newbits2;
...@@ -916,12 +912,10 @@ static int tg3_set_power_state(struct tg3 *tp, int state) ...@@ -916,12 +912,10 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
} }
tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1); tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
tr32(TG3PCI_CLOCK_CTRL);
udelay(40); udelay(40);
tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2); tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
tr32(TG3PCI_CLOCK_CTRL);
udelay(40); udelay(40);
if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
...@@ -936,8 +930,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state) ...@@ -936,8 +930,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
newbits3 = CLOCK_CTRL_44MHZ_CORE; newbits3 = CLOCK_CTRL_44MHZ_CORE;
} }
tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits3); tw32_f(TG3PCI_CLOCK_CTRL,
tr32(TG3PCI_CLOCK_CTRL); tp->pci_clock_ctrl | newbits3);
udelay(40); udelay(40);
} }
} }
...@@ -1228,17 +1222,15 @@ static int tg3_setup_copper_phy(struct tg3 *tp) ...@@ -1228,17 +1222,15 @@ static int tg3_setup_copper_phy(struct tg3 *tp)
tw32(MAC_EVENT, 0); tw32(MAC_EVENT, 0);
tw32(MAC_STATUS, tw32_f(MAC_STATUS,
(MAC_STATUS_SYNC_CHANGED | (MAC_STATUS_SYNC_CHANGED |
MAC_STATUS_CFG_CHANGED | MAC_STATUS_CFG_CHANGED |
MAC_STATUS_MI_COMPLETION | MAC_STATUS_MI_COMPLETION |
MAC_STATUS_LNKSTATE_CHANGED)); MAC_STATUS_LNKSTATE_CHANGED));
tr32(MAC_STATUS);
udelay(40); udelay(40);
tp->mi_mode = MAC_MI_MODE_BASE; tp->mi_mode = MAC_MI_MODE_BASE;
tw32(MAC_MI_MODE, tp->mi_mode); tw32_f(MAC_MI_MODE, tp->mi_mode);
tr32(MAC_MI_MODE);
udelay(40); udelay(40);
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02); tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
...@@ -1430,24 +1422,19 @@ static int tg3_setup_copper_phy(struct tg3 *tp) ...@@ -1430,24 +1422,19 @@ static int tg3_setup_copper_phy(struct tg3 *tp)
if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 && if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
tw32(MAC_MI_MODE, tp->mi_mode); tw32_f(MAC_MI_MODE, tp->mi_mode);
tr32(MAC_MI_MODE);
udelay(40); udelay(40);
} }
tw32(MAC_MODE, tp->mac_mode); tw32_f(MAC_MODE, tp->mac_mode);
tr32(MAC_MODE);
udelay(40); udelay(40);
if (tp->tg3_flags & if (tp->tg3_flags & (TG3_FLAG_USE_LINKCHG_REG | TG3_FLAG_POLL_SERDES)) {
(TG3_FLAG_USE_LINKCHG_REG |
TG3_FLAG_POLL_SERDES)) {
/* Polled via timer. */ /* Polled via timer. */
tw32(MAC_EVENT, 0); tw32_f(MAC_EVENT, 0);
} else { } else {
tw32(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
} }
tr32(MAC_EVENT);
udelay(40); udelay(40);
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
...@@ -1456,10 +1443,9 @@ static int tg3_setup_copper_phy(struct tg3 *tp) ...@@ -1456,10 +1443,9 @@ static int tg3_setup_copper_phy(struct tg3 *tp)
((tp->tg3_flags & TG3_FLAG_PCIX_MODE) || ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
(tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) { (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
udelay(120); udelay(120);
tw32(MAC_STATUS, tw32_f(MAC_STATUS,
(MAC_STATUS_SYNC_CHANGED | (MAC_STATUS_SYNC_CHANGED |
MAC_STATUS_CFG_CHANGED)); MAC_STATUS_CFG_CHANGED));
tr32(MAC_STATUS);
udelay(40); udelay(40);
tg3_write_mem(tp, tg3_write_mem(tp,
NIC_SRAM_FIRMWARE_MBOX, NIC_SRAM_FIRMWARE_MBOX,
...@@ -1621,8 +1607,7 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp, ...@@ -1621,8 +1607,7 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
ap->txconfig = 0; ap->txconfig = 0;
tw32(MAC_TX_AUTO_NEG, 0); tw32(MAC_TX_AUTO_NEG, 0);
tp->mac_mode |= MAC_MODE_SEND_CONFIGS; tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
tw32(MAC_MODE, tp->mac_mode); tw32_f(MAC_MODE, tp->mac_mode);
tr32(MAC_MODE);
udelay(40); udelay(40);
ret = ANEG_TIMER_ENAB; ret = ANEG_TIMER_ENAB;
...@@ -1647,8 +1632,7 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp, ...@@ -1647,8 +1632,7 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1); ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
tw32(MAC_TX_AUTO_NEG, ap->txconfig); tw32(MAC_TX_AUTO_NEG, ap->txconfig);
tp->mac_mode |= MAC_MODE_SEND_CONFIGS; tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
tw32(MAC_MODE, tp->mac_mode); tw32_f(MAC_MODE, tp->mac_mode);
tr32(MAC_MODE);
udelay(40); udelay(40);
ap->state = ANEG_STATE_ABILITY_DETECT; ap->state = ANEG_STATE_ABILITY_DETECT;
...@@ -1664,8 +1648,7 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp, ...@@ -1664,8 +1648,7 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
ap->txconfig |= ANEG_CFG_ACK; ap->txconfig |= ANEG_CFG_ACK;
tw32(MAC_TX_AUTO_NEG, ap->txconfig); tw32(MAC_TX_AUTO_NEG, ap->txconfig);
tp->mac_mode |= MAC_MODE_SEND_CONFIGS; tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
tw32(MAC_MODE, tp->mac_mode); tw32_f(MAC_MODE, tp->mac_mode);
tr32(MAC_MODE);
udelay(40); udelay(40);
ap->state = ANEG_STATE_ACK_DETECT; ap->state = ANEG_STATE_ACK_DETECT;
...@@ -1751,8 +1734,7 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp, ...@@ -1751,8 +1734,7 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
case ANEG_STATE_IDLE_DETECT_INIT: case ANEG_STATE_IDLE_DETECT_INIT:
ap->link_time = ap->cur_time; ap->link_time = ap->cur_time;
tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
tw32(MAC_MODE, tp->mac_mode); tw32_f(MAC_MODE, tp->mac_mode);
tr32(MAC_MODE);
udelay(40); udelay(40);
ap->state = ANEG_STATE_IDLE_DETECT; ap->state = ANEG_STATE_IDLE_DETECT;
...@@ -1809,8 +1791,7 @@ static int tg3_setup_fiber_phy(struct tg3 *tp) ...@@ -1809,8 +1791,7 @@ static int tg3_setup_fiber_phy(struct tg3 *tp)
tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
tw32(MAC_MODE, tp->mac_mode); tw32_f(MAC_MODE, tp->mac_mode);
tr32(MAC_MODE);
udelay(40); udelay(40);
/* Reset when initting first time or we have a link. */ /* Reset when initting first time or we have a link. */
...@@ -1858,10 +1839,9 @@ static int tg3_setup_fiber_phy(struct tg3 *tp) ...@@ -1858,10 +1839,9 @@ static int tg3_setup_fiber_phy(struct tg3 *tp)
/* Enable link change interrupt unless serdes polling. */ /* Enable link change interrupt unless serdes polling. */
if (!(tp->tg3_flags & TG3_FLAG_POLL_SERDES)) if (!(tp->tg3_flags & TG3_FLAG_POLL_SERDES))
tw32(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
else else
tw32(MAC_EVENT, 0); tw32_f(MAC_EVENT, 0);
tr32(MAC_EVENT);
udelay(40); udelay(40);
current_link_up = 0; current_link_up = 0;
...@@ -1879,12 +1859,10 @@ static int tg3_setup_fiber_phy(struct tg3 *tp) ...@@ -1879,12 +1859,10 @@ static int tg3_setup_fiber_phy(struct tg3 *tp)
tw32(MAC_TX_AUTO_NEG, 0); tw32(MAC_TX_AUTO_NEG, 0);
tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
tw32(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
tr32(MAC_MODE);
udelay(40); udelay(40);
tw32(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
tr32(MAC_MODE);
udelay(40); udelay(40);
aninfo.state = ANEG_STATE_UNKNOWN; aninfo.state = ANEG_STATE_UNKNOWN;
...@@ -1900,8 +1878,7 @@ static int tg3_setup_fiber_phy(struct tg3 *tp) ...@@ -1900,8 +1878,7 @@ static int tg3_setup_fiber_phy(struct tg3 *tp)
} }
tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
tw32(MAC_MODE, tp->mac_mode); tw32_f(MAC_MODE, tp->mac_mode);
tr32(MAC_MODE);
udelay(40); udelay(40);
if (status == ANEG_DONE && if (status == ANEG_DONE &&
...@@ -1925,10 +1902,9 @@ static int tg3_setup_fiber_phy(struct tg3 *tp) ...@@ -1925,10 +1902,9 @@ static int tg3_setup_fiber_phy(struct tg3 *tp)
} }
for (i = 0; i < 60; i++) { for (i = 0; i < 60; i++) {
udelay(20); udelay(20);
tw32(MAC_STATUS, tw32_f(MAC_STATUS,
(MAC_STATUS_SYNC_CHANGED | (MAC_STATUS_SYNC_CHANGED |
MAC_STATUS_CFG_CHANGED)); MAC_STATUS_CFG_CHANGED));
tr32(MAC_STATUS);
udelay(40); udelay(40);
if ((tr32(MAC_STATUS) & if ((tr32(MAC_STATUS) &
(MAC_STATUS_SYNC_CHANGED | (MAC_STATUS_SYNC_CHANGED |
...@@ -1946,8 +1922,7 @@ static int tg3_setup_fiber_phy(struct tg3 *tp) ...@@ -1946,8 +1922,7 @@ static int tg3_setup_fiber_phy(struct tg3 *tp)
} }
tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
tw32(MAC_MODE, tp->mac_mode); tw32_f(MAC_MODE, tp->mac_mode);
tr32(MAC_MODE);
udelay(40); udelay(40);
tp->hw_status->status = tp->hw_status->status =
...@@ -1956,10 +1931,9 @@ static int tg3_setup_fiber_phy(struct tg3 *tp) ...@@ -1956,10 +1931,9 @@ static int tg3_setup_fiber_phy(struct tg3 *tp)
for (i = 0; i < 100; i++) { for (i = 0; i < 100; i++) {
udelay(20); udelay(20);
tw32(MAC_STATUS, tw32_f(MAC_STATUS,
(MAC_STATUS_SYNC_CHANGED | (MAC_STATUS_SYNC_CHANGED |
MAC_STATUS_CFG_CHANGED)); MAC_STATUS_CFG_CHANGED));
tr32(MAC_STATUS);
udelay(40); udelay(40);
if ((tr32(MAC_STATUS) & if ((tr32(MAC_STATUS) &
(MAC_STATUS_SYNC_CHANGED | (MAC_STATUS_SYNC_CHANGED |
...@@ -1995,12 +1969,10 @@ static int tg3_setup_fiber_phy(struct tg3 *tp) ...@@ -1995,12 +1969,10 @@ static int tg3_setup_fiber_phy(struct tg3 *tp)
} }
if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0) { if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0) {
tw32(MAC_MODE, tp->mac_mode | MAC_MODE_LINK_POLARITY); tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_LINK_POLARITY);
tr32(MAC_MODE);
udelay(40); udelay(40);
if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) { if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
tw32(MAC_MODE, tp->mac_mode); tw32_f(MAC_MODE, tp->mac_mode);
tr32(MAC_MODE);
udelay(40); udelay(40);
} }
} }
...@@ -3328,8 +3300,7 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit) ...@@ -3328,8 +3300,7 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit)
val = tr32(ofs); val = tr32(ofs);
val &= ~enable_bit; val &= ~enable_bit;
tw32(ofs, val); tw32_f(ofs, val);
tr32(ofs);
for (i = 0; i < MAX_WAIT_CNT; i++) { for (i = 0; i < MAX_WAIT_CNT; i++) {
udelay(100); udelay(100);
...@@ -3356,8 +3327,7 @@ static int tg3_abort_hw(struct tg3 *tp) ...@@ -3356,8 +3327,7 @@ static int tg3_abort_hw(struct tg3 *tp)
tg3_disable_ints(tp); tg3_disable_ints(tp);
tp->rx_mode &= ~RX_MODE_ENABLE; tp->rx_mode &= ~RX_MODE_ENABLE;
tw32(MAC_RX_MODE, tp->rx_mode); tw32_f(MAC_RX_MODE, tp->rx_mode);
tr32(MAC_RX_MODE);
udelay(10); udelay(10);
err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE); err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE);
...@@ -3378,13 +3348,11 @@ static int tg3_abort_hw(struct tg3 *tp) ...@@ -3378,13 +3348,11 @@ static int tg3_abort_hw(struct tg3 *tp)
goto out; goto out;
tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
tw32(MAC_MODE, tp->mac_mode); tw32_f(MAC_MODE, tp->mac_mode);
tr32(MAC_MODE);
udelay(40); udelay(40);
tp->tx_mode &= ~TX_MODE_ENABLE; tp->tx_mode &= ~TX_MODE_ENABLE;
tw32(MAC_TX_MODE, tp->tx_mode); tw32_f(MAC_TX_MODE, tp->tx_mode);
tr32(MAC_TX_MODE);
for (i = 0; i < MAX_WAIT_CNT; i++) { for (i = 0; i < MAX_WAIT_CNT; i++) {
udelay(100); udelay(100);
...@@ -3710,8 +3678,7 @@ static int tg3_halt_cpu(struct tg3 *tp, u32 offset) ...@@ -3710,8 +3678,7 @@ static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
} }
tw32(offset + CPU_STATE, 0xffffffff); tw32(offset + CPU_STATE, 0xffffffff);
tw32(offset + CPU_MODE, CPU_MODE_HALT); tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
tr32(offset + CPU_MODE);
udelay(10); udelay(10);
} else { } else {
for (i = 0; i < 10000; i++) { for (i = 0; i < 10000; i++) {
...@@ -3834,20 +3801,14 @@ static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) ...@@ -3834,20 +3801,14 @@ static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
/* Now startup only the RX cpu. */ /* Now startup only the RX cpu. */
tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
tw32(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR); tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
/* Flush posted writes. */
tr32(RX_CPU_BASE + CPU_PC);
for (i = 0; i < 5; i++) { for (i = 0; i < 5; i++) {
if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR) if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
break; break;
tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
tw32(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR); tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
/* Flush posted writes. */
tr32(RX_CPU_BASE + CPU_PC);
udelay(1000); udelay(1000);
} }
if (i >= 5) { if (i >= 5) {
...@@ -3858,10 +3819,7 @@ static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) ...@@ -3858,10 +3819,7 @@ static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
return -ENODEV; return -ENODEV;
} }
tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
tw32(RX_CPU_BASE + CPU_MODE, 0x00000000); tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
/* Flush posted writes. */
tr32(RX_CPU_BASE + CPU_MODE);
return 0; return 0;
} }
...@@ -4419,20 +4377,14 @@ static int tg3_load_tso_firmware(struct tg3 *tp) ...@@ -4419,20 +4377,14 @@ static int tg3_load_tso_firmware(struct tg3 *tp)
/* Now startup the cpu. */ /* Now startup the cpu. */
tw32(cpu_base + CPU_STATE, 0xffffffff); tw32(cpu_base + CPU_STATE, 0xffffffff);
tw32(cpu_base + CPU_PC, info.text_base); tw32_f(cpu_base + CPU_PC, info.text_base);
/* Flush posted writes. */
tr32(cpu_base + CPU_PC);
for (i = 0; i < 5; i++) { for (i = 0; i < 5; i++) {
if (tr32(cpu_base + CPU_PC) == info.text_base) if (tr32(cpu_base + CPU_PC) == info.text_base)
break; break;
tw32(cpu_base + CPU_STATE, 0xffffffff); tw32(cpu_base + CPU_STATE, 0xffffffff);
tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
tw32(cpu_base + CPU_PC, info.text_base); tw32_f(cpu_base + CPU_PC, info.text_base);
/* Flush posted writes. */
tr32(cpu_base + CPU_PC);
udelay(1000); udelay(1000);
} }
if (i >= 5) { if (i >= 5) {
...@@ -4443,11 +4395,7 @@ static int tg3_load_tso_firmware(struct tg3 *tp) ...@@ -4443,11 +4395,7 @@ static int tg3_load_tso_firmware(struct tg3 *tp)
return -ENODEV; return -ENODEV;
} }
tw32(cpu_base + CPU_STATE, 0xffffffff); tw32(cpu_base + CPU_STATE, 0xffffffff);
tw32(cpu_base + CPU_MODE, 0x00000000); tw32_f(cpu_base + CPU_MODE, 0x00000000);
/* Flush posted writes. */
tr32(cpu_base + CPU_MODE);
return 0; return 0;
} }
...@@ -4556,10 +4504,9 @@ static int tg3_reset_hw(struct tg3 *tp) ...@@ -4556,10 +4504,9 @@ static int tg3_reset_hw(struct tg3 *tp)
NIC_SRAM_FIRMWARE_MBOX_MAGIC1); NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
if (tp->phy_id == PHY_ID_SERDES) { if (tp->phy_id == PHY_ID_SERDES) {
tp->mac_mode = MAC_MODE_PORT_MODE_TBI; tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
tw32(MAC_MODE, tp->mac_mode); tw32_f(MAC_MODE, tp->mac_mode);
} else } else
tw32(MAC_MODE, 0); tw32_f(MAC_MODE, 0);
tr32(MAC_MODE);
udelay(40); udelay(40);
/* Wait for firmware initialization to complete. */ /* Wait for firmware initialization to complete. */
...@@ -4589,8 +4536,7 @@ static int tg3_reset_hw(struct tg3 *tp) ...@@ -4589,8 +4536,7 @@ static int tg3_reset_hw(struct tg3 *tp)
* other revision. * other revision.
*/ */
tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
tr32(TG3PCI_CLOCK_CTRL);
if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
...@@ -4934,24 +4880,21 @@ static int tg3_reset_hw(struct tg3 *tp) ...@@ -4934,24 +4880,21 @@ static int tg3_reset_hw(struct tg3 *tp)
tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
tw32(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
tr32(MAC_MODE);
udelay(40); udelay(40);
tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
GRC_LCLCTRL_GPIO_OUTPUT1); GRC_LCLCTRL_GPIO_OUTPUT1);
tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
tr32(GRC_LOCAL_CTRL);
udelay(100); udelay(100);
tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0); tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
tr32(MAILBOX_INTERRUPT_0); tr32(MAILBOX_INTERRUPT_0);
if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
tw32(DMAC_MODE, DMAC_MODE_ENABLE); tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
tr32(DMAC_MODE);
udelay(40); udelay(40);
} }
...@@ -4964,8 +4907,7 @@ static int tg3_reset_hw(struct tg3 *tp) ...@@ -4964,8 +4907,7 @@ static int tg3_reset_hw(struct tg3 *tp)
(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) != 0 && (tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) != 0 &&
!(tp->tg3_flags2 & TG3_FLG2_IS_5788)) !(tp->tg3_flags2 & TG3_FLG2_IS_5788))
val |= WDMAC_MODE_RX_ACCEL; val |= WDMAC_MODE_RX_ACCEL;
tw32(WDMAC_MODE, val); tw32_f(WDMAC_MODE, val);
tr32(WDMAC_MODE);
udelay(40); udelay(40);
if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) { if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
...@@ -4983,8 +4925,7 @@ static int tg3_reset_hw(struct tg3 *tp) ...@@ -4983,8 +4925,7 @@ static int tg3_reset_hw(struct tg3 *tp)
tw32(TG3PCI_X_CAPS, val); tw32(TG3PCI_X_CAPS, val);
} }
tw32(RDMAC_MODE, rdmac_mode); tw32_f(RDMAC_MODE, rdmac_mode);
tr32(RDMAC_MODE);
udelay(40); udelay(40);
tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
...@@ -5013,13 +4954,11 @@ static int tg3_reset_hw(struct tg3 *tp) ...@@ -5013,13 +4954,11 @@ static int tg3_reset_hw(struct tg3 *tp)
#endif #endif
tp->tx_mode = TX_MODE_ENABLE; tp->tx_mode = TX_MODE_ENABLE;
tw32(MAC_TX_MODE, tp->tx_mode); tw32_f(MAC_TX_MODE, tp->tx_mode);
tr32(MAC_TX_MODE);
udelay(100); udelay(100);
tp->rx_mode = RX_MODE_ENABLE; tp->rx_mode = RX_MODE_ENABLE;
tw32(MAC_RX_MODE, tp->rx_mode); tw32_f(MAC_RX_MODE, tp->rx_mode);
tr32(MAC_RX_MODE);
udelay(10); udelay(10);
if (tp->link_config.phy_is_low_power) { if (tp->link_config.phy_is_low_power) {
...@@ -5030,19 +4969,16 @@ static int tg3_reset_hw(struct tg3 *tp) ...@@ -5030,19 +4969,16 @@ static int tg3_reset_hw(struct tg3 *tp)
} }
tp->mi_mode = MAC_MI_MODE_BASE; tp->mi_mode = MAC_MI_MODE_BASE;
tw32(MAC_MI_MODE, tp->mi_mode); tw32_f(MAC_MI_MODE, tp->mi_mode);
tr32(MAC_MI_MODE);
udelay(40); udelay(40);
tw32(MAC_LED_CTRL, 0); tw32(MAC_LED_CTRL, 0);
tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
if (tp->phy_id == PHY_ID_SERDES) { if (tp->phy_id == PHY_ID_SERDES) {
tw32(MAC_RX_MODE, RX_MODE_RESET); tw32_f(MAC_RX_MODE, RX_MODE_RESET);
tr32(MAC_RX_MODE);
udelay(10); udelay(10);
} }
tw32(MAC_RX_MODE, tp->rx_mode); tw32_f(MAC_RX_MODE, tp->rx_mode);
tr32(MAC_RX_MODE);
udelay(10); udelay(10);
if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
...@@ -5051,8 +4987,7 @@ static int tg3_reset_hw(struct tg3 *tp) ...@@ -5051,8 +4987,7 @@ static int tg3_reset_hw(struct tg3 *tp)
/* Prevent chip from dropping frames when flow control /* Prevent chip from dropping frames when flow control
* is enabled. * is enabled.
*/ */
tw32(MAC_LOW_WMARK_MAX_RX_FRAME, 2); tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
tr32(MAC_LOW_WMARK_MAX_RX_FRAME);
err = tg3_setup_phy(tp); err = tg3_setup_phy(tp);
if (err) if (err)
...@@ -5250,13 +5185,11 @@ static void tg3_timer(unsigned long __opaque) ...@@ -5250,13 +5185,11 @@ static void tg3_timer(unsigned long __opaque)
need_setup = 1; need_setup = 1;
} }
if (need_setup) { if (need_setup) {
tw32(MAC_MODE, tw32_f(MAC_MODE,
(tp->mac_mode & (tp->mac_mode &
~MAC_MODE_PORT_MODE_MASK)); ~MAC_MODE_PORT_MODE_MASK));
tr32(MAC_MODE);
udelay(40); udelay(40);
tw32(MAC_MODE, tp->mac_mode); tw32_f(MAC_MODE, tp->mac_mode);
tr32(MAC_MODE);
udelay(40); udelay(40);
tg3_setup_phy(tp); tg3_setup_phy(tp);
} }
...@@ -5811,8 +5744,7 @@ static void __tg3_set_rx_mode(struct net_device *dev) ...@@ -5811,8 +5744,7 @@ static void __tg3_set_rx_mode(struct net_device *dev)
if (rx_mode != tp->rx_mode) { if (rx_mode != tp->rx_mode) {
tp->rx_mode = rx_mode; tp->rx_mode = rx_mode;
tw32(MAC_RX_MODE, rx_mode); tw32_f(MAC_RX_MODE, rx_mode);
tr32(MAC_RX_MODE);
udelay(10); udelay(10);
} }
} }
...@@ -6281,7 +6213,7 @@ static void __devinit tg3_nvram_init(struct tg3 *tp) ...@@ -6281,7 +6213,7 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
if (tp->tg3_flags2 & TG3_FLG2_SUN_5704) if (tp->tg3_flags2 & TG3_FLG2_SUN_5704)
return; return;
tw32(GRC_EEPROM_ADDR, tw32_f(GRC_EEPROM_ADDR,
(EEPROM_ADDR_FSM_RESET | (EEPROM_ADDR_FSM_RESET |
(EEPROM_DEFAULT_CLOCK_PERIOD << (EEPROM_DEFAULT_CLOCK_PERIOD <<
EEPROM_ADDR_CLKPERD_SHIFT))); EEPROM_ADDR_CLKPERD_SHIFT)));
...@@ -6291,9 +6223,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp) ...@@ -6291,9 +6223,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
udelay(10); udelay(10);
/* Enable seeprom accesses. */ /* Enable seeprom accesses. */
tw32(GRC_LOCAL_CTRL, tw32_f(GRC_LOCAL_CTRL,
tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
tr32(GRC_LOCAL_CTRL);
udelay(100); udelay(100);
if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
...@@ -6922,8 +6853,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) ...@@ -6922,8 +6853,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
tp->coalesce_mode |= HOSTCC_MODE_32BYTE; tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
/* Initialize MAC MI mode, polling disabled. */ /* Initialize MAC MI mode, polling disabled. */
tw32(MAC_MI_MODE, tp->mi_mode); tw32_f(MAC_MI_MODE, tp->mi_mode);
tr32(MAC_MI_MODE);
udelay(40); udelay(40);
/* Initialize data/descriptor byte/word swapping. */ /* Initialize data/descriptor byte/word swapping. */
...@@ -7198,14 +7128,12 @@ static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dm ...@@ -7198,14 +7128,12 @@ static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dm
if (to_device) { if (to_device) {
test_desc.cqid_sqid = (13 << 8) | 2; test_desc.cqid_sqid = (13 << 8) | 2;
tw32(RDMAC_MODE, RDMAC_MODE_ENABLE); tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
tr32(RDMAC_MODE);
udelay(40); udelay(40);
} else { } else {
test_desc.cqid_sqid = (16 << 8) | 7; test_desc.cqid_sqid = (16 << 8) | 7;
tw32(WDMAC_MODE, WDMAC_MODE_ENABLE); tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
tr32(WDMAC_MODE);
udelay(40); udelay(40);
} }
test_desc.flags = 0x00000005; test_desc.flags = 0x00000005;
......
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