Commit b4a7bd7a authored by addy ke's avatar addy ke Committed by Wolfram Sang

i2c: rk3x: fix divisor calculation for SCL frequency

I2C_CLKDIV register descripted in the previous version of
RK3x chip manual is incorrect. Plus 1 is required.

The correct formula:
- T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
- T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
- (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
- SCL = PCLK / (CLK Divsor)

It will be updated to the latest version of chip manual.
Signed-off-by: default avatarAddy Ke <addy.ke@rock-chips.com>
Reviewed-by: default avatarDoug Anderson <dianders@chromium.org>
Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
Cc: stable@kernel.org
parent a4780d03
...@@ -433,12 +433,11 @@ static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate) ...@@ -433,12 +433,11 @@ static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
unsigned long i2c_rate = clk_get_rate(i2c->clk); unsigned long i2c_rate = clk_get_rate(i2c->clk);
unsigned int div; unsigned int div;
/* SCL rate = (clk rate) / (8 * DIV) */ /* set DIV = DIVH = DIVL
div = DIV_ROUND_UP(i2c_rate, scl_rate * 8); * SCL rate = (clk rate) / (8 * (DIVH + 1 + DIVL + 1))
* = (clk rate) / (16 * (DIV + 1))
/* The lower and upper half of the CLKDIV reg describe the length of */
* SCL low & high periods. */ div = DIV_ROUND_UP(i2c_rate, scl_rate * 16) - 1;
div = DIV_ROUND_UP(div, 2);
i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV); i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV);
} }
......
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