Commit b62e4197 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'mips_5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS upates from Thomas Bogendoerfer:

 - improvements for Loongson64

 - extended ingenic support

 - removal of not maintained paravirt system type

 - cleanups and fixes

* tag 'mips_5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (81 commits)
  MIPS: SGI-IP27: always enable NUMA in Kconfig
  MAINTAINERS: Update KVM/MIPS maintainers
  MIPS: Update default config file for Loongson-3
  MIPS: KVM: Add kvm guest support for Loongson-3
  dt-bindings: mips: Document Loongson kvm guest board
  MIPS: handle Loongson-specific GSExc exception
  MIPS: add definitions for Loongson-specific CP0.Diag1 register
  MIPS: only register FTLBPar exception handler for supported models
  MIPS: ingenic: Hardcode mem size for qi,lb60 board
  MIPS: DTS: ingenic/qi,lb60: Add model and memory node
  MIPS: ingenic: Use fw_passed_dtb even if CONFIG_BUILTIN_DTB
  MIPS: head.S: Init fw_passed_dtb to builtin DTB
  of: address: Fix parser address/size cells initialization
  of_address: Guard of_bus_pci_get_flags with CONFIG_PCI
  MIPS: DTS: Fix number of msi vectors for Loongson64G
  MIPS: Loongson64: Add ISA node for LS7A PCH
  MIPS: Loongson64: DTS: Fix ISA and PCI I/O ranges for RS780E PCH
  MIPS: Loongson64: Enlarge IO_SPACE_LIMIT
  MIPS: Loongson64: Process ISA Node in DeviceTree
  of_address: Add bus type match for pci ranges parser
  ...
parents 40ddad19 6c86a302
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/mti,mips-cdmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MIPS Common Device Memory Map
description: |
Defines a location of the MIPS Common Device Memory Map registers.
maintainers:
- James Hogan <jhogan@kernel.org>
properties:
compatible:
const: mti,mips-cdmm
reg:
description: |
Base address and size of an unoccupied memory region, which will be
used to map the MIPS CDMM registers block.
maxItems: 1
required:
- compatible
- reg
examples:
- |
cdmm@1bde8000 {
compatible = "mti,mips-cdmm";
reg = <0x1bde8000 0x8000>;
};
...
MIPS Global Interrupt Controller (GIC)
The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
It also supports local (per-processor) interrupts and software-generated
interrupts which can be used as IPIs. The GIC also includes a free-running
global timer, per-CPU count/compare timers, and a watchdog.
Required properties:
- compatible : Should be "mti,gic".
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt specifier. Should be 3.
- The first cell is the type of interrupt, local or shared.
See <include/dt-bindings/interrupt-controller/mips-gic.h>.
- The second cell is the GIC interrupt number.
- The third cell encodes the interrupt flags.
See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid
flags.
Optional properties:
- reg : Base address and length of the GIC registers. If not present,
the base address reported by the hardware GCR_GIC_BASE will be used.
- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
to which the GIC may not route interrupts. Valid values are 2 - 7.
This property is ignored if the CPU is started in EIC mode.
- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
reserved for IPIs.
It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
of the reserved range.
If not specified, the driver will allocate the last 2 * number of VPEs in the
system.
Required properties for timer sub-node:
- compatible : Should be "mti,gic-timer".
- interrupts : Interrupt for the GIC local timer.
Optional properties for timer sub-node:
- clocks : GIC timer operating clock.
- clock-frequency : Clock frequency at which the GIC timers operate.
Note that one of clocks or clock-frequency must be specified.
Example:
gic: interrupt-controller@1bdc0000 {
compatible = "mti,gic";
reg = <0x1bdc0000 0x20000>;
interrupt-controller;
#interrupt-cells = <3>;
mti,reserved-cpu-vectors = <7>;
mti,reserved-ipi-vectors = <40 8>;
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
clock-frequency = <50000000>;
};
};
uart@18101400 {
...
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
...
};
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MIPS Global Interrupt Controller
maintainers:
- Paul Burton <paulburton@kernel.org>
- Thomas Bogendoerfer <tsbogend@alpha.franken.de>
description: |
The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
It also supports local (per-processor) interrupts and software-generated
interrupts which can be used as IPIs. The GIC also includes a free-running
global timer, per-CPU count/compare timers, and a watchdog.
properties:
compatible:
const: mti,gic
"#interrupt-cells":
const: 3
description: |
The 1st cell is the type of interrupt: local or shared defined in the
file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
GIC interrupt number. The 3d cell encodes the interrupt flags setting up
the IRQ trigger modes, which are defined in the file
'dt-bindings/interrupt-controller/irq.h'.
reg:
description: |
Base address and length of the GIC registers space. If not present,
the base address reported by the hardware GCR_GIC_BASE will be used.
maxItems: 1
interrupt-controller: true
mti,reserved-cpu-vectors:
description: |
Specifies the list of CPU interrupt vectors to which the GIC may not
route interrupts. This property is ignored if the CPU is started in EIC
mode.
allOf:
- $ref: /schemas/types.yaml#definitions/uint32-array
- minItems: 1
maxItems: 6
uniqueItems: true
items:
minimum: 2
maximum: 7
mti,reserved-ipi-vectors:
description: |
Specifies the range of GIC interrupts that are reserved for IPIs.
It accepts two values: the 1st is the starting interrupt and the 2nd is
the size of the reserved range. If not specified, the driver will
allocate the last (2 * number of VPEs in the system).
allOf:
- $ref: /schemas/types.yaml#definitions/uint32-array
- items:
- minimum: 0
maximum: 254
- minimum: 2
maximum: 254
timer:
type: object
description: |
MIPS GIC includes a free-running global timer, per-CPU count/compare
timers, and a watchdog. Currently only the GIC Timer is supported.
properties:
compatible:
const: mti,gic-timer
interrupts:
description: |
Interrupt for the GIC local timer, so normally it's suppose to be of
<GIC_LOCAL X IRQ_TYPE_NONE> format.
maxItems: 1
clocks:
maxItems: 1
clock-frequency: true
required:
- compatible
- interrupts
oneOf:
- required:
- clocks
- required:
- clock-frequency
additionalProperties: false
unevaluatedProperties: false
required:
- compatible
- "#interrupt-cells"
- interrupt-controller
examples:
- |
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
interrupt-controller@1bdc0000 {
compatible = "mti,gic";
reg = <0x1bdc0000 0x20000>;
interrupt-controller;
#interrupt-cells = <3>;
mti,reserved-cpu-vectors = <7>;
mti,reserved-ipi-vectors = <40 8>;
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
clock-frequency = <50000000>;
};
};
- |
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
interrupt-controller@1bdc0000 {
compatible = "mti,gic";
reg = <0x1bdc0000 0x20000>;
interrupt-controller;
#interrupt-cells = <3>;
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
clocks = <&cpu_pll>;
};
};
- |
interrupt-controller {
compatible = "mti,gic";
interrupt-controller;
#interrupt-cells = <3>;
};
...
...@@ -8,7 +8,8 @@ title: Ingenic XBurst based Platforms Device Tree Bindings ...@@ -8,7 +8,8 @@ title: Ingenic XBurst based Platforms Device Tree Bindings
maintainers: maintainers:
- 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
description: |
description:
Devices with a Ingenic XBurst CPU shall have the following properties. Devices with a Ingenic XBurst CPU shall have the following properties.
properties: properties:
...@@ -22,6 +23,11 @@ properties: ...@@ -22,6 +23,11 @@ properties:
- const: qi,lb60 - const: qi,lb60
- const: ingenic,jz4740 - const: ingenic,jz4740
- description: YLM RetroMini RS-90
items:
- const: ylm,rs90
- const: ingenic,jz4725b
- description: Game Consoles Worldwide GCW Zero - description: Game Consoles Worldwide GCW Zero
items: items:
- const: gcw,zero - const: gcw,zero
...@@ -32,8 +38,13 @@ properties: ...@@ -32,8 +38,13 @@ properties:
- const: img,ci20 - const: img,ci20
- const: ingenic,jz4780 - const: ingenic,jz4780
- description: YSH & ATIL General Board CU Neo - description: YSH & ATIL General Board, CU1000 Module with Neo Backplane
items: items:
- const: yna,cu1000-neo - const: yna,cu1000-neo
- const: ingenic,x1000 - const: ingenic,x1000e
- description: YSH & ATIL General Board, CU1830 Module with Neo Backplane
items:
- const: yna,cu1830-neo
- const: ingenic,x1830
... ...
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Bindings for Ingenic XBurst family CPUs
maintainers:
- 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
description:
Ingenic XBurst family CPUs shall have the following properties.
properties:
compatible:
oneOf:
- description: Ingenic XBurst®1 CPU Cores
enum:
- ingenic,xburst-mxu1.0
- ingenic,xburst-fpu1.0-mxu1.1
- ingenic,xburst-fpu2.0-mxu2.0
- description: Ingenic XBurst®2 CPU Cores
enum:
- ingenic,xburst2-fpu2.1-mxu2.1-smt
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- device_type
- compatible
- reg
- clocks
examples:
- |
#include <dt-bindings/clock/jz4780-cgu.h>
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
reg = <0>;
clocks = <&cgu JZ4780_CLK_CPU>;
clock-names = "cpu";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
reg = <1>;
clocks = <&cgu JZ4780_CLK_CORE1>;
clock-names = "cpu";
};
};
...
...@@ -17,11 +17,23 @@ properties: ...@@ -17,11 +17,23 @@ properties:
compatible: compatible:
oneOf: oneOf:
- description: Generic Loongson3 Quad Core + RS780E - description: Classic Loongson64 Quad Core + LS7A
items: items:
- const: loongson,loongson3-4core-rs780e - const: loongson,loongson64c-4core-ls7a
- description: Generic Loongson3 Octa Core + RS780E - description: Classic Loongson64 Quad Core + RS780E
items: items:
- const: loongson,loongson3-8core-rs780e - const: loongson,loongson64c-4core-rs780e
- description: Classic Loongson64 Octa Core + RS780E
items:
- const: loongson,loongson64c-8core-rs780e
- description: Generic Loongson64 Quad Core + LS7A
items:
- const: loongson,loongson64g-4core-ls7a
- description: Virtual Loongson64 Quad Core + VirtIO
items:
- const: loongson,loongson64v-4core-virtio
... ...
Binding for MIPS Cluster Power Controller (CPC).
This binding allows a system to specify where the CPC registers are
located.
Required properties:
compatible : Should be "mti,mips-cpc".
regs: Should describe the address & size of the CPC register region.
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/mti,mips-cpc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MIPS Cluster Power Controller
description: |
Defines a location of the MIPS Cluster Power Controller registers.
maintainers:
- Paul Burton <paulburton@kernel.org>
properties:
compatible:
const: mti,mips-cpc
reg:
description: |
Base address and size of an unoccupied memory region, which will be
used to map the MIPS CPC registers block.
maxItems: 1
required:
- compatible
- reg
examples:
- |
cpc@1bde0000 {
compatible = "mti,mips-cpc";
reg = <0x1bde0000 0x8000>;
};
...
...@@ -116,7 +116,9 @@ patternProperties: ...@@ -116,7 +116,9 @@ patternProperties:
- ingenic,jz4740-watchdog - ingenic,jz4740-watchdog
- ingenic,jz4780-watchdog - ingenic,jz4780-watchdog
- items: - items:
- const: ingenic,jz4770-watchdog - enum:
- ingenic,jz4770-watchdog
- ingenic,jz4725b-watchdog
- const: ingenic,jz4740-watchdog - const: ingenic,jz4740-watchdog
reg: reg:
...@@ -142,6 +144,7 @@ patternProperties: ...@@ -142,6 +144,7 @@ patternProperties:
oneOf: oneOf:
- enum: - enum:
- ingenic,jz4740-pwm - ingenic,jz4740-pwm
- ingenic,jz4725b-pwm
- items: - items:
- enum: - enum:
- ingenic,jz4770-pwm - ingenic,jz4770-pwm
......
...@@ -1179,6 +1179,8 @@ patternProperties: ...@@ -1179,6 +1179,8 @@ patternProperties:
description: Shenzhen Xunlong Software CO.,Limited description: Shenzhen Xunlong Software CO.,Limited
"^xylon,.*": "^xylon,.*":
description: Xylon description: Xylon
"^ylm,.*":
description: Shenzhen Yangliming Electronic Technology Co., Ltd.
"^yna,.*": "^yna,.*":
description: YSH & ATIL description: YSH & ATIL
"^yones-toptech,.*": "^yones-toptech,.*":
......
...@@ -9509,9 +9509,11 @@ F: arch/arm64/kvm/ ...@@ -9509,9 +9509,11 @@ F: arch/arm64/kvm/
F: include/kvm/arm_* F: include/kvm/arm_*
KERNEL VIRTUAL MACHINE FOR MIPS (KVM/mips) KERNEL VIRTUAL MACHINE FOR MIPS (KVM/mips)
M: Huacai Chen <chenhc@lemote.com>
M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
L: linux-mips@vger.kernel.org L: linux-mips@vger.kernel.org
L: kvm@vger.kernel.org L: kvm@vger.kernel.org
S: Orphan S: Maintained
F: arch/mips/include/asm/kvm* F: arch/mips/include/asm/kvm*
F: arch/mips/include/uapi/asm/kvm* F: arch/mips/include/uapi/asm/kvm*
F: arch/mips/kvm/ F: arch/mips/kvm/
...@@ -11516,6 +11518,17 @@ F: arch/mips/configs/generic/board-boston.config ...@@ -11516,6 +11518,17 @@ F: arch/mips/configs/generic/board-boston.config
F: drivers/clk/imgtec/clk-boston.c F: drivers/clk/imgtec/clk-boston.c
F: include/dt-bindings/clock/boston-clock.h F: include/dt-bindings/clock/boston-clock.h
MIPS CORE DRIVERS
M: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
M: Serge Semin <fancer.lancer@gmail.com>
L: linux-mips@vger.kernel.org
S: Supported
F: drivers/bus/mips_cdmm.c
F: drivers/clocksource/mips-gic-timer.c
F: drivers/cpuidle/cpuidle-cps.c
F: drivers/irqchip/irq-mips-cpu.c
F: drivers/irqchip/irq-mips-gic.c
MIPS GENERIC PLATFORM MIPS GENERIC PLATFORM
M: Paul Burton <paulburton@kernel.org> M: Paul Burton <paulburton@kernel.org>
L: linux-mips@vger.kernel.org L: linux-mips@vger.kernel.org
......
...@@ -20,7 +20,6 @@ platform-$(CONFIG_MACH_LOONGSON32) += loongson32/ ...@@ -20,7 +20,6 @@ platform-$(CONFIG_MACH_LOONGSON32) += loongson32/
platform-$(CONFIG_MACH_LOONGSON64) += loongson64/ platform-$(CONFIG_MACH_LOONGSON64) += loongson64/
platform-$(CONFIG_MIPS_MALTA) += mti-malta/ platform-$(CONFIG_MIPS_MALTA) += mti-malta/
platform-$(CONFIG_NLM_COMMON) += netlogic/ platform-$(CONFIG_NLM_COMMON) += netlogic/
platform-$(CONFIG_MIPS_PARAVIRT) += paravirt/
platform-$(CONFIG_PIC32MZDA) += pic32/ platform-$(CONFIG_PIC32MZDA) += pic32/
platform-$(CONFIG_MACH_PISTACHIO) += pistachio/ platform-$(CONFIG_MACH_PISTACHIO) += pistachio/
platform-$(CONFIG_SOC_PNX833X) += pnx833x/ platform-$(CONFIG_SOC_PNX833X) += pnx833x/
......
...@@ -478,6 +478,7 @@ config MACH_LOONGSON64 ...@@ -478,6 +478,7 @@ config MACH_LOONGSON64
select COMMON_CLK select COMMON_CLK
select USE_OF select USE_OF
select BUILTIN_DTB select BUILTIN_DTB
select PCI_HOST_GENERIC
help help
This enables the support of Loongson-2/3 family of machines. This enables the support of Loongson-2/3 family of machines.
...@@ -678,6 +679,7 @@ config SGI_IP27 ...@@ -678,6 +679,7 @@ config SGI_IP27
select SYS_SUPPORTS_NUMA select SYS_SUPPORTS_NUMA
select SYS_SUPPORTS_SMP select SYS_SUPPORTS_SMP
select MIPS_L1_CACHE_SHIFT_7 select MIPS_L1_CACHE_SHIFT_7
select NUMA
help help
This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
workstations. To compile a Linux kernel that runs on these, say Y workstations. To compile a Linux kernel that runs on these, say Y
...@@ -1013,24 +1015,6 @@ config NLM_XLP_BOARD ...@@ -1013,24 +1015,6 @@ config NLM_XLP_BOARD
This board is based on Netlogic XLP Processor. This board is based on Netlogic XLP Processor.
Say Y here if you have a XLP based board. Say Y here if you have a XLP based board.
config MIPS_PARAVIRT
bool "Para-Virtualized guest system"
select CEVT_R4K
select CSRC_R4K
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_SMP
select NR_CPUS_DEFAULT_4
select SYS_HAS_EARLY_PRINTK
select SYS_HAS_CPU_MIPS32_R2
select SYS_HAS_CPU_MIPS64_R2
select SYS_HAS_CPU_CAVIUM_OCTEON
select HAVE_PCI
select SWAP_IO_SPACE
help
This option supports guest running under ????
endchoice endchoice
source "arch/mips/alchemy/Kconfig" source "arch/mips/alchemy/Kconfig"
...@@ -1055,7 +1039,6 @@ source "arch/mips/loongson2ef/Kconfig" ...@@ -1055,7 +1039,6 @@ source "arch/mips/loongson2ef/Kconfig"
source "arch/mips/loongson32/Kconfig" source "arch/mips/loongson32/Kconfig"
source "arch/mips/loongson64/Kconfig" source "arch/mips/loongson64/Kconfig"
source "arch/mips/netlogic/Kconfig" source "arch/mips/netlogic/Kconfig"
source "arch/mips/paravirt/Kconfig"
endmenu endmenu
...@@ -1169,9 +1152,6 @@ config MIPS_MSC ...@@ -1169,9 +1152,6 @@ config MIPS_MSC
config SYNC_R4K config SYNC_R4K
bool bool
config MIPS_MACHINE
def_bool n
config NO_IOPORT_MAP config NO_IOPORT_MAP
def_bool n def_bool n
...@@ -2825,7 +2805,7 @@ config SMP ...@@ -2825,7 +2805,7 @@ config SMP
Y to "Enhanced Real Time Clock Support", below. Y to "Enhanced Real Time Clock Support", below.
See also the SMP-HOWTO available at See also the SMP-HOWTO available at
<http://www.tldp.org/docs.html#howto>. <https://www.tldp.org/docs.html#howto>.
If you don't know what to do here, say N. If you don't know what to do here, say N.
......
...@@ -23,7 +23,6 @@ ...@@ -23,7 +23,6 @@
#include <asm/idle.h> #include <asm/idle.h>
#include <asm/time.h> /* for mips_hpt_frequency */ #include <asm/time.h> /* for mips_hpt_frequency */
#include <asm/reboot.h> /* for _machine_{restart,halt} */ #include <asm/reboot.h> /* for _machine_{restart,halt} */
#include <asm/mips_machine.h>
#include <asm/prom.h> #include <asm/prom.h>
#include <asm/fw/fw.h> #include <asm/fw/fw.h>
......
...@@ -67,7 +67,7 @@ static struct board_info __initdata board_cvg834g = { ...@@ -67,7 +67,7 @@ static struct board_info __initdata board_cvg834g = {
.ephy_reset_gpio = 36, .ephy_reset_gpio = 36,
.ephy_reset_gpio_flags = GPIOF_INIT_HIGH, .ephy_reset_gpio_flags = GPIOF_INIT_HIGH,
}; };
#endif #endif /* CONFIG_BCM63XX_CPU_3368 */
/* /*
* known 6328 boards * known 6328 boards
...@@ -115,7 +115,7 @@ static struct board_info __initdata board_96328avng = { ...@@ -115,7 +115,7 @@ static struct board_info __initdata board_96328avng = {
}, },
}, },
}; };
#endif #endif /* CONFIG_BCM63XX_CPU_6328 */
/* /*
* known 6338 boards * known 6338 boards
...@@ -204,7 +204,7 @@ static struct board_info __initdata board_96338w = { ...@@ -204,7 +204,7 @@ static struct board_info __initdata board_96338w = {
}, },
}, },
}; };
#endif #endif /* CONFIG_BCM63XX_CPU_6338 */
/* /*
* known 6345 boards * known 6345 boards
...@@ -216,7 +216,7 @@ static struct board_info __initdata board_96345gw2 = { ...@@ -216,7 +216,7 @@ static struct board_info __initdata board_96345gw2 = {
.has_uart0 = 1, .has_uart0 = 1,
}; };
#endif #endif /* CONFIG_BCM63XX_CPU_6345 */
/* /*
* known 6348 boards * known 6348 boards
...@@ -464,7 +464,6 @@ static struct board_info __initdata board_rta1025w_16 = { ...@@ -464,7 +464,6 @@ static struct board_info __initdata board_rta1025w_16 = {
}, },
}; };
static struct board_info __initdata board_DV201AMR = { static struct board_info __initdata board_DV201AMR = {
.name = "DV201AMR", .name = "DV201AMR",
.expected_cpu_id = 0x6348, .expected_cpu_id = 0x6348,
...@@ -505,7 +504,7 @@ static struct board_info __initdata board_96348gw_a = { ...@@ -505,7 +504,7 @@ static struct board_info __initdata board_96348gw_a = {
.has_ohci0 = 1, .has_ohci0 = 1,
}; };
#endif #endif /* CONFIG_BCM63XX_CPU_6348 */
/* /*
* known 6358 boards * known 6358 boards
...@@ -530,7 +529,6 @@ static struct board_info __initdata board_96358vw = { ...@@ -530,7 +529,6 @@ static struct board_info __initdata board_96358vw = {
.force_duplex_full = 1, .force_duplex_full = 1,
}, },
.has_ohci0 = 1, .has_ohci0 = 1,
.has_pccard = 1, .has_pccard = 1,
.has_ehci0 = 1, .has_ehci0 = 1,
...@@ -654,7 +652,7 @@ static struct board_info __initdata board_DWVS0 = { ...@@ -654,7 +652,7 @@ static struct board_info __initdata board_DWVS0 = {
.has_ohci0 = 1, .has_ohci0 = 1,
}; };
#endif #endif /* CONFIG_BCM63XX_CPU_6358 */
/* /*
* all boards * all boards
...@@ -662,17 +660,17 @@ static struct board_info __initdata board_DWVS0 = { ...@@ -662,17 +660,17 @@ static struct board_info __initdata board_DWVS0 = {
static const struct board_info __initconst *bcm963xx_boards[] = { static const struct board_info __initconst *bcm963xx_boards[] = {
#ifdef CONFIG_BCM63XX_CPU_3368 #ifdef CONFIG_BCM63XX_CPU_3368
&board_cvg834g, &board_cvg834g,
#endif #endif /* CONFIG_BCM63XX_CPU_3368 */
#ifdef CONFIG_BCM63XX_CPU_6328 #ifdef CONFIG_BCM63XX_CPU_6328
&board_96328avng, &board_96328avng,
#endif #endif /* CONFIG_BCM63XX_CPU_6328 */
#ifdef CONFIG_BCM63XX_CPU_6338 #ifdef CONFIG_BCM63XX_CPU_6338
&board_96338gw, &board_96338gw,
&board_96338w, &board_96338w,
#endif #endif /* CONFIG_BCM63XX_CPU_6338 */
#ifdef CONFIG_BCM63XX_CPU_6345 #ifdef CONFIG_BCM63XX_CPU_6345
&board_96345gw2, &board_96345gw2,
#endif #endif /* CONFIG_BCM63XX_CPU_6345 */
#ifdef CONFIG_BCM63XX_CPU_6348 #ifdef CONFIG_BCM63XX_CPU_6348
&board_96348r, &board_96348r,
&board_96348gw, &board_96348gw,
...@@ -682,14 +680,13 @@ static const struct board_info __initconst *bcm963xx_boards[] = { ...@@ -682,14 +680,13 @@ static const struct board_info __initconst *bcm963xx_boards[] = {
&board_DV201AMR, &board_DV201AMR,
&board_96348gw_a, &board_96348gw_a,
&board_rta1025w_16, &board_rta1025w_16,
#endif #endif /* CONFIG_BCM63XX_CPU_6348 */
#ifdef CONFIG_BCM63XX_CPU_6358 #ifdef CONFIG_BCM63XX_CPU_6358
&board_96358vw, &board_96358vw,
&board_96358vw2, &board_96358vw2,
&board_AGPFS0, &board_AGPFS0,
&board_DWVS0, &board_DWVS0,
#endif #endif /* CONFIG_BCM63XX_CPU_6358 */
}; };
/* /*
...@@ -728,7 +725,7 @@ int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) ...@@ -728,7 +725,7 @@ int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)
return -EINVAL; return -EINVAL;
} }
} }
#endif #endif /* CONFIG_SSB_PCIHOST */
/* /*
* return board name for /proc/cpuinfo * return board name for /proc/cpuinfo
...@@ -763,11 +760,25 @@ void __init board_prom_init(void) ...@@ -763,11 +760,25 @@ void __init board_prom_init(void)
/* dump cfe version */ /* dump cfe version */
cfe = boot_addr + BCM963XX_CFE_VERSION_OFFSET; cfe = boot_addr + BCM963XX_CFE_VERSION_OFFSET;
if (!memcmp(cfe, "cfe-v", 5)) if (strstarts(cfe, "cfe-")) {
snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u", if(cfe[4] == 'v') {
cfe[5], cfe[6], cfe[7], cfe[8], cfe[9]); if(cfe[5] == 'd')
snprintf(cfe_version, 11, "%s",
(char *) &cfe[5]);
else if (cfe[10] > 0)
snprintf(cfe_version, sizeof(cfe_version),
"%u.%u.%u-%u.%u-%u", cfe[5], cfe[6],
cfe[7], cfe[8], cfe[9], cfe[10]);
else else
snprintf(cfe_version, sizeof(cfe_version),
"%u.%u.%u-%u.%u", cfe[5], cfe[6],
cfe[7], cfe[8], cfe[9]);
} else {
snprintf(cfe_version, 12, "%s", (char *) &cfe[4]);
}
} else {
strcpy(cfe_version, "unknown"); strcpy(cfe_version, "unknown");
}
pr_info("CFE version: %s\n", cfe_version); pr_info("CFE version: %s\n", cfe_version);
bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET); bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET);
...@@ -807,7 +818,7 @@ void __init board_prom_init(void) ...@@ -807,7 +818,7 @@ void __init board_prom_init(void)
if (BCMCPU_IS_6348()) if (BCMCPU_IS_6348())
val |= GPIO_MODE_6348_G2_PCI; val |= GPIO_MODE_6348_G2_PCI;
} }
#endif #endif /* CONFIG_PCI */
if (board.has_pccard) { if (board.has_pccard) {
if (BCMCPU_IS_6348()) if (BCMCPU_IS_6348())
...@@ -892,7 +903,7 @@ int __init board_register_devices(void) ...@@ -892,7 +903,7 @@ int __init board_register_devices(void)
&bcm63xx_get_fallback_sprom) < 0) &bcm63xx_get_fallback_sprom) < 0)
pr_err("failed to register fallback SPROM\n"); pr_err("failed to register fallback SPROM\n");
} }
#endif #endif /* CONFIG_SSB_PCIHOST */
bcm63xx_spi_register(); bcm63xx_spi_register();
......
# SPDX-License-Identifier: GPL-2.0 # SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_JZ4740_QI_LB60) += qi_lb60.dtb dtb-$(CONFIG_JZ4740_QI_LB60) += qi_lb60.dtb
dtb-$(CONFIG_JZ4740_RS90) += rs90.dtb
dtb-$(CONFIG_JZ4770_GCW0) += gcw0.dtb dtb-$(CONFIG_JZ4770_GCW0) += gcw0.dtb
dtb-$(CONFIG_JZ4780_CI20) += ci20.dtb dtb-$(CONFIG_JZ4780_CI20) += ci20.dtb
dtb-$(CONFIG_X1000_CU1000_NEO) += cu1000-neo.dtb dtb-$(CONFIG_X1000_CU1000_NEO) += cu1000-neo.dtb
dtb-$(CONFIG_X1830_CU1830_NEO) += cu1830-neo.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
...@@ -7,8 +7,8 @@ ...@@ -7,8 +7,8 @@
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
/ { / {
compatible = "yna,cu1000-neo", "ingenic,x1000"; compatible = "yna,cu1000-neo", "ingenic,x1000e";
model = "YSH & ATIL General Board CU Neo"; model = "YSH & ATIL General Board CU1000-Neo";
aliases { aliases {
serial2 = &uart2; serial2 = &uart2;
...@@ -23,20 +23,19 @@ memory { ...@@ -23,20 +23,19 @@ memory {
reg = <0x0 0x04000000>; reg = <0x0 0x04000000>;
}; };
leds {
compatible = "gpio-leds";
led-0 {
gpios = <&gpb 21 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
};
wlan_pwrseq: msc1-pwrseq { wlan_pwrseq: msc1-pwrseq {
compatible = "mmc-pwrseq-simple"; compatible = "mmc-pwrseq-simple";
clocks = <&lpoclk>;
clock-names = "ext_clock";
reset-gpios = <&gpc 17 GPIO_ACTIVE_LOW>; reset-gpios = <&gpc 17 GPIO_ACTIVE_LOW>;
post-power-on-delay-ms = <200>; post-power-on-delay-ms = <200>;
lpoclk: ap6212a {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
}; };
}; };
...@@ -53,6 +52,13 @@ &tcu { ...@@ -53,6 +52,13 @@ &tcu {
ingenic,pwm-channels-mask = <0xfa>; ingenic,pwm-channels-mask = <0xfa>;
}; };
&uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pins_uart2>;
};
&i2c0 { &i2c0 {
status = "okay"; status = "okay";
...@@ -61,43 +67,15 @@ &i2c0 { ...@@ -61,43 +67,15 @@ &i2c0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pins_i2c0>; pinctrl-0 = <&pins_i2c0>;
ads7830@48 { ads7830: adc@48 {
compatible = "ti,ads7830"; compatible = "ti,ads7830";
reg = <0x48>; reg = <0x48>;
}; };
}; };
&uart2 { &msc0 {
pinctrl-names = "default";
pinctrl-0 = <&pins_uart2>;
status = "okay";
};
&mac {
phy-mode = "rmii";
phy-handle = <&lan8720a>;
pinctrl-names = "default";
pinctrl-0 = <&pins_mac>;
snps,reset-gpio = <&gpc 23 GPIO_ACTIVE_LOW>; /* PC23 */
snps,reset-active-low;
snps,reset-delays-us = <0 10000 30000>;
status = "okay";
};
&mdio {
status = "okay"; status = "okay";
lan8720a: ethernet-phy@0 {
compatible = "ethernet-phy-id0007.c0f0", "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
&msc0 {
bus-width = <8>; bus-width = <8>;
max-frequency = <50000000>; max-frequency = <50000000>;
...@@ -105,26 +83,23 @@ &msc0 { ...@@ -105,26 +83,23 @@ &msc0 {
pinctrl-0 = <&pins_msc0>; pinctrl-0 = <&pins_msc0>;
non-removable; non-removable;
status = "okay";
}; };
&msc1 { &msc1 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>; bus-width = <4>;
max-frequency = <50000000>; max-frequency = <50000000>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pins_msc1>; pinctrl-0 = <&pins_msc1>;
#address-cells = <1>;
#size-cells = <0>;
non-removable; non-removable;
mmc-pwrseq = <&wlan_pwrseq>; mmc-pwrseq = <&wlan_pwrseq>;
status = "okay";
ap6212a: wifi@1 { ap6212a: wifi@1 {
compatible = "brcm,bcm4329-fmac"; compatible = "brcm,bcm4329-fmac";
reg = <1>; reg = <1>;
...@@ -137,23 +112,40 @@ ap6212a: wifi@1 { ...@@ -137,23 +112,40 @@ ap6212a: wifi@1 {
}; };
}; };
&pinctrl { &mac {
pins_i2c0: i2c0 { status = "okay";
function = "i2c0";
groups = "i2c0-data"; phy-mode = "rmii";
bias-disable; phy-handle = <&lan8720a>;
pinctrl-names = "default";
pinctrl-0 = <&pins_mac>;
snps,reset-gpio = <&gpc 23 GPIO_ACTIVE_LOW>; /* PC23 */
snps,reset-active-low;
snps,reset-delays-us = <0 10000 30000>;
};
&mdio {
status = "okay";
lan8720a: ethernet-phy@0 {
compatible = "ethernet-phy-id0007.c0f0", "ethernet-phy-ieee802.3-c22";
reg = <0>;
}; };
};
&pinctrl {
pins_uart2: uart2 { pins_uart2: uart2 {
function = "uart2"; function = "uart2";
groups = "uart2-data-d"; groups = "uart2-data-d";
bias-disable; bias-pull-up;
}; };
pins_mac: mac { pins_i2c0: i2c0 {
function = "mac"; function = "i2c0";
groups = "mac"; groups = "i2c0-data";
bias-disable; bias-pull-up;
}; };
pins_msc0: msc0 { pins_msc0: msc0 {
...@@ -167,4 +159,10 @@ pins_msc1: msc1 { ...@@ -167,4 +159,10 @@ pins_msc1: msc1 {
groups = "mmc1-1bit", "mmc1-4bit"; groups = "mmc1-1bit", "mmc1-4bit";
bias-disable; bias-disable;
}; };
pins_mac: mac {
function = "mac";
groups = "mac";
bias-disable;
};
}; };
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "x1830.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/ingenic,tcu.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "yna,cu1830-neo", "ingenic,x1830";
model = "YSH & ATIL General Board CU1830-Neo";
aliases {
serial1 = &uart1;
};
chosen {
stdout-path = "serial1:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x08000000>;
};
leds {
compatible = "gpio-leds";
led-0 {
gpios = <&gpc 17 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
};
wlan_pwrseq: msc1-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpc 13 GPIO_ACTIVE_LOW>;
post-power-on-delay-ms = <200>;
};
};
&exclk {
clock-frequency = <24000000>;
};
&tcu {
/* 1500 kHz for the system timer and clocksource */
assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
assigned-clock-rates = <1500000>, <1500000>;
/* Use channel #0 for the system timer channel #2 for the clocksource */
ingenic,pwm-channels-mask = <0xfa>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pins_uart1>;
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pins_i2c0>;
ads7830: adc@48 {
compatible = "ti,ads7830";
reg = <0x48>;
};
};
&msc0 {
status = "okay";
bus-width = <4>;
max-frequency = <50000000>;
pinctrl-names = "default";
pinctrl-0 = <&pins_msc0>;
non-removable;
};
&msc1 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
max-frequency = <50000000>;
pinctrl-names = "default";
pinctrl-0 = <&pins_msc1>;
non-removable;
mmc-pwrseq = <&wlan_pwrseq>;
ap6212a: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpc>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
interrupt-names = "host-wake";
brcm,drive-strength = <10>;
};
};
&mac {
status = "okay";
phy-mode = "rmii";
phy-handle = <&ip101gr>;
pinctrl-names = "default";
pinctrl-0 = <&pins_mac>;
snps,reset-gpio = <&gpb 28 GPIO_ACTIVE_LOW>; /* PB28 */
snps,reset-active-low;
snps,reset-delays-us = <0 10000 30000>;
};
&mdio {
status = "okay";
ip101gr: ethernet-phy@0 {
compatible = "ethernet-phy-id0243.0c54", "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
&pinctrl {
pins_uart1: uart1 {
function = "uart1";
groups = "uart1-data";
bias-pull-up;
};
pins_i2c0: i2c0 {
function = "i2c0";
groups = "i2c0-data";
bias-pull-up;
};
pins_msc0: msc0 {
function = "mmc0";
groups = "mmc0-1bit", "mmc0-4bit";
bias-disable;
};
pins_msc1: msc1 {
function = "mmc1";
groups = "mmc1-1bit", "mmc1-4bit";
bias-disable;
};
pins_mac: mac {
function = "mac";
groups = "mac";
bias-disable;
};
};
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/jz4725b-cgu.h>
#include <dt-bindings/clock/ingenic,tcu.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ingenic,jz4725b";
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
intc: interrupt-controller@10001000 {
compatible = "ingenic,jz4725b-intc", "ingenic,jz4740-intc";
reg = <0x10001000 0x14>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};
ext: ext {
compatible = "fixed-clock";
#clock-cells = <0>;
};
osc32k: osc32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
cgu: clock-controller@10000000 {
compatible = "ingenic,jz4725b-cgu";
reg = <0x10000000 0x100>;
clocks = <&ext>, <&osc32k>;
clock-names = "ext", "osc32k";
#clock-cells = <1>;
};
tcu: timer@10002000 {
compatible = "ingenic,jz4725b-tcu", "simple-mfd";
reg = <0x10002000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10002000 0x1000>;
#clock-cells = <1>;
clocks = <&cgu JZ4725B_CLK_RTC>,
<&cgu JZ4725B_CLK_EXT>,
<&cgu JZ4725B_CLK_PCLK>,
<&cgu JZ4725B_CLK_TCU>;
clock-names = "rtc", "ext", "pclk", "tcu";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <23>, <22>, <21>;
watchdog: watchdog@0 {
compatible = "ingenic,jz4725b-watchdog", "ingenic,jz4740-watchdog";
reg = <0x0 0xc>;
clocks = <&tcu TCU_CLK_WDT>;
clock-names = "wdt";
};
pwm: pwm@60 {
compatible = "ingenic,jz4725b-pwm";
reg = <0x60 0x40>;
#pwm-cells = <3>;
clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
<&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
<&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>;
clock-names = "timer0", "timer1", "timer2",
"timer3", "timer4", "timer5";
};
ost: timer@e0 {
compatible = "ingenic,jz4725b-ost";
reg = <0xe0 0x20>;
clocks = <&tcu TCU_CLK_OST>;
clock-names = "ost";
interrupts = <15>;
};
};
rtc_dev: rtc@10003000 {
compatible = "ingenic,jz4725b-rtc", "ingenic,jz4740-rtc";
reg = <0x10003000 0x40>;
interrupt-parent = <&intc>;
interrupts = <6>;
clocks = <&cgu JZ4725B_CLK_RTC>;
clock-names = "rtc";
};
pinctrl: pinctrl@10010000 {
compatible = "ingenic,jz4725b-pinctrl";
reg = <0x10010000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
gpa: gpio@0 {
compatible = "ingenic,jz4725b-gpio";
reg = <0>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <16>;
};
gpb: gpio@1 {
compatible = "ingenic,jz4725b-gpio";
reg = <1>;
gpio-controller;
gpio-ranges = <&pinctrl 0 32 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <15>;
};
gpc: gpio@2 {
compatible = "ingenic,jz4725b-gpio";
reg = <2>;
gpio-controller;
gpio-ranges = <&pinctrl 0 64 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <14>;
};
gpd: gpio@3 {
compatible = "ingenic,jz4725b-gpio";
reg = <3>;
gpio-controller;
gpio-ranges = <&pinctrl 0 96 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <13>;
};
};
aic: audio-controller@10020000 {
compatible = "ingenic,jz4725b-i2s", "ingenic,jz4740-i2s";
reg = <0x10020000 0x38>;
#sound-dai-cells = <0>;
clocks = <&cgu JZ4725B_CLK_AIC>,
<&cgu JZ4725B_CLK_I2S>,
<&cgu JZ4725B_CLK_EXT>,
<&cgu JZ4725B_CLK_PLL_HALF>;
clock-names = "aic", "i2s", "ext", "pll half";
interrupt-parent = <&intc>;
interrupts = <10>;
dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
dma-names = "rx", "tx";
};
codec: audio-codec@100200a4 {
compatible = "ingenic,jz4725b-codec";
reg = <0x100200a4 0x8>;
#sound-dai-cells = <0>;
clocks = <&cgu JZ4725B_CLK_AIC>;
clock-names = "aic";
};
mmc0: mmc@10021000 {
compatible = "ingenic,jz4725b-mmc";
reg = <0x10021000 0x1000>;
clocks = <&cgu JZ4725B_CLK_MMC0>;
clock-names = "mmc";
interrupt-parent = <&intc>;
interrupts = <25>;
dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
dma-names = "rx", "tx";
cap-sd-highspeed;
cap-mmc-highspeed;
cap-sdio-irq;
};
mmc1: mmc@10022000 {
compatible = "ingenic,jz4725b-mmc";
reg = <0x10022000 0x1000>;
clocks = <&cgu JZ4725B_CLK_MMC1>;
clock-names = "mmc";
interrupt-parent = <&intc>;
interrupts = <24>;
dmas = <&dmac 31 0xffffffff>, <&dmac 30 0xffffffff>;
dma-names = "rx", "tx";
cap-sd-highspeed;
cap-mmc-highspeed;
cap-sdio-irq;
};
uart: serial@10030000 {
compatible = "ingenic,jz4725b-uart", "ingenic,jz4740-uart";
reg = <0x10030000 0x100>;
interrupt-parent = <&intc>;
interrupts = <9>;
clocks = <&ext>, <&cgu JZ4725B_CLK_UART>;
clock-names = "baud", "module";
};
adc: adc@10070000 {
compatible = "ingenic,jz4725b-adc";
#io-channel-cells = <1>;
reg = <0x10070000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10070000 0x30>;
clocks = <&cgu JZ4725B_CLK_ADC>;
clock-names = "adc";
interrupt-parent = <&intc>;
interrupts = <18>;
};
nemc: memory-controller@13010000 {
compatible = "ingenic,jz4725b-nemc", "ingenic,jz4740-nemc";
reg = <0x13010000 0x10000>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <1 0 0x18000000 0x4000000>, <2 0 0x14000000 0x4000000>,
<3 0 0x0c000000 0x4000000>, <4 0 0x08000000 0x4000000>;
clocks = <&cgu JZ4725B_CLK_MCLK>;
};
dmac: dma-controller@13020000 {
compatible = "ingenic,jz4725b-dma";
reg = <0x13020000 0xd8>, <0x13020300 0x14>;
#dma-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <29>;
clocks = <&cgu JZ4725B_CLK_DMA>;
};
udc: usb@13040000 {
compatible = "ingenic,jz4725b-musb", "ingenic,jz4740-musb";
reg = <0x13040000 0x10000>;
interrupt-parent = <&intc>;
interrupts = <27>;
interrupt-names = "mc";
clocks = <&cgu JZ4725B_CLK_UDC>;
clock-names = "udc";
};
lcd: lcd-controller@13050000 {
compatible = "ingenic,jz4725b-lcd";
reg = <0x13050000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <31>;
clocks = <&cgu JZ4725B_CLK_LCD>;
clock-names = "lcd_pclk";
lcd_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
port@8 {
reg = <8>;
ipu_output: endpoint {
remote-endpoint = <&ipu_input>;
};
};
};
};
ipu: ipu@13080000 {
compatible = "ingenic,jz4725b-ipu";
reg = <0x13080000 0x64>;
interrupt-parent = <&intc>;
interrupts = <30>;
clocks = <&cgu JZ4725B_CLK_IPU>;
clock-names = "ipu";
port {
ipu_input: endpoint {
remote-endpoint = <&ipu_output>;
};
};
};
bch: ecc-controller@130d0000 {
compatible = "ingenic,jz4725b-bch";
reg = <0x130d0000 0x44>;
clocks = <&cgu JZ4725B_CLK_BCH>;
};
rom: memory@1fc00000 {
compatible = "mtd-rom";
probe-type = "map_rom";
reg = <0x1fc00000 0x2000>;
bank-width = <4>;
device-width = <1>;
};
};
...@@ -16,6 +16,12 @@ ...@@ -16,6 +16,12 @@
/ { / {
compatible = "qi,lb60", "ingenic,jz4740"; compatible = "qi,lb60", "ingenic,jz4740";
model = "Ben Nanonote";
memory {
device_type = "memory";
reg = <0x0 0x2000000>;
};
chosen { chosen {
stdout-path = &uart0; stdout-path = &uart0;
...@@ -69,7 +75,7 @@ sound { ...@@ -69,7 +75,7 @@ sound {
"Speaker", "OUTL", "Speaker", "OUTL",
"Speaker", "OUTR", "Speaker", "OUTR",
"INL", "LOUT", "INL", "LOUT",
"INL", "ROUT"; "INR", "ROUT";
simple-audio-card,aux-devs = <&amp>; simple-audio-card,aux-devs = <&amp>;
......
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "jz4725b.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/adc/ingenic,adc.h>
#include <dt-bindings/input/linux-event-codes.h>
/ {
compatible = "ylm,rs90", "ingenic,jz4725b";
model = "RS-90";
memory {
device_type = "memory";
reg = <0x0 0x2000000>;
};
vcc: regulator {
compatible = "regulator-fixed";
regulator-name = "vcc";
regulaor-min-microvolt = <3300000>;
regulaor-max-microvolt = <3300000>;
regulator-always-on;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 3 40000 0>;
brightness-levels = <0 16 32 48 64 80 112 144 192 255>;
default-brightness-level = <8>;
pinctrl-names = "default";
pinctrl-0 = <&pins_pwm3>;
power-supply = <&vcc>;
};
keys@0 {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
key@0 {
label = "D-pad up";
linux,code = <KEY_UP>;
gpios = <&gpc 10 GPIO_ACTIVE_LOW>;
};
key@1 {
label = "D-pad down";
linux,code = <KEY_DOWN>;
gpios = <&gpc 11 GPIO_ACTIVE_LOW>;
};
key@2 {
label = "D-pad left";
linux,code = <KEY_LEFT>;
gpios = <&gpb 31 GPIO_ACTIVE_LOW>;
};
key@3 {
label = "D-pad right";
linux,code = <KEY_RIGHT>;
gpios = <&gpd 21 GPIO_ACTIVE_LOW>;
};
key@4 {
label = "Button A";
linux,code = <KEY_LEFTCTRL>;
gpios = <&gpc 31 GPIO_ACTIVE_LOW>;
};
key@5 {
label = "Button B";
linux,code = <KEY_LEFTALT>;
gpios = <&gpc 30 GPIO_ACTIVE_LOW>;
};
key@6 {
label = "Right shoulder button";
linux,code = <KEY_BACKSPACE>;
gpios = <&gpc 12 GPIO_ACTIVE_LOW>;
debounce-interval = <10>;
};
key@7 {
label = "Start button";
linux,code = <KEY_ENTER>;
gpios = <&gpd 17 GPIO_ACTIVE_LOW>;
};
};
keys@1 {
compatible = "adc-keys";
io-channels = <&adc INGENIC_ADC_AUX>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1400000>;
poll-interval = <30>;
key@0 {
label = "Left shoulder button";
linux,code = <KEY_TAB>;
press-threshold-microvolt = <800000>;
};
key@1 {
label = "Select button";
linux,code = <KEY_ESC>;
press-threshold-microvolt = <1100000>;
};
};
amp: analog-amplifier {
compatible = "simple-audio-amplifier";
enable-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
VCC-supply = <&vcc>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "rs90-audio";
simple-audio-card,format = "i2s";
simple-audio-card,widgets =
"Speaker", "Speaker",
"Headphone", "Headphones";
simple-audio-card,routing =
"INL", "LHPOUT",
"INR", "RHPOUT",
"Headphones", "LHPOUT",
"Headphones", "RHPOUT",
"Speaker", "OUTL",
"Speaker", "OUTR";
simple-audio-card,pin-switches = "Speaker";
simple-audio-card,hp-det-gpio = <&gpd 16 GPIO_ACTIVE_LOW>;
simple-audio-card,aux-devs = <&amp>;
simple-audio-card,bitclock-master = <&dai_codec>;
simple-audio-card,frame-master = <&dai_codec>;
dai_cpu: simple-audio-card,cpu {
sound-dai = <&aic>;
};
dai_codec: simple-audio-card,codec {
sound-dai = <&codec>;
};
};
usb_phy: usb-phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
clocks = <&cgu JZ4725B_CLK_UDC_PHY>;
clock-names = "main_clk";
vcc-supply = <&vcc>;
};
panel {
compatible = "sharp,ls020b1dd01d";
backlight = <&backlight>;
power-supply = <&vcc>;
port {
panel_input: endpoint {
remote-endpoint = <&panel_output>;
};
};
};
};
&ext {
clock-frequency = <12000000>;
};
&rtc_dev {
system-power-controller;
};
&udc {
phys = <&usb_phy>;
};
&pinctrl {
pins_mmc1: mmc1 {
function = "mmc1";
groups = "mmc1-1bit";
};
pins_nemc: nemc {
function = "nand";
groups = "nand-cs1", "nand-cle-ale", "nand-fre-fwe";
};
pins_pwm3: pwm3 {
function = "pwm3";
groups = "pwm3";
bias-disable;
};
pins_lcd: lcd {
function = "lcd";
groups = "lcd-8bit", "lcd-16bit", "lcd-special";
};
};
&mmc0 {
status = "disabled";
};
&mmc1 {
bus-width = <1>;
max-frequency = <48000000>;
pinctrl-names = "default";
pinctrl-0 = <&pins_mmc1>;
cd-gpios = <&gpc 20 GPIO_ACTIVE_LOW>;
};
&uart {
/*
* The pins for RX/TX are used for the right shoulder button and
* backlight PWM.
*/
status = "disabled";
};
&nemc {
nandc: nand-controller@1 {
compatible = "ingenic,jz4725b-nand";
reg = <1 0 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
ecc-engine = <&bch>;
ingenic,nemc-tAS = <10>;
ingenic,nemc-tAH = <5>;
ingenic,nemc-tBP = <10>;
ingenic,nemc-tAW = <15>;
ingenic,nemc-tSTRV = <100>;
pinctrl-names = "default";
pinctrl-0 = <&pins_nemc>;
rb-gpios = <&gpc 27 GPIO_ACTIVE_HIGH>;
nand@1 {
reg = <1>;
nand-ecc-step-size = <512>;
nand-ecc-strength = <8>;
nand-ecc-mode = "hw";
nand-is-boot-medium;
nand-on-flash-bbt;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bootloader";
reg = <0x0 0x20000>;
};
partition@20000 {
label = "system";
reg = <0x20000 0x0>;
};
};
};
};
};
&cgu {
/* Use 32kHz oscillator as the parent of the RTC clock */
assigned-clocks = <&cgu JZ4725B_CLK_RTC>;
assigned-clock-parents = <&cgu JZ4725B_CLK_OSC32K>;
};
&tcu {
/*
* 750 kHz for the system timer and clocksource, and use RTC as the
* parent for the watchdog clock.
*/
assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, <&tcu TCU_CLK_WDT>;
assigned-clock-parents = <0>, <0>, <&cgu JZ4725B_CLK_RTC>;
assigned-clock-rates = <750000>, <750000>;
};
&lcd {
pinctrl-names = "default";
pinctrl-0 = <&pins_lcd>;
};
&lcd_ports {
port@0 {
reg = <0>;
panel_output: endpoint {
remote-endpoint = <&panel_input>;
};
};
};
...@@ -48,9 +48,7 @@ cgu: x1000-cgu@10000000 { ...@@ -48,9 +48,7 @@ cgu: x1000-cgu@10000000 {
}; };
tcu: timer@10002000 { tcu: timer@10002000 {
compatible = "ingenic,x1000-tcu", compatible = "ingenic,x1000-tcu", "simple-mfd";
"ingenic,jz4770-tcu",
"simple-mfd";
reg = <0x10002000 0x1000>; reg = <0x10002000 0x1000>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
...@@ -156,48 +154,6 @@ gpd: gpio@3 { ...@@ -156,48 +154,6 @@ gpd: gpio@3 {
}; };
}; };
i2c0: i2c-controller@10050000 {
compatible = "ingenic,x1000-i2c";
reg = <0x10050000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&intc>;
interrupts = <60>;
clocks = <&cgu X1000_CLK_I2C0>;
status = "disabled";
};
i2c1: i2c-controller@10051000 {
compatible = "ingenic,x1000-i2c";
reg = <0x10051000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&intc>;
interrupts = <59>;
clocks = <&cgu X1000_CLK_I2C1>;
status = "disabled";
};
i2c2: i2c-controller@10052000 {
compatible = "ingenic,x1000-i2c";
reg = <0x10052000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&intc>;
interrupts = <58>;
clocks = <&cgu X1000_CLK_I2C2>;
status = "disabled";
};
uart0: serial@10030000 { uart0: serial@10030000 {
compatible = "ingenic,x1000-uart"; compatible = "ingenic,x1000-uart";
reg = <0x10030000 0x100>; reg = <0x10030000 0x100>;
...@@ -237,37 +193,57 @@ uart2: serial@10032000 { ...@@ -237,37 +193,57 @@ uart2: serial@10032000 {
status = "disabled"; status = "disabled";
}; };
pdma: dma-controller@13420000 { i2c0: i2c-controller@10050000 {
compatible = "ingenic,x1000-dma"; compatible = "ingenic,x1000-i2c";
reg = <0x13420000 0x400>, <0x13421000 0x40>; reg = <0x10050000 0x1000>;
#dma-cells = <2>; #address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
interrupts = <10>; interrupts = <60>;
clocks = <&cgu X1000_CLK_PDMA>; clocks = <&cgu X1000_CLK_I2C0>;
status = "disabled";
}; };
mac: ethernet@134b0000 { i2c1: i2c-controller@10051000 {
compatible = "ingenic,x1000-mac", "snps,dwmac"; compatible = "ingenic,x1000-i2c";
reg = <0x134b0000 0x2000>; reg = <0x10051000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
interrupts = <55>; interrupts = <59>;
interrupt-names = "macirq";
clocks = <&cgu X1000_CLK_MAC>; clocks = <&cgu X1000_CLK_I2C1>;
clock-names = "stmmaceth";
status = "disabled"; status = "disabled";
};
mdio: mdio { i2c2: i2c-controller@10052000 {
compatible = "snps,dwmac-mdio"; compatible = "ingenic,x1000-i2c";
reg = <0x10052000 0x1000>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupt-parent = <&intc>;
interrupts = <58>;
clocks = <&cgu X1000_CLK_I2C2>;
status = "disabled"; status = "disabled";
}; };
pdma: dma-controller@13420000 {
compatible = "ingenic,x1000-dma";
reg = <0x13420000 0x400>, <0x13421000 0x40>;
#dma-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <10>;
clocks = <&cgu X1000_CLK_PDMA>;
}; };
msc0: mmc@13450000 { msc0: mmc@13450000 {
...@@ -311,4 +287,26 @@ msc1: mmc@13460000 { ...@@ -311,4 +287,26 @@ msc1: mmc@13460000 {
status = "disabled"; status = "disabled";
}; };
mac: ethernet@134b0000 {
compatible = "ingenic,x1000-mac", "snps,dwmac";
reg = <0x134b0000 0x2000>;
interrupt-parent = <&intc>;
interrupts = <55>;
interrupt-names = "macirq";
clocks = <&cgu X1000_CLK_MAC>;
clock-names = "stmmaceth";
status = "disabled";
mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
}; };
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/ingenic,tcu.h>
#include <dt-bindings/clock/x1830-cgu.h>
#include <dt-bindings/dma/x1830-dma.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ingenic,x1830";
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
intc: interrupt-controller@10001000 {
compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc";
reg = <0x10001000 0x50>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};
exclk: ext {
compatible = "fixed-clock";
#clock-cells = <0>;
};
rtclk: rtc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
cgu: x1830-cgu@10000000 {
compatible = "ingenic,x1830-cgu";
reg = <0x10000000 0x100>;
#clock-cells = <1>;
clocks = <&exclk>, <&rtclk>;
clock-names = "ext", "rtc";
};
tcu: timer@10002000 {
compatible = "ingenic,x1830-tcu", "ingenic,x1000-tcu", "simple-mfd";
reg = <0x10002000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10002000 0x1000>;
#clock-cells = <1>;
clocks = <&cgu X1830_CLK_RTCLK
&cgu X1830_CLK_EXCLK
&cgu X1830_CLK_PCLK>;
clock-names = "rtc", "ext", "pclk";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <27 26 25>;
wdt: watchdog@0 {
compatible = "ingenic,x1830-watchdog", "ingenic,jz4780-watchdog";
reg = <0x0 0x10>;
clocks = <&tcu TCU_CLK_WDT>;
clock-names = "wdt";
};
};
rtc: rtc@10003000 {
compatible = "ingenic,x1830-rtc", "ingenic,jz4780-rtc";
reg = <0x10003000 0x4c>;
interrupt-parent = <&intc>;
interrupts = <32>;
clocks = <&cgu X1830_CLK_RTCLK>;
clock-names = "rtc";
};
pinctrl: pin-controller@10010000 {
compatible = "ingenic,x1830-pinctrl";
reg = <0x10010000 0x800>;
#address-cells = <1>;
#size-cells = <0>;
gpa: gpio@0 {
compatible = "ingenic,x1830-gpio";
reg = <0>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <17>;
};
gpb: gpio@1 {
compatible = "ingenic,x1830-gpio";
reg = <1>;
gpio-controller;
gpio-ranges = <&pinctrl 0 32 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <16>;
};
gpc: gpio@2 {
compatible = "ingenic,x1830-gpio";
reg = <2>;
gpio-controller;
gpio-ranges = <&pinctrl 0 64 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <15>;
};
gpd: gpio@3 {
compatible = "ingenic,x1830-gpio";
reg = <3>;
gpio-controller;
gpio-ranges = <&pinctrl 0 96 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <14>;
};
};
uart0: serial@10030000 {
compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
reg = <0x10030000 0x100>;
interrupt-parent = <&intc>;
interrupts = <51>;
clocks = <&exclk>, <&cgu X1830_CLK_UART0>;
clock-names = "baud", "module";
status = "disabled";
};
uart1: serial@10031000 {
compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
reg = <0x10031000 0x100>;
interrupt-parent = <&intc>;
interrupts = <50>;
clocks = <&exclk>, <&cgu X1830_CLK_UART1>;
clock-names = "baud", "module";
status = "disabled";
};
i2c0: i2c-controller@10050000 {
compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
reg = <0x10050000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&intc>;
interrupts = <60>;
clocks = <&cgu X1830_CLK_SMB0>;
status = "disabled";
};
i2c1: i2c-controller@10051000 {
compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
reg = <0x10051000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&intc>;
interrupts = <59>;
clocks = <&cgu X1830_CLK_SMB1>;
status = "disabled";
};
i2c2: i2c-controller@10052000 {
compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
reg = <0x10052000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&intc>;
interrupts = <58>;
clocks = <&cgu X1830_CLK_SMB2>;
status = "disabled";
};
pdma: dma-controller@13420000 {
compatible = "ingenic,x1830-dma";
reg = <0x13420000 0x400
0x13421000 0x40>;
#dma-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <10>;
clocks = <&cgu X1830_CLK_PDMA>;
};
msc0: mmc@13450000 {
compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
reg = <0x13450000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <37>;
clocks = <&cgu X1830_CLK_MSC0>;
clock-names = "mmc";
cap-sd-highspeed;
cap-mmc-highspeed;
cap-sdio-irq;
dmas = <&pdma X1830_DMA_MSC0_RX 0xffffffff>,
<&pdma X1830_DMA_MSC0_TX 0xffffffff>;
dma-names = "rx", "tx";
status = "disabled";
};
msc1: mmc@13460000 {
compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
reg = <0x13460000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <36>;
clocks = <&cgu X1830_CLK_MSC1>;
clock-names = "mmc";
cap-sd-highspeed;
cap-mmc-highspeed;
cap-sdio-irq;
dmas = <&pdma X1830_DMA_MSC1_RX 0xffffffff>,
<&pdma X1830_DMA_MSC1_TX 0xffffffff>;
dma-names = "rx", "tx";
status = "disabled";
};
mac: ethernet@134b0000 {
compatible = "ingenic,x1830-mac", "snps,dwmac";
reg = <0x134b0000 0x2000>;
interrupt-parent = <&intc>;
interrupts = <55>;
interrupt-names = "macirq";
clocks = <&cgu X1830_CLK_MAC>;
clock-names = "stmmaceth";
status = "disabled";
mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
};
# SPDX_License_Identifier: GPL_2.0 # SPDX_License_Identifier: GPL_2.0
dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_rs780e.dtb loongson3_8core_rs780e.dtb dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_ls7a.dtb
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_rs780e.dtb
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_8core_rs780e.dtb
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64g_4core_ls7a.dtb
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64v_4core_virtio.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "loongson64c-package.dtsi"
#include "ls7a-pch.dtsi"
/ {
compatible = "loongson,loongson64c-4core-ls7a";
};
&package0 {
htvec: interrupt-controller@efdfb000080 {
compatible = "loongson,htvec-1.0";
reg = <0xefd 0xfb000080 0x40>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&liointc>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
<25 IRQ_TYPE_LEVEL_HIGH>,
<26 IRQ_TYPE_LEVEL_HIGH>,
<27 IRQ_TYPE_LEVEL_HIGH>;
};
};
&pch {
msi: msi-controller@2ff00000 {
compatible = "loongson,pch-msi-1.0";
reg = <0 0x2ff00000 0 0x8>;
interrupt-controller;
msi-controller;
loongson,msi-base-vec = <64>;
loongson,msi-num-vecs = <64>;
interrupt-parent = <&htvec>;
};
};
...@@ -2,11 +2,11 @@ ...@@ -2,11 +2,11 @@
/dts-v1/; /dts-v1/;
#include "loongson3-package.dtsi" #include "loongson64c-package.dtsi"
#include "rs780e-pch.dtsi" #include "rs780e-pch.dtsi"
/ { / {
compatible = "loongson,loongson3-4core-rs780e"; compatible = "loongson,loongson64c-4core-rs780e";
}; };
&package0 { &package0 {
......
...@@ -2,11 +2,11 @@ ...@@ -2,11 +2,11 @@
/dts-v1/; /dts-v1/;
#include "loongson3-package.dtsi" #include "loongson64c-package.dtsi"
#include "rs780e-pch.dtsi" #include "rs780e-pch.dtsi"
/ { / {
compatible = "loongson,loongson3-8core-rs780e"; compatible = "loongson,loongson64c-8core-rs780e";
}; };
&package0 { &package0 {
......
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
package0: bus@1fe00000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
0 0x3ff00000 0 0x3ff00000 0x100000
0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
liointc: interrupt-controller@3ff01400 {
compatible = "loongson,liointc-1.0";
reg = <0 0x3ff01400 0x64>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&cpuintc>;
interrupts = <2>, <3>;
interrupt-names = "int0", "int1";
loongson,parent_int_map = <0x00ffffff>, /* int0 */
<0xff000000>, /* int1 */
<0x00000000>, /* int2 */
<0x00000000>; /* int3 */
};
cpu_uart0: serial@1fe001e0 {
compatible = "ns16550a";
reg = <0 0x1fe00100 0x10>;
clock-frequency = <100000000>;
interrupt-parent = <&liointc>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
no-loopback-test;
};
cpu_uart1: serial@1fe001e8 {
status = "disabled";
compatible = "ns16550a";
reg = <0 0x1fe00110 0x10>;
clock-frequency = <100000000>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc>;
no-loopback-test;
};
};
};
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "loongson64g-package.dtsi"
#include "ls7a-pch.dtsi"
/ {
compatible = "loongson,loongson64g-4core-ls7a";
};
&package0 {
htvec: interrupt-controller@efdfb000080 {
compatible = "loongson,htvec-1.0";
reg = <0xefd 0xfb000080 0x40>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&liointc>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
<25 IRQ_TYPE_LEVEL_HIGH>,
<26 IRQ_TYPE_LEVEL_HIGH>,
<27 IRQ_TYPE_LEVEL_HIGH>,
<28 IRQ_TYPE_LEVEL_HIGH>,
<29 IRQ_TYPE_LEVEL_HIGH>,
<30 IRQ_TYPE_LEVEL_HIGH>,
<31 IRQ_TYPE_LEVEL_HIGH>;
};
};
&pch {
msi: msi-controller@2ff00000 {
compatible = "loongson,pch-msi-1.0";
reg = <0 0x2ff00000 0 0x8>;
interrupt-controller;
msi-controller;
loongson,msi-base-vec = <64>;
loongson,msi-num-vecs = <192>;
interrupt-parent = <&htvec>;
};
};
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/interrupt-controller/irq.h>
/dts-v1/;
/ {
compatible = "loongson,loongson64v-4core-virtio";
#address-cells = <2>;
#size-cells = <2>;
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
package0: bus@1fe00000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
0 0x3ff00000 0 0x3ff00000 0x100000
0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
liointc: interrupt-controller@3ff01400 {
compatible = "loongson,liointc-1.0";
reg = <0 0x3ff01400 0x64>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&cpuintc>;
interrupts = <2>, <3>;
interrupt-names = "int0", "int1";
loongson,parent_int_map = <0x00000001>, /* int0 */
<0xfffffffe>, /* int1 */
<0x00000000>, /* int2 */
<0x00000000>; /* int3 */
};
cpu_uart0: serial@1fe001e0 {
compatible = "ns16550a";
reg = <0 0x1fe001e0 0x8>;
clock-frequency = <33000000>;
interrupt-parent = <&liointc>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
no-loopback-test;
};
};
bus@10000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
0 0x40000000 0 0x40000000 0 0x40000000>; /* PCI MEM */
rtc0: rtc@10081000 {
compatible = "google,goldfish-rtc";
reg = <0 0x10081000 0 0x1000>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc>;
};
pci@1a000000 {
compatible = "pci-host-ecam-generic";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
bus-range = <0x0 0x1f>;
reg = <0 0x1a000000 0 0x02000000>;
ranges = <0x01000000 0x0 0x00004000 0x0 0x18004000 0x0 0x0000c000>,
<0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
interrupt-map = <
0x0000 0x0 0x0 0x1 &liointc 0x2 IRQ_TYPE_LEVEL_HIGH
0x0800 0x0 0x0 0x1 &liointc 0x3 IRQ_TYPE_LEVEL_HIGH
0x1000 0x0 0x0 0x1 &liointc 0x4 IRQ_TYPE_LEVEL_HIGH
0x1800 0x0 0x0 0x1 &liointc 0x5 IRQ_TYPE_LEVEL_HIGH
>;
interrupt-map-mask = <0x1800 0x0 0x0 0x7>;
};
isa {
compatible = "isa";
#address-cells = <2>;
#size-cells = <1>;
ranges = <1 0 0 0x18000000 0x4000>;
};
};
hypervisor {
compatible = "linux,kvm";
};
};
// SPDX-License-Identifier: GPL-2.0
/ {
pch: bus@10000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
0 0x20000000 0 0x20000000 0 0x10000000
0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */
0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>;
pic: interrupt-controller@10000000 {
compatible = "loongson,pch-pic-1.0";
reg = <0 0x10000000 0 0x400>;
interrupt-controller;
interrupt-parent = <&htvec>;
loongson,pic-base-vec = <0>;
#interrupt-cells = <2>;
};
pci@1a000000 {
compatible = "loongson,ls7a-pci";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <2>;
msi-parent = <&msi>;
reg = <0 0x1a000000 0 0x02000000>,
<0xefe 0x00000000 0 0x20000000>;
ranges = <0x01000000 0x0 0x00020000 0x0 0x18020000 0x0 0x00020000>,
<0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
ohci@4,0 {
compatible = "pci0014,7a24.0",
"pci0014,7a24",
"pciclass0c0310",
"pciclass0c03";
reg = <0x2000 0x0 0x0 0x0 0x0>;
interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
};
ehci@4,1 {
compatible = "pci0014,7a14.0",
"pci0014,7a14",
"pciclass0c0320",
"pciclass0c03";
reg = <0x2100 0x0 0x0 0x0 0x0>;
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
};
ohci@5,0 {
compatible = "pci0014,7a24.0",
"pci0014,7a24",
"pciclass0c0310",
"pciclass0c03";
reg = <0x2800 0x0 0x0 0x0 0x0>;
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
};
ehci@5,1 {
compatible = "pci0014,7a14.0",
"pci0014,7a14",
"pciclass0c0320",
"pciclass0c03";
reg = <0x2900 0x0 0x0 0x0 0x0>;
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
};
sata@8,0 {
compatible = "pci0014,7a08.0",
"pci0014,7a08",
"pciclass010601",
"pciclass0106";
reg = <0x4000 0x0 0x0 0x0 0x0>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
};
sata@8,1 {
compatible = "pci0014,7a08.0",
"pci0014,7a08",
"pciclass010601",
"pciclass0106";
reg = <0x4100 0x0 0x0 0x0 0x0>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
};
sata@8,2 {
compatible = "pci0014,7a08.0",
"pci0014,7a08",
"pciclass010601",
"pciclass0106";
reg = <0x4200 0x0 0x0 0x0 0x0>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
};
gpu@6,0 {
compatible = "pci0014,7a15.0",
"pci0014,7a15",
"pciclass030200",
"pciclass0302";
reg = <0x3000 0x0 0x0 0x0 0x0>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
};
dc@6,1 {
compatible = "pci0014,7a06.0",
"pci0014,7a06",
"pciclass030000",
"pciclass0300";
reg = <0x3100 0x0 0x0 0x0 0x0>;
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
};
hda@7,0 {
compatible = "pci0014,7a07.0",
"pci0014,7a07",
"pciclass040300",
"pciclass0403";
reg = <0x3800 0x0 0x0 0x0 0x0>;
interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
};
gmac@3,0 {
compatible = "pci0014,7a03.0",
"pci0014,7a03",
"pciclass020000",
"pciclass0200";
reg = <0x1800 0x0 0x0 0x0 0x0>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
<13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_lpi";
interrupt-parent = <&pic>;
phy-mode = "rgmii";
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
gmac@3,1 {
compatible = "pci0014,7a03.0",
"pci0014,7a03",
"pciclass020000",
"pciclass0200";
reg = <0x1900 0x0 0x0 0x0 0x0>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
<15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_lpi";
interrupt-parent = <&pic>;
phy-mode = "rgmii";
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy1: ethernet-phy@1 {
reg = <0>;
};
};
};
pci_bridge@9,0 {
compatible = "pci0014,7a19.1",
"pci0014,7a19",
"pciclass060400",
"pciclass0604";
reg = <0x4800 0x0 0x0 0x0 0x0>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
};
pci_bridge@a,0 {
compatible = "pci0014,7a09.1",
"pci0014,7a09",
"pciclass060400",
"pciclass0604";
reg = <0x5000 0x0 0x0 0x0 0x0>;
interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
};
pci_bridge@b,0 {
compatible = "pci0014,7a09.1",
"pci0014,7a09",
"pciclass060400",
"pciclass0604";
reg = <0x5800 0x0 0x0 0x0 0x0>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
};
pci_bridge@c,0 {
compatible = "pci0014,7a09.1",
"pci0014,7a09",
"pciclass060400",
"pciclass0604";
reg = <0x6000 0x0 0x0 0x0 0x0>;
interrupts = <35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
};
pci_bridge@d,0 {
compatible = "pci0014,7a19.1",
"pci0014,7a19",
"pciclass060400",
"pciclass0604";
reg = <0x6800 0x0 0x0 0x0 0x0>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
};
pci_bridge@e,0 {
compatible = "pci0014,7a09.1",
"pci0014,7a09",
"pciclass060400",
"pciclass0604";
reg = <0x7000 0x0 0x0 0x0 0x0>;
interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
};
pci_bridge@f,0 {
compatible = "pci0014,7a29.1",
"pci0014,7a29",
"pciclass060400",
"pciclass0604";
reg = <0x7800 0x0 0x0 0x0 0x0>;
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
};
pci_bridge@10,0 {
compatible = "pci0014,7a19.1",
"pci0014,7a19",
"pciclass060400",
"pciclass0604";
reg = <0x8000 0x0 0x0 0x0 0x0>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>;
};
pci_bridge@11,0 {
compatible = "pci0014,7a29.1",
"pci0014,7a29",
"pciclass060400",
"pciclass0604";
reg = <0x8800 0x0 0x0 0x0 0x0>;
interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>;
};
pci_bridge@12,0 {
compatible = "pci0014,7a19.1",
"pci0014,7a19",
"pciclass060400",
"pciclass0604";
reg = <0x9000 0x0 0x0 0x0 0x0>;
interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &pic 43 IRQ_TYPE_LEVEL_HIGH>;
};
pci_bridge@13,0 {
compatible = "pci0014,7a29.1",
"pci0014,7a29",
"pciclass060400",
"pciclass0604";
reg = <0x9800 0x0 0x0 0x0 0x0>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &pic 38 IRQ_TYPE_LEVEL_HIGH>;
};
pci_bridge@14,0 {
compatible = "pci0014,7a19.1",
"pci0014,7a19",
"pciclass060400",
"pciclass0604";
reg = <0xa000 0x0 0x0 0x0 0x0>;
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pic>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>;
};
};
isa {
compatible = "isa";
#address-cells = <2>;
#size-cells = <1>;
ranges = <1 0 0 0x18000000 0x20000>;
};
};
};
...@@ -17,7 +17,7 @@ pci@1a000000 { ...@@ -17,7 +17,7 @@ pci@1a000000 {
reg = <0 0x1a000000 0 0x02000000>; reg = <0 0x1a000000 0 0x02000000>;
ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x00004000>, ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x0000c000>,
<0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>; <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
}; };
...@@ -25,7 +25,7 @@ isa { ...@@ -25,7 +25,7 @@ isa {
compatible = "isa"; compatible = "isa";
#address-cells = <2>; #address-cells = <2>;
#size-cells = <1>; #size-cells = <1>;
ranges = <1 0 0 0 0x1000>; ranges = <1 0 0 0x18000000 0x4000>;
rtc0: rtc@70 { rtc0: rtc@70 {
compatible = "motorola,mc146818"; compatible = "motorola,mc146818";
......
...@@ -518,6 +518,7 @@ static int __init dwc3_octeon_device_init(void) ...@@ -518,6 +518,7 @@ static int __init dwc3_octeon_device_init(void)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL) { if (res == NULL) {
put_device(&pdev->dev);
dev_err(&pdev->dev, "No memory resources\n"); dev_err(&pdev->dev, "No memory resources\n");
return -ENXIO; return -ENXIO;
} }
...@@ -529,8 +530,10 @@ static int __init dwc3_octeon_device_init(void) ...@@ -529,8 +530,10 @@ static int __init dwc3_octeon_device_init(void)
* know the difference. * know the difference.
*/ */
base = devm_ioremap_resource(&pdev->dev, res); base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base)) if (IS_ERR(base)) {
put_device(&pdev->dev);
return PTR_ERR(base); return PTR_ERR(base);
}
mutex_lock(&dwc3_octeon_clocks_mutex); mutex_lock(&dwc3_octeon_clocks_mutex);
dwc3_octeon_clocks_start(&pdev->dev, (u64)base); dwc3_octeon_clocks_start(&pdev->dev, (u64)base);
......
...@@ -128,6 +128,7 @@ CONFIG_DMA_JZ4780=y ...@@ -128,6 +128,7 @@ CONFIG_DMA_JZ4780=y
CONFIG_INGENIC_OST=y CONFIG_INGENIC_OST=y
# CONFIG_IOMMU_SUPPORT is not set # CONFIG_IOMMU_SUPPORT is not set
CONFIG_MEMORY=y CONFIG_MEMORY=y
CONFIG_JZ4780_NEMC=y
CONFIG_PWM=y CONFIG_PWM=y
CONFIG_PWM_JZ4740=m CONFIG_PWM_JZ4740=m
CONFIG_EXT4_FS=y CONFIG_EXT4_FS=y
......
...@@ -74,6 +74,10 @@ CONFIG_JZ4740_WDT=y ...@@ -74,6 +74,10 @@ CONFIG_JZ4740_WDT=y
# CONFIG_USB_SUPPORT is not set # CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y CONFIG_MMC=y
CONFIG_MMC_JZ4740=y CONFIG_MMC_JZ4740=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_RTC_CLASS=y CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_JZ4740=y CONFIG_RTC_DRV_JZ4740=y
CONFIG_DMADEVICES=y CONFIG_DMADEVICES=y
......
CONFIG_LOCALVERSION_AUTO=y
CONFIG_KERNEL_GZIP=y
CONFIG_SYSVIPC=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CGROUPS=y
CONFIG_MEMCG=y
CONFIG_MEMCG_KMEM=y
CONFIG_CGROUP_SCHED=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_NAMESPACES=y
CONFIG_USER_NS=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
CONFIG_MACH_INGENIC=y
CONFIG_X1830_CU1830_NEO=y
CONFIG_HIGHMEM=y
CONFIG_HZ_100=y
# CONFIG_SECCOMP is not set
# CONFIG_SUSPEND is not set
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_COMPACTION is not set
CONFIG_CMA=y
CONFIG_CMA_AREAS=7
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_CFG80211=y
CONFIG_UEVENT_HELPER=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
# CONFIG_FW_LOADER is not set
# CONFIG_ALLOW_DEV_COREDUMP is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=y
CONFIG_BLK_DEV_DM=y
CONFIG_NETDEVICES=y
CONFIG_STMMAC_ETH=y
CONFIG_ICPLUS_PHY=y
CONFIG_BRCMFMAC=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_LEGACY_PTY_COUNT=2
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_SERIAL_8250_INGENIC=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_JZ4780=y
CONFIG_GPIO_SYSFS=y
CONFIG_SENSORS_ADS7828=y
CONFIG_WATCHDOG=y
CONFIG_JZ4740_WDT=y
# CONFIG_LCD_CLASS_DEVICE is not set
# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_JZ4740=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_JZ4740=y
CONFIG_DMADEVICES=y
CONFIG_DMA_JZ4780=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_EXT4_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_AUTOFS_FS=y
CONFIG_PROC_KCORE=y
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=y
CONFIG_NFS_FS=y
CONFIG_NLS=y
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_CODEPAGE_950=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_PRINTK_TIME=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
CONFIG_CONSOLE_LOGLEVEL_QUIET=15
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
CONFIG_DEBUG_INFO=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_TIMEOUT=10
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_STACKTRACE=y
# CONFIG_FTRACE is not set
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="earlycon clk_ignore_unused"
...@@ -15,7 +15,13 @@ CONFIG_TASK_IO_ACCOUNTING=y ...@@ -15,7 +15,13 @@ CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_MEMCG=y CONFIG_MEMCG=y
CONFIG_MEMCG_SWAP=y CONFIG_MEMCG_SWAP=y
CONFIG_BLK_CGROUP=y CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CPUSETS=y CONFIG_CPUSETS=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_NAMESPACES=y
CONFIG_USER_NS=y
CONFIG_SCHED_AUTOGROUP=y CONFIG_SCHED_AUTOGROUP=y
CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED=y
CONFIG_RELAY=y CONFIG_RELAY=y
...@@ -23,16 +29,16 @@ CONFIG_BLK_DEV_INITRD=y ...@@ -23,16 +29,16 @@ CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y CONFIG_PERF_EVENTS=y
CONFIG_MACH_LOONGSON64=y CONFIG_MACH_LOONGSON64=y
CONFIG_CPU_HAS_MSA=y
CONFIG_SMP=y CONFIG_SMP=y
CONFIG_NR_CPUS=16
CONFIG_HZ_256=y CONFIG_HZ_256=y
CONFIG_KEXEC=y CONFIG_KEXEC=y
CONFIG_PCIEPORTBUS=y
CONFIG_HOTPLUG_PCI_PCIE=y
# CONFIG_PCIEAER is not set
CONFIG_PCIEASPM_PERFORMANCE=y
CONFIG_HOTPLUG_PCI=y
CONFIG_MIPS32_O32=y CONFIG_MIPS32_O32=y
CONFIG_MIPS32_N32=y CONFIG_MIPS32_N32=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=m
CONFIG_KVM_MIPS_VZ=y
CONFIG_MODULES=y CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_UNLOAD=y
...@@ -56,11 +62,19 @@ CONFIG_IP_MULTIPLE_TABLES=y ...@@ -56,11 +62,19 @@ CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_NETFILTER=y CONFIG_NETFILTER=y
CONFIG_BRIDGE_NETFILTER=m
CONFIG_NETFILTER_NETLINK_LOG=m CONFIG_NETFILTER_NETLINK_LOG=m
CONFIG_NF_CONNTRACK=m
CONFIG_NF_CONNTRACK_SNMP=m
CONFIG_NF_TABLES=m
CONFIG_NFT_CT=m
CONFIG_NFT_NAT=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m
...@@ -74,28 +88,56 @@ CONFIG_NETFILTER_XT_MATCH_REALM=m ...@@ -74,28 +88,56 @@ CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_IP_SET=m
CONFIG_IP_VS=m CONFIG_IP_VS=m
CONFIG_NF_TABLES_IPV4=y
CONFIG_NF_TABLES_ARP=y
CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_RPFILTER=m
CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_SECURITY=m
CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m CONFIG_IP_NF_ARP_MANGLE=m
CONFIG_NF_TABLES_IPV6=y
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
CONFIG_IP6_NF_SECURITY=m
CONFIG_IP6_NF_NAT=m
CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_NF_TABLES_BRIDGE=m
CONFIG_BRIDGE_NF_EBTABLES=m
CONFIG_BRIDGE_EBT_T_FILTER=m
CONFIG_BRIDGE_EBT_T_NAT=m
CONFIG_IP_SCTP=m CONFIG_IP_SCTP=m
CONFIG_L2TP=m CONFIG_L2TP=m
CONFIG_BRIDGE=m CONFIG_BRIDGE=m
CONFIG_VSOCKETS=m
CONFIG_VIRTIO_VSOCKETS=m
CONFIG_CFG80211=m CONFIG_CFG80211=m
CONFIG_CFG80211_WEXT=y CONFIG_CFG80211_WEXT=y
CONFIG_MAC80211=m CONFIG_MAC80211=m
CONFIG_RFKILL=m CONFIG_RFKILL=m
CONFIG_RFKILL_INPUT=y CONFIG_RFKILL_INPUT=y
CONFIG_NET_9P=m
CONFIG_NET_9P_VIRTIO=m
CONFIG_PCIEPORTBUS=y
# CONFIG_PCIEASPM is not set
CONFIG_HOTPLUG_PCI=y
CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=m CONFIG_MTD=m
...@@ -103,6 +145,7 @@ CONFIG_BLK_DEV_LOOP=y ...@@ -103,6 +145,7 @@ CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_CRYPTOLOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_VIRTIO_BLK=y
CONFIG_RAID_ATTRS=m CONFIG_RAID_ATTRS=m
CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SD=y
CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR=y
...@@ -118,6 +161,7 @@ CONFIG_MEGARAID_MM=y ...@@ -118,6 +161,7 @@ CONFIG_MEGARAID_MM=y
CONFIG_MEGARAID_MAILBOX=y CONFIG_MEGARAID_MAILBOX=y
CONFIG_MEGARAID_LEGACY=y CONFIG_MEGARAID_LEGACY=y
CONFIG_MEGARAID_SAS=y CONFIG_MEGARAID_SAS=y
CONFIG_SCSI_VIRTIO=y
CONFIG_ATA=y CONFIG_ATA=y
CONFIG_SATA_AHCI=y CONFIG_SATA_AHCI=y
CONFIG_PATA_ATIIXP=y CONFIG_PATA_ATIIXP=y
...@@ -141,7 +185,10 @@ CONFIG_TCM_PSCSI=m ...@@ -141,7 +185,10 @@ CONFIG_TCM_PSCSI=m
CONFIG_LOOPBACK_TARGET=m CONFIG_LOOPBACK_TARGET=m
CONFIG_ISCSI_TARGET=m CONFIG_ISCSI_TARGET=m
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
CONFIG_DUMMY=m
CONFIG_TUN=m CONFIG_TUN=m
CONFIG_VETH=m
CONFIG_VIRTIO_NET=m
# CONFIG_NET_VENDOR_3COM is not set # CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set # CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_ALTEON is not set # CONFIG_NET_VENDOR_ALTEON is not set
...@@ -200,6 +247,8 @@ CONFIG_ATH9K=m ...@@ -200,6 +247,8 @@ CONFIG_ATH9K=m
CONFIG_HOSTAP=m CONFIG_HOSTAP=m
CONFIG_INPUT_POLLDEV=m CONFIG_INPUT_POLLDEV=m
CONFIG_INPUT_SPARSEKMAP=y CONFIG_INPUT_SPARSEKMAP=y
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_XTKBD=m CONFIG_KEYBOARD_XTKBD=m
CONFIG_MOUSE_PS2_SENTELIC=y CONFIG_MOUSE_PS2_SENTELIC=y
...@@ -209,7 +258,6 @@ CONFIG_INPUT_UINPUT=m ...@@ -209,7 +258,6 @@ CONFIG_INPUT_UINPUT=m
CONFIG_SERIO_SERPORT=m CONFIG_SERIO_SERPORT=m
CONFIG_SERIO_RAW=m CONFIG_SERIO_RAW=m
CONFIG_LEGACY_PTY_COUNT=16 CONFIG_LEGACY_PTY_COUNT=16
CONFIG_SERIAL_NONSTANDARD=y
CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=16 CONFIG_SERIAL_8250_NR_UARTS=16
...@@ -218,6 +266,8 @@ CONFIG_SERIAL_8250_MANY_PORTS=y ...@@ -218,6 +266,8 @@ CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_RSA=y CONFIG_SERIAL_8250_RSA=y
CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_NONSTANDARD=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM=y
CONFIG_RAW_DRIVER=m CONFIG_RAW_DRIVER=m
CONFIG_I2C_CHARDEV=y CONFIG_I2C_CHARDEV=y
...@@ -232,6 +282,8 @@ CONFIG_MEDIA_USB_SUPPORT=y ...@@ -232,6 +282,8 @@ CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m CONFIG_USB_VIDEO_CLASS=m
CONFIG_DRM=y CONFIG_DRM=y
CONFIG_DRM_RADEON=m CONFIG_DRM_RADEON=m
CONFIG_DRM_QXL=y
CONFIG_DRM_VIRTIO_GPU=y
CONFIG_FB_RADEON=y CONFIG_FB_RADEON=y
CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_PLATFORM=m CONFIG_LCD_PLATFORM=m
...@@ -248,10 +300,15 @@ CONFIG_SND_SEQ_DUMMY=m ...@@ -248,10 +300,15 @@ CONFIG_SND_SEQ_DUMMY=m
CONFIG_SND_HDA_INTEL=m CONFIG_SND_HDA_INTEL=m
CONFIG_SND_HDA_PATCH_LOADER=y CONFIG_SND_HDA_PATCH_LOADER=y
CONFIG_SND_HDA_CODEC_REALTEK=m CONFIG_SND_HDA_CODEC_REALTEK=m
CONFIG_SND_HDA_CODEC_SIGMATEL=m
CONFIG_SND_HDA_CODEC_HDMI=m
CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CONEXANT=m
# CONFIG_SND_USB is not set # CONFIG_SND_USB is not set
CONFIG_HIDRAW=y
CONFIG_HID_A4TECH=m CONFIG_HID_A4TECH=m
CONFIG_HID_SUNPLUS=m CONFIG_HID_SUNPLUS=m
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_USB_MON=y CONFIG_USB_MON=y
CONFIG_USB_XHCI_HCD=m CONFIG_USB_XHCI_HCD=m
...@@ -264,7 +321,16 @@ CONFIG_USB_SERIAL=m ...@@ -264,7 +321,16 @@ CONFIG_USB_SERIAL=m
CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_SERIAL_OPTION=m
CONFIG_RTC_CLASS=y CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_CMOS=y CONFIG_RTC_DRV_CMOS=y
CONFIG_RTC_DRV_GOLDFISH=y
CONFIG_DMADEVICES=y CONFIG_DMADEVICES=y
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_INPUT=y
CONFIG_VIRTIO_MMIO=y
CONFIG_VHOST_NET=m
CONFIG_VHOST_SCSI=m
CONFIG_VHOST_VSOCK=m
CONFIG_GOLDFISH=y
CONFIG_PM_DEVFREQ=y CONFIG_PM_DEVFREQ=y
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y CONFIG_DEVFREQ_GOV_PERFORMANCE=y
...@@ -277,10 +343,16 @@ CONFIG_EXT2_FS_SECURITY=y ...@@ -277,10 +343,16 @@ CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y CONFIG_EXT3_FS_SECURITY=y
CONFIG_XFS_FS=y
CONFIG_XFS_POSIX_ACL=y
CONFIG_QUOTA=y CONFIG_QUOTA=y
# CONFIG_PRINT_QUOTA_WARNING is not set # CONFIG_PRINT_QUOTA_WARNING is not set
CONFIG_QFMT_V1=m
CONFIG_QFMT_V2=m
CONFIG_AUTOFS4_FS=y CONFIG_AUTOFS4_FS=y
CONFIG_FUSE_FS=m CONFIG_FUSE_FS=m
CONFIG_VIRTIO_FS=m
CONFIG_FSCACHE=m
CONFIG_ISO9660_FS=m CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y CONFIG_JOLIET=y
CONFIG_MSDOS_FS=m CONFIG_MSDOS_FS=m
...@@ -301,6 +373,9 @@ CONFIG_NFSD=m ...@@ -301,6 +373,9 @@ CONFIG_NFSD=m
CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V3_ACL=y
CONFIG_NFSD_V4=y CONFIG_NFSD_V4=y
CONFIG_CIFS=m CONFIG_CIFS=m
CONFIG_9P_FS=m
CONFIG_9P_FSCACHE=y
CONFIG_9P_FS_POSIX_ACL=y
CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_936=y CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_ASCII=y CONFIG_NLS_ASCII=y
...@@ -334,3 +409,5 @@ CONFIG_MAGIC_SYSRQ=y ...@@ -334,3 +409,5 @@ CONFIG_MAGIC_SYSRQ=y
# CONFIG_SCHED_DEBUG is not set # CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set # CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set # CONFIG_FTRACE is not set
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="ieee754=relaxed"
CONFIG_SYSVIPC=y
CONFIG_PREEMPT=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_SLAB=y
CONFIG_MIPS_PARAVIRT=y
CONFIG_CPU_MIPS64_R2=y
CONFIG_64BIT=y
CONFIG_SMP=y
CONFIG_HZ_1000=y
CONFIG_PCI=y
CONFIG_MIPS32_O32=y
CONFIG_MIPS32_N32=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_IP_MROUTE=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
# CONFIG_WIRELESS is not set
# CONFIG_FW_LOADER is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_VIRTIO_BLK=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_VIRTIO_NET=y
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_PHYLIB=y
CONFIG_BCM87XX_PHY=y
CONFIG_BROADCOM_PHY=y
CONFIG_MARVELL_PHY=y
# CONFIG_WLAN is not set
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_VIRTIO_CONSOLE=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_MMIO=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_HUGETLBFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_DES=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_FTRACE is not set
...@@ -108,6 +108,7 @@ CONFIG_RTC_DRV_JZ4740=y ...@@ -108,6 +108,7 @@ CONFIG_RTC_DRV_JZ4740=y
CONFIG_DMADEVICES=y CONFIG_DMADEVICES=y
CONFIG_DMA_JZ4780=y CONFIG_DMA_JZ4780=y
CONFIG_MEMORY=y CONFIG_MEMORY=y
CONFIG_JZ4780_NEMC=y
CONFIG_IIO=y CONFIG_IIO=y
CONFIG_INGENIC_ADC=y CONFIG_INGENIC_ADC=y
CONFIG_PWM=y CONFIG_PWM=y
......
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_DEFAULT_HOSTNAME="rs90"
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y
# CONFIG_SGETMASK_SYSCALL is not set
# CONFIG_SYSFS_SYSCALL is not set
# CONFIG_ELF_CORE is not set
# CONFIG_BASE_FULL is not set
# CONFIG_TIMERFD is not set
# CONFIG_AIO is not set
# CONFIG_IO_URING is not set
# CONFIG_ADVISE_SYSCALLS is not set
# CONFIG_KALLSYMS is not set
CONFIG_EMBEDDED=y
# CONFIG_PERF_EVENTS is not set
CONFIG_SLAB=y
CONFIG_PROFILING=y
CONFIG_MACH_INGENIC=y
CONFIG_JZ4740_RS90=y
CONFIG_PAGE_SIZE_16KB=y
CONFIG_HZ_100=y
# CONFIG_SECCOMP is not set
CONFIG_MIPS_CMDLINE_DTB_EXTEND=y
# CONFIG_SUSPEND is not set
CONFIG_PM=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
CONFIG_CPUFREQ_DT=y
CONFIG_OPROFILE=y
CONFIG_JUMP_LABEL=y
# CONFIG_STACKPROTECTOR is not set
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
# CONFIG_EFI_PARTITION is not set
# CONFIG_MQ_IOSCHED_DEADLINE is not set
# CONFIG_MQ_IOSCHED_KYBER is not set
CONFIG_FRONTSWAP=y
CONFIG_CMA=y
CONFIG_ZSMALLOC=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
# CONFIG_INET_DIAG is not set
CONFIG_TCP_CONG_ADVANCED=y
# CONFIG_TCP_CONG_BIC is not set
# CONFIG_TCP_CONG_CUBIC is not set
# CONFIG_TCP_CONG_HTCP is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_JZ4780=y
CONFIG_MTD_NAND_JZ4725B_BCH=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_ZRAM=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=0
CONFIG_NETDEVICES=y
# CONFIG_ETHERNET is not set
# CONFIG_WLAN is not set
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_ADC=y
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_LEGACY_PTY_COUNT=2
# CONFIG_DEVMEM is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_I2C_COMPAT is not set
# CONFIG_I2C_HELPER_AUTO is not set
CONFIG_POWER_SUPPLY=y
CONFIG_BATTERY_INGENIC=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is not set
CONFIG_JZ4740_WDT=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_DRM=y
CONFIG_DRM_FBDEV_OVERALLOC=300
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_INGENIC=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_BACKLIGHT_PWM=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_PCM_TIMER is not set
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_PROC_FS is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_MIPS is not set
CONFIG_SND_SOC=y
CONFIG_SND_JZ4740_SOC_I2S=y
CONFIG_SND_SOC_JZ4725B_CODEC=y
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y
CONFIG_SND_SIMPLE_CARD=y
# CONFIG_HID is not set
CONFIG_USB_MUSB_HDRC=y
CONFIG_USB_MUSB_JZ4740=y
CONFIG_USB_INVENTRA_DMA=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_VBUS_DRAW=500
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_MMC=y
# CONFIG_PWRSEQ_EMMC is not set
# CONFIG_PWRSEQ_SIMPLE is not set
CONFIG_MMC_JZ4740=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_HCTOSYS is not set
# CONFIG_RTC_SYSTOHC is not set
# CONFIG_RTC_NVMEM is not set
# CONFIG_RTC_INTF_PROC is not set
CONFIG_RTC_DRV_JZ4740=y
CONFIG_DMADEVICES=y
CONFIG_DMA_JZ4780=y
# CONFIG_VIRTIO_MENU is not set
# CONFIG_MIPS_PLATFORM_DEVICES is not set
CONFIG_INGENIC_OST=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_MEMORY=y
CONFIG_JZ4780_NEMC=y
CONFIG_IIO=y
CONFIG_INGENIC_ADC=y
CONFIG_IIO_RESCALE=y
CONFIG_PWM=y
CONFIG_PWM_JZ4740=y
# CONFIG_NVMEM is not set
CONFIG_EXT4_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_VFAT_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
# CONFIG_UBIFS_FS_ZSTD is not set
# CONFIG_UBIFS_FS_XATTR is not set
CONFIG_SQUASHFS=y
CONFIG_SQUASHFS_FILE_DIRECT=y
CONFIG_SQUASHFS_DECOMP_MULTI=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
# CONFIG_CRYPTO_HW is not set
CONFIG_FONTS=y
CONFIG_FONT_6x10=y
# CONFIG_SYMBOLIC_ERRNAME is not set
CONFIG_STRIP_ASM_SYMS=y
# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
# CONFIG_DEBUG_MISC is not set
CONFIG_PANIC_ON_OOPS=y
# CONFIG_FTRACE is not set
# CONFIG_RUNTIME_TESTING_MENU is not set
...@@ -5,6 +5,7 @@ generated-y += syscall_table_64_n32.h ...@@ -5,6 +5,7 @@ generated-y += syscall_table_64_n32.h
generated-y += syscall_table_64_n64.h generated-y += syscall_table_64_n64.h
generated-y += syscall_table_64_o32.h generated-y += syscall_table_64_o32.h
generic-y += export.h generic-y += export.h
generic-y += kvm_para.h
generic-y += local64.h generic-y += local64.h
generic-y += mcs_spinlock.h generic-y += mcs_spinlock.h
generic-y += parport.h generic-y += parport.h
......
...@@ -65,12 +65,23 @@ enum loongson2ef_machine_type { ...@@ -65,12 +65,23 @@ enum loongson2ef_machine_type {
/* /*
* Valid machtype for group INGENIC * Valid machtype for group INGENIC
*/ */
#define MACH_INGENIC_JZ4730 0 /* JZ4730 SOC */ enum ingenic_machine_type {
#define MACH_INGENIC_JZ4740 1 /* JZ4740 SOC */ MACH_INGENIC_UNKNOWN,
#define MACH_INGENIC_JZ4770 2 /* JZ4770 SOC */ MACH_INGENIC_JZ4720,
#define MACH_INGENIC_JZ4780 3 /* JZ4780 SOC */ MACH_INGENIC_JZ4725,
#define MACH_INGENIC_X1000 4 /* X1000 SOC */ MACH_INGENIC_JZ4725B,
#define MACH_INGENIC_X1830 5 /* X1830 SOC */ MACH_INGENIC_JZ4730,
MACH_INGENIC_JZ4740,
MACH_INGENIC_JZ4750,
MACH_INGENIC_JZ4755,
MACH_INGENIC_JZ4760,
MACH_INGENIC_JZ4770,
MACH_INGENIC_JZ4775,
MACH_INGENIC_JZ4780,
MACH_INGENIC_X1000,
MACH_INGENIC_X1830,
MACH_INGENIC_X2000,
};
extern char *system_type; extern char *system_type;
const char *get_system_type(void); const char *get_system_type(void);
......
...@@ -113,9 +113,9 @@ static inline __sum16 csum_fold(__wsum csum) ...@@ -113,9 +113,9 @@ static inline __sum16 csum_fold(__wsum csum)
u32 sum = (__force u32)csum; u32 sum = (__force u32)csum;
sum += (sum << 16); sum += (sum << 16);
csum = (sum < csum); csum = (__force __wsum)(sum < (__force u32)csum);
sum >>= 16; sum >>= 16;
sum += csum; sum += (__force u32)csum;
return (__force __sum16)~sum; return (__force __sum16)~sum;
} }
......
...@@ -568,6 +568,14 @@ ...@@ -568,6 +568,14 @@
# define cpu_has_mac2008_only __opt(MIPS_CPU_MAC_2008_ONLY) # define cpu_has_mac2008_only __opt(MIPS_CPU_MAC_2008_ONLY)
#endif #endif
#ifndef cpu_has_ftlbparex
# define cpu_has_ftlbparex __opt(MIPS_CPU_FTLBPAREX)
#endif
#ifndef cpu_has_gsexcex
# define cpu_has_gsexcex __opt(MIPS_CPU_GSEXCEX)
#endif
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
/* /*
* Some systems share FTLB RAMs between threads within a core (siblings in * Some systems share FTLB RAMs between threads within a core (siblings in
......
...@@ -46,6 +46,7 @@ ...@@ -46,6 +46,7 @@
#define PRID_COMP_NETLOGIC 0x0c0000 #define PRID_COMP_NETLOGIC 0x0c0000
#define PRID_COMP_CAVIUM 0x0d0000 #define PRID_COMP_CAVIUM 0x0d0000
#define PRID_COMP_LOONGSON 0x140000 #define PRID_COMP_LOONGSON 0x140000
#define PRID_COMP_INGENIC_13 0x130000 /* X2000 */
#define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4740, JZ4750, X1830 */ #define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4740, JZ4750, X1830 */
#define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775, X1000 */ #define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775, X1000 */
#define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */ #define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */
...@@ -185,8 +186,9 @@ ...@@ -185,8 +186,9 @@
* These are the PRID's for when 23:16 == PRID_COMP_INGENIC_* * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
*/ */
#define PRID_IMP_XBURST_REV1 0x0200 /* XBurst with MXU SIMD ISA */ #define PRID_IMP_XBURST_REV1 0x0200 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
#define PRID_IMP_XBURST_REV2 0x0100 /* XBurst with MXU2 SIMD ISA */ #define PRID_IMP_XBURST_REV2 0x0100 /* XBurst®1 with MXU2.0 SIMD ISA */
#define PRID_IMP_XBURST2 0x2000 /* XBurst®2 with MXU2.1 SIMD ISA */
/* /*
* These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
...@@ -425,6 +427,8 @@ enum cpu_type_enum { ...@@ -425,6 +427,8 @@ enum cpu_type_enum {
#define MIPS_CPU_MM_SYSAD BIT_ULL(58) /* CPU supports write-through SysAD Valid merge */ #define MIPS_CPU_MM_SYSAD BIT_ULL(58) /* CPU supports write-through SysAD Valid merge */
#define MIPS_CPU_MM_FULL BIT_ULL(59) /* CPU supports write-through full merge */ #define MIPS_CPU_MM_FULL BIT_ULL(59) /* CPU supports write-through full merge */
#define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instruction */ #define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instruction */
#define MIPS_CPU_FTLBPAREX BIT_ULL(61) /* CPU has FTLB parity exception */
#define MIPS_CPU_GSEXCEX BIT_ULL(62) /* CPU has GSExc exception */
/* /*
* CPU ASE encodings * CPU ASE encodings
......
...@@ -410,6 +410,7 @@ do { \ ...@@ -410,6 +410,7 @@ do { \
clear_thread_flag(TIF_32BIT_FPREGS); \ clear_thread_flag(TIF_32BIT_FPREGS); \
clear_thread_flag(TIF_HYBRID_FPREGS); \ clear_thread_flag(TIF_HYBRID_FPREGS); \
clear_thread_flag(TIF_32BIT_ADDR); \ clear_thread_flag(TIF_32BIT_ADDR); \
current->personality &= ~READ_IMPLIES_EXEC; \
\ \
if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
__SET_PERSONALITY32(ex, state); \ __SET_PERSONALITY32(ex, state); \
......
...@@ -51,15 +51,13 @@ ...@@ -51,15 +51,13 @@
/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
#define IO_SPACE_LIMIT 0xffff
/* /*
* On MIPS I/O ports are memory mapped, so we access them using normal * On MIPS I/O ports are memory mapped, so we access them using normal
* load/store instructions. mips_io_port_base is the virtual address to * load/store instructions. mips_io_port_base is the virtual address to
* which all ports are being mapped. For sake of efficiency some code * which all ports are being mapped. For sake of efficiency some code
* assumes that this is an address that can be loaded with a single lui * assumes that this is an address that can be loaded with a single lui
* instruction, so the lower 16 bits must be zero. Should be true on * instruction, so the lower 16 bits must be zero. Should be true on
* on any sane architecture; generic code does not use this assumption. * any sane architecture; generic code does not use this assumption.
*/ */
extern unsigned long mips_io_port_base; extern unsigned long mips_io_port_base;
......
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_MIPS_KVM_PARA_H
#define _ASM_MIPS_KVM_PARA_H
#include <uapi/asm/kvm_para.h>
#define KVM_HYPERCALL ".word 0x42000028"
/*
* Hypercalls for KVM.
*
* Hypercall number is passed in v0.
* Return value will be placed in v0.
* Up to 3 arguments are passed in a0, a1, and a2.
*/
static inline unsigned long kvm_hypercall0(unsigned long num)
{
register unsigned long n asm("v0");
register unsigned long r asm("v0");
n = num;
__asm__ __volatile__(
KVM_HYPERCALL
: "=r" (r) : "r" (n) : "memory"
);
return r;
}
static inline unsigned long kvm_hypercall1(unsigned long num,
unsigned long arg0)
{
register unsigned long n asm("v0");
register unsigned long r asm("v0");
register unsigned long a0 asm("a0");
n = num;
a0 = arg0;
__asm__ __volatile__(
KVM_HYPERCALL
: "=r" (r) : "r" (n), "r" (a0) : "memory"
);
return r;
}
static inline unsigned long kvm_hypercall2(unsigned long num,
unsigned long arg0, unsigned long arg1)
{
register unsigned long n asm("v0");
register unsigned long r asm("v0");
register unsigned long a0 asm("a0");
register unsigned long a1 asm("a1");
n = num;
a0 = arg0;
a1 = arg1;
__asm__ __volatile__(
KVM_HYPERCALL
: "=r" (r) : "r" (n), "r" (a0), "r" (a1) : "memory"
);
return r;
}
static inline unsigned long kvm_hypercall3(unsigned long num,
unsigned long arg0, unsigned long arg1, unsigned long arg2)
{
register unsigned long n asm("v0");
register unsigned long r asm("v0");
register unsigned long a0 asm("a0");
register unsigned long a1 asm("a1");
register unsigned long a2 asm("a2");
n = num;
a0 = arg0;
a1 = arg1;
a2 = arg2;
__asm__ __volatile__(
KVM_HYPERCALL
: "=r" (r) : "r" (n), "r" (a0), "r" (a1), "r" (a2) : "memory"
);
return r;
}
static inline bool kvm_check_and_clear_guest_paused(void)
{
return false;
}
static inline unsigned int kvm_arch_para_features(void)
{
return 0;
}
static inline unsigned int kvm_arch_para_hints(void)
{
return 0;
}
#ifdef CONFIG_MIPS_PARAVIRT
static inline bool kvm_para_available(void)
{
return true;
}
#else
static inline bool kvm_para_available(void)
{
return false;
}
#endif
#endif /* _ASM_MIPS_KVM_PARA_H */
...@@ -48,11 +48,17 @@ static inline bool __should_swizzle_addr(u64 p) ...@@ -48,11 +48,17 @@ static inline bool __should_swizzle_addr(u64 p)
# define ioswabb(a, x) (x) # define ioswabb(a, x) (x)
# define __mem_ioswabb(a, x) (x) # define __mem_ioswabb(a, x) (x)
# define ioswabw(a, x) (__should_swizzle_bits(a) ? le16_to_cpu(x) : x) # define ioswabw(a, x) (__should_swizzle_bits(a) ? \
le16_to_cpu((__force __le16)(x)) : \
(x))
# define __mem_ioswabw(a, x) (x) # define __mem_ioswabw(a, x) (x)
# define ioswabl(a, x) (__should_swizzle_bits(a) ? le32_to_cpu(x) : x) # define ioswabl(a, x) (__should_swizzle_bits(a) ? \
le32_to_cpu((__force __le32)(x)) : \
(x))
# define __mem_ioswabl(a, x) (x) # define __mem_ioswabl(a, x) (x)
# define ioswabq(a, x) (__should_swizzle_bits(a) ? le64_to_cpu(x) : x) # define ioswabq(a, x) (__should_swizzle_bits(a) ? \
le64_to_cpu((__force __le64)(x)) : \
(x))
# define __mem_ioswabq(a, x) (x) # define __mem_ioswabq(a, x) (x)
#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */ #endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
...@@ -43,7 +43,6 @@ ...@@ -43,7 +43,6 @@
#define cpu_has_dsp2 0 #define cpu_has_dsp2 0
#define cpu_has_mipsmt 0 #define cpu_has_mipsmt 0
#define cpu_has_userlocal 0 #define cpu_has_userlocal 0
#define cpu_hwrena_impl_bits 0
#define cpu_has_perf_cntr_intr_bit 0 #define cpu_has_perf_cntr_intr_bit 0
#define cpu_has_vz 0 #define cpu_has_vz 0
#define cpu_has_fre 0 #define cpu_has_fre 0
......
...@@ -29,11 +29,11 @@ ...@@ -29,11 +29,11 @@
# define ioswabb(a, x) (x) # define ioswabb(a, x) (x)
# define __mem_ioswabb(a, x) (x) # define __mem_ioswabb(a, x) (x)
# define ioswabw(a, x) le16_to_cpu(x) # define ioswabw(a, x) le16_to_cpu((__force __le16)(x))
# define __mem_ioswabw(a, x) (x) # define __mem_ioswabw(a, x) (x)
# define ioswabl(a, x) le32_to_cpu(x) # define ioswabl(a, x) le32_to_cpu((__force __le32)(x))
# define __mem_ioswabl(a, x) (x) # define __mem_ioswabl(a, x) (x)
# define ioswabq(a, x) le64_to_cpu(x) # define ioswabq(a, x) le64_to_cpu((__force __le64)(x))
# define __mem_ioswabq(a, x) (x) # define __mem_ioswabq(a, x) (x)
#else #else
...@@ -41,11 +41,11 @@ ...@@ -41,11 +41,11 @@
# define ioswabb(a, x) (x) # define ioswabb(a, x) (x)
# define __mem_ioswabb(a, x) (x) # define __mem_ioswabb(a, x) (x)
# define ioswabw(a, x) (x) # define ioswabw(a, x) (x)
# define __mem_ioswabw(a, x) cpu_to_le16(x) # define __mem_ioswabw(a, x) ((__force u16)cpu_to_le16(x))
# define ioswabl(a, x) (x) # define ioswabl(a, x) (x)
# define __mem_ioswabl(a, x) cpu_to_le32(x) # define __mem_ioswabl(a, x) ((__force u32)cpu_to_le32(x))
# define ioswabq(a, x) (x) # define ioswabq(a, x) (x)
# define __mem_ioswabq(a, x) cpu_to_le32(x) # define __mem_ioswabq(a, x) ((__force u64)cpu_to_le64(x))
#endif #endif
......
...@@ -14,6 +14,10 @@ ...@@ -14,6 +14,10 @@
#include <asm/mipsregs.h> #include <asm/mipsregs.h>
#ifndef IO_SPACE_LIMIT
#define IO_SPACE_LIMIT 0xffff
#endif
/* /*
* This gives the physical RAM offset. * This gives the physical RAM offset.
*/ */
......
...@@ -25,8 +25,6 @@ ...@@ -25,8 +25,6 @@
#define cpu_has_4kex 1 #define cpu_has_4kex 1
#define cpu_has_3k_cache 0 #define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1 #define cpu_has_4k_cache 1
#define cpu_has_6k_cache 0
#define cpu_has_8k_cache 0
#define cpu_has_tx39_cache 0 #define cpu_has_tx39_cache 0
#define cpu_has_fpu 1 #define cpu_has_fpu 1
#define cpu_has_nofpuex 0 #define cpu_has_nofpuex 0
...@@ -67,7 +65,6 @@ ...@@ -67,7 +65,6 @@
#define cpu_has_mipsmt 0 #define cpu_has_mipsmt 0
#define cpu_has_userlocal 0 #define cpu_has_userlocal 0
#define cpu_has_inclusive_pcaches 1 #define cpu_has_inclusive_pcaches 1
#define cpu_hwrena_impl_bits 0
#define cpu_has_perf_cntr_intr_bit 0 #define cpu_has_perf_cntr_intr_bit 0
#define cpu_has_vz 0 #define cpu_has_vz 0
#define cpu_has_fre 0 #define cpu_has_fre 0
......
...@@ -16,10 +16,10 @@ ...@@ -16,10 +16,10 @@
# define ioswabb(a, x) (x) # define ioswabb(a, x) (x)
# define __mem_ioswabb(a, x) (x) # define __mem_ioswabb(a, x) (x)
# define ioswabw(a, x) (x) # define ioswabw(a, x) (x)
# define __mem_ioswabw(a, x) cpu_to_le16(x) # define __mem_ioswabw(a, x) ((__force u16)cpu_to_le16(x))
# define ioswabl(a, x) (x) # define ioswabl(a, x) (x)
# define __mem_ioswabl(a, x) cpu_to_le32(x) # define __mem_ioswabl(a, x) ((__force u32)cpu_to_le32(x))
# define ioswabq(a, x) (x) # define ioswabq(a, x) (x)
# define __mem_ioswabq(a, x) cpu_to_le64(x) # define __mem_ioswabq(a, x) ((__force u64)cpu_to_le64(x))
#endif /* __ASM_MACH_IP27_MANGLE_PORT_H */ #endif /* __ASM_MACH_IP27_MANGLE_PORT_H */
...@@ -28,8 +28,6 @@ ...@@ -28,8 +28,6 @@
#define cpu_has_4kex 1 #define cpu_has_4kex 1
#define cpu_has_3k_cache 0 #define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1 #define cpu_has_4k_cache 1
#define cpu_has_6k_cache 0
#define cpu_has_8k_cache 0
#define cpu_has_tx39_cache 0 #define cpu_has_tx39_cache 0
#define cpu_has_fpu 1 #define cpu_has_fpu 1
#define cpu_has_nofpuex 0 #define cpu_has_nofpuex 0
...@@ -69,7 +67,6 @@ ...@@ -69,7 +67,6 @@
#define cpu_has_mipsmt 0 #define cpu_has_mipsmt 0
#define cpu_has_userlocal 0 #define cpu_has_userlocal 0
#define cpu_has_inclusive_pcaches 1 #define cpu_has_inclusive_pcaches 1
#define cpu_hwrena_impl_bits 0
#define cpu_has_perf_cntr_intr_bit 0 #define cpu_has_perf_cntr_intr_bit 0
#define cpu_has_vz 0 #define cpu_has_vz 0
#define cpu_has_fre 0 #define cpu_has_fre 0
......
...@@ -13,10 +13,10 @@ ...@@ -13,10 +13,10 @@
#define ioswabb(a, x) (x) #define ioswabb(a, x) (x)
#define __mem_ioswabb(a, x) (x) #define __mem_ioswabb(a, x) (x)
#define ioswabw(a, x) (x) #define ioswabw(a, x) (x)
#define __mem_ioswabw(a, x) cpu_to_le16(x) #define __mem_ioswabw(a, x) ((__force u16)cpu_to_le16(x))
#define ioswabl(a, x) (x) #define ioswabl(a, x) (x)
#define __mem_ioswabl(a, x) cpu_to_le32(x) #define __mem_ioswabl(a, x) ((__force u32)cpu_to_le32(x))
#define ioswabq(a, x) (x) #define ioswabq(a, x) (x)
#define __mem_ioswabq(a, x) cpu_to_le64(x) #define __mem_ioswabq(a, x) ((__force u64)cpu_to_le64(x))
#endif /* __ASM_MACH_IP30_MANGLE_PORT_H */ #endif /* __ASM_MACH_IP30_MANGLE_PORT_H */
...@@ -17,10 +17,10 @@ ...@@ -17,10 +17,10 @@
# define ioswabb(a, x) (x) # define ioswabb(a, x) (x)
# define __mem_ioswabb(a, x) (x) # define __mem_ioswabb(a, x) (x)
# define ioswabw(a, x) (x) # define ioswabw(a, x) (x)
# define __mem_ioswabw(a, x) cpu_to_le16(x) # define __mem_ioswabw(a, x) ((__force u16)cpu_to_le16(x))
# define ioswabl(a, x) (x) # define ioswabl(a, x) (x)
# define __mem_ioswabl(a, x) cpu_to_le32(x) # define __mem_ioswabl(a, x) ((__force u32)cpu_to_le32(x))
# define ioswabq(a, x) (x) # define ioswabq(a, x) (x)
# define __mem_ioswabq(a, x) cpu_to_le32(x) # define __mem_ioswabq(a, x) ((__force u64)cpu_to_le64(x))
#endif /* __ASM_MACH_IP32_MANGLE_PORT_H */ #endif /* __ASM_MACH_IP32_MANGLE_PORT_H */
...@@ -194,7 +194,8 @@ struct boot_params { ...@@ -194,7 +194,8 @@ struct boot_params {
enum loongson_bridge_type { enum loongson_bridge_type {
LS7A = 1, LS7A = 1,
RS780E = 2 RS780E = 2,
VIRTUAL = 3
}; };
struct loongson_system_configuration { struct loongson_system_configuration {
...@@ -230,5 +231,6 @@ extern struct loongson_system_configuration loongson_sysconf; ...@@ -230,5 +231,6 @@ extern struct loongson_system_configuration loongson_sysconf;
extern u32 node_id_offset; extern u32 node_id_offset;
extern void ls7a_early_config(void); extern void ls7a_early_config(void);
extern void rs780e_early_config(void); extern void rs780e_early_config(void);
extern void virtual_early_config(void);
#endif #endif
...@@ -8,6 +8,9 @@ ...@@ -8,6 +8,9 @@
#ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_ #ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
#define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_ #define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
extern u32 __dtb_loongson3_4core_rs780e_begin[]; extern u32 __dtb_loongson64c_4core_ls7a_begin[];
extern u32 __dtb_loongson3_8core_rs780e_begin[]; extern u32 __dtb_loongson64c_4core_rs780e_begin[];
extern u32 __dtb_loongson64c_8core_rs780e_begin[];
extern u32 __dtb_loongson64g_4core_ls7a_begin[];
extern u32 __dtb_loongson64v_4core_virtio_begin[];
#endif #endif
...@@ -5,7 +5,11 @@ ...@@ -5,7 +5,11 @@
#include <boot_param.h> #include <boot_param.h>
/* cpu core interrupt numbers */ /* cpu core interrupt numbers */
#define MIPS_CPU_IRQ_BASE 56 #define NR_IRQS_LEGACY 16
#define NR_MIPS_CPU_IRQS 8
#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256)
#define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY
#include <asm/mach-generic/irq.h> #include <asm/mach-generic/irq.h>
......
...@@ -11,8 +11,7 @@ ...@@ -11,8 +11,7 @@
#define PCI_IOSIZE SZ_16M #define PCI_IOSIZE SZ_16M
#define MAP_BASE (PCI_IOBASE + PCI_IOSIZE) #define MAP_BASE (PCI_IOBASE + PCI_IOSIZE)
/* Reserved at the start of PCI_IOBASE for legacy drivers */ #define IO_SPACE_LIMIT (PCI_IOSIZE - 1)
#define MMIO_LOWER_RESERVED 0x10000
#include <asm/mach-generic/spaces.h> #include <asm/mach-generic/spaces.h>
#endif #endif
...@@ -29,7 +29,6 @@ ...@@ -29,7 +29,6 @@
#define cpu_has_octeon_cache 1 #define cpu_has_octeon_cache 1
#define cpu_has_4k_cache 0 #define cpu_has_4k_cache 0
#else #else
#define cpu_has_octeon_cache 0
#define cpu_has_4k_cache 1 #define cpu_has_4k_cache 1
#endif #endif
......
...@@ -14,11 +14,11 @@ extern unsigned long (*__swizzle_addr_b)(unsigned long port); ...@@ -14,11 +14,11 @@ extern unsigned long (*__swizzle_addr_b)(unsigned long port);
#define ioswabb(a, x) (x) #define ioswabb(a, x) (x)
#define __mem_ioswabb(a, x) (x) #define __mem_ioswabb(a, x) (x)
#define ioswabw(a, x) le16_to_cpu(x) #define ioswabw(a, x) le16_to_cpu((__force __le16)(x))
#define __mem_ioswabw(a, x) (x) #define __mem_ioswabw(a, x) (x)
#define ioswabl(a, x) le32_to_cpu(x) #define ioswabl(a, x) le32_to_cpu((__force __le32)(x))
#define __mem_ioswabl(a, x) (x) #define __mem_ioswabl(a, x) (x)
#define ioswabq(a, x) le64_to_cpu(x) #define ioswabq(a, x) le64_to_cpu((__force __le64)(x))
#define __mem_ioswabq(a, x) (x) #define __mem_ioswabq(a, x) (x)
#endif /* __ASM_MACH_TX39XX_MANGLE_PORT_H */ #endif /* __ASM_MACH_TX39XX_MANGLE_PORT_H */
...@@ -16,12 +16,12 @@ ...@@ -16,12 +16,12 @@
extern u16 (*ioswabw)(volatile u16 *a, u16 x); extern u16 (*ioswabw)(volatile u16 *a, u16 x);
extern u16 (*__mem_ioswabw)(volatile u16 *a, u16 x); extern u16 (*__mem_ioswabw)(volatile u16 *a, u16 x);
#else #else
#define ioswabw(a, x) le16_to_cpu(x) #define ioswabw(a, x) le16_to_cpu((__force __le16)(x))
#define __mem_ioswabw(a, x) (x) #define __mem_ioswabw(a, x) (x)
#endif #endif
#define ioswabl(a, x) le32_to_cpu(x) #define ioswabl(a, x) le32_to_cpu((__force __le32)(x))
#define __mem_ioswabl(a, x) (x) #define __mem_ioswabl(a, x) (x)
#define ioswabq(a, x) le64_to_cpu(x) #define ioswabq(a, x) le64_to_cpu((__force __le64)(x))
#define __mem_ioswabq(a, x) (x) #define __mem_ioswabq(a, x) (x)
#endif /* __ASM_MACH_TX49XX_MANGLE_PORT_H */ #endif /* __ASM_MACH_TX49XX_MANGLE_PORT_H */
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
*/
#ifndef __ASM_MIPS_MACHINE_H
#define __ASM_MIPS_MACHINE_H
#include <linux/init.h>
#include <linux/stddef.h>
#include <asm/bootinfo.h>
struct mips_machine {
unsigned long mach_type;
const char *mach_id;
const char *mach_name;
void (*mach_setup)(void);
};
#define MIPS_MACHINE(_type, _id, _name, _setup) \
static const char machine_name_##_type[] __initconst \
__aligned(1) = _name; \
static const char machine_id_##_type[] __initconst \
__aligned(1) = _id; \
static struct mips_machine machine_##_type \
__used __section(.mips.machines.init) = \
{ \
.mach_type = _type, \
.mach_id = machine_id_##_type, \
.mach_name = machine_name_##_type, \
.mach_setup = _setup, \
};
extern long __mips_machines_start;
extern long __mips_machines_end;
#ifdef CONFIG_MIPS_MACHINE
int mips_machtype_setup(char *id) __init;
void mips_machine_setup(void) __init;
#else
static inline int mips_machtype_setup(char *id) { return 1; }
static inline void mips_machine_setup(void) { }
#endif /* CONFIG_MIPS_MACHINE */
#endif /* __ASM_MIPS_MACHINE_H */
...@@ -86,6 +86,7 @@ ...@@ -86,6 +86,7 @@
#define CP0_XCONTEXT $20 #define CP0_XCONTEXT $20
#define CP0_FRAMEMASK $21 #define CP0_FRAMEMASK $21
#define CP0_DIAGNOSTIC $22 #define CP0_DIAGNOSTIC $22
#define CP0_DIAGNOSTIC1 $22, 1
#define CP0_DEBUG $23 #define CP0_DEBUG $23
#define CP0_DEPC $24 #define CP0_DEPC $24
#define CP0_PERFORMANCE $25 #define CP0_PERFORMANCE $25
...@@ -473,6 +474,9 @@ ...@@ -473,6 +474,9 @@
/* Implementation specific trap codes used by MIPS cores */ /* Implementation specific trap codes used by MIPS cores */
#define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */ #define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */
/* Implementation specific trap codes used by Loongson cores */
#define LOONGSON_EXCCODE_GSEXC 16 /* Loongson-specific exception */
/* /*
* Bits in the coprocessor 0 config register. * Bits in the coprocessor 0 config register.
*/ */
...@@ -689,35 +693,35 @@ ...@@ -689,35 +693,35 @@
/* Config6 feature bits for proAptiv/P5600 */ /* Config6 feature bits for proAptiv/P5600 */
/* Jump register cache prediction disable */ /* Jump register cache prediction disable */
#define MIPS_CONF6_MTI_JRCD (_ULCAST_(1) << 0) #define MTI_CONF6_JRCD (_ULCAST_(1) << 0)
/* MIPSr6 extensions enable */ /* MIPSr6 extensions enable */
#define MIPS_CONF6_MTI_R6 (_ULCAST_(1) << 2) #define MTI_CONF6_R6 (_ULCAST_(1) << 2)
/* IFU Performance Control */ /* IFU Performance Control */
#define MIPS_CONF6_MTI_IFUPERFCTL (_ULCAST_(3) << 10) #define MTI_CONF6_IFUPERFCTL (_ULCAST_(3) << 10)
#define MIPS_CONF6_MTI_SYND (_ULCAST_(1) << 13) #define MTI_CONF6_SYND (_ULCAST_(1) << 13)
/* Sleep state performance counter disable */ /* Sleep state performance counter disable */
#define MIPS_CONF6_MTI_SPCD (_ULCAST_(1) << 14) #define MTI_CONF6_SPCD (_ULCAST_(1) << 14)
/* proAptiv FTLB on/off bit */ /* proAptiv FTLB on/off bit */
#define MIPS_CONF6_MTI_FTLBEN (_ULCAST_(1) << 15) #define MTI_CONF6_FTLBEN (_ULCAST_(1) << 15)
/* Disable load/store bonding */ /* Disable load/store bonding */
#define MIPS_CONF6_MTI_DLSB (_ULCAST_(1) << 21) #define MTI_CONF6_DLSB (_ULCAST_(1) << 21)
/* FTLB probability bits */ /* FTLB probability bits */
#define MIPS_CONF6_MTI_FTLBP_SHIFT (16) #define MTI_CONF6_FTLBP_SHIFT (16)
/* Config6 feature bits for Loongson-3 */ /* Config6 feature bits for Loongson-3 */
/* Loongson-3 internal timer bit */ /* Loongson-3 internal timer bit */
#define MIPS_CONF6_LOONGSON_INTIMER (_ULCAST_(1) << 6) #define LOONGSON_CONF6_INTIMER (_ULCAST_(1) << 6)
/* Loongson-3 external timer bit */ /* Loongson-3 external timer bit */
#define MIPS_CONF6_LOONGSON_EXTIMER (_ULCAST_(1) << 7) #define LOONGSON_CONF6_EXTIMER (_ULCAST_(1) << 7)
/* Loongson-3 SFB on/off bit, STFill in manual */ /* Loongson-3 SFB on/off bit, STFill in manual */
#define MIPS_CONF6_LOONGSON_SFBEN (_ULCAST_(1) << 8) #define LOONGSON_CONF6_SFBEN (_ULCAST_(1) << 8)
/* Loongson-3's LL on exclusive cacheline */ /* Loongson-3's LL on exclusive cacheline */
#define MIPS_CONF6_LOONGSON_LLEXC (_ULCAST_(1) << 16) #define LOONGSON_CONF6_LLEXC (_ULCAST_(1) << 16)
/* Loongson-3's SC has a random delay */ /* Loongson-3's SC has a random delay */
#define MIPS_CONF6_LOONGSON_SCRAND (_ULCAST_(1) << 17) #define LOONGSON_CONF6_SCRAND (_ULCAST_(1) << 17)
/* Loongson-3 FTLB on/off bit, VTLBOnly in manual */ /* Loongson-3 FTLB on/off bit, VTLBOnly in manual */
#define MIPS_CONF6_LOONGSON_FTLBDIS (_ULCAST_(1) << 22) #define LOONGSON_CONF6_FTLBDIS (_ULCAST_(1) << 22)
#define MIPS_CONF7_WII (_ULCAST_(1) << 31) #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
...@@ -1051,6 +1055,13 @@ ...@@ -1051,6 +1055,13 @@
/* Flush FTLB */ /* Flush FTLB */
#define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13) #define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13)
/*
* Diag1 (GSCause in Loongson-speak) fields
*/
/* Loongson-specific exception code (GSExcCode) */
#define LOONGSON_DIAG1_EXCCODE_SHIFT 2
#define LOONGSON_DIAG1_EXCCODE GENMASK(6, 2)
/* CvmCtl register field definitions */ /* CvmCtl register field definitions */
#define CVMCTL_IPPCI_SHIFT 7 #define CVMCTL_IPPCI_SHIFT 7
#define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT) #define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
......
...@@ -327,7 +327,7 @@ void cvmx_l2c_flush(void); ...@@ -327,7 +327,7 @@ void cvmx_l2c_flush(void);
/** /**
* *
* Returns Returns the size of the L2 cache in bytes, * Returns the size of the L2 cache in bytes,
* -1 on error (unrecognized model) * -1 on error (unrecognized model)
*/ */
int cvmx_l2c_get_cache_size_bytes(void); int cvmx_l2c_get_cache_size_bytes(void);
......
...@@ -503,7 +503,7 @@ static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index) ...@@ -503,7 +503,7 @@ static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index)
* offsetof() to determine the offsets into packet headers. * offsetof() to determine the offsets into packet headers.
* For example, offsetof(ethhdr, protocol) returns the offset * For example, offsetof(ethhdr, protocol) returns the offset
* of the ethernet protocol field. The bitmask selects which * of the ethernet protocol field. The bitmask selects which
* bytes to include the the tag, with bit offset X selecting * bytes to include the tag, with bit offset X selecting
* byte at offset X from the beginning of the packet data. * byte at offset X from the beginning of the packet data.
* @len: Number of bytes to include. Usually this is the sizeof() * @len: Number of bytes to include. Usually this is the sizeof()
* the field. * the field.
......
...@@ -40,8 +40,7 @@ ...@@ -40,8 +40,7 @@
* generic code while CVMX_PKO_LOCK_CMD_QUEUE should be used * generic code while CVMX_PKO_LOCK_CMD_QUEUE should be used
* with hand tuned fast path code. * with hand tuned fast path code.
* *
* Some of other SDK differences visible to the command command * Some of other SDK differences visible to the command queuing:
* queuing:
* - PKO indexes are no longer stored in the FAU. A large * - PKO indexes are no longer stored in the FAU. A large
* percentage of the FAU register block used to be tied up * percentage of the FAU register block used to be tied up
* maintaining PKO queue pointers. These are now stored in a * maintaining PKO queue pointers. These are now stored in a
...@@ -413,7 +412,7 @@ static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue, ...@@ -413,7 +412,7 @@ static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
* @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
* CVMX_PKO_LOCK_CMD_QUEUE * CVMX_PKO_LOCK_CMD_QUEUE
* *
* Returns returns CVMX_PKO_SUCCESS on success, or error code on * Returns: CVMX_PKO_SUCCESS on success, or error code on
* failure of output * failure of output
*/ */
static inline cvmx_pko_status_t cvmx_pko_send_packet_finish( static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(
...@@ -456,7 +455,7 @@ static inline cvmx_pko_status_t cvmx_pko_send_packet_finish( ...@@ -456,7 +455,7 @@ static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(
* @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
* CVMX_PKO_LOCK_CMD_QUEUE * CVMX_PKO_LOCK_CMD_QUEUE
* *
* Returns returns CVMX_PKO_SUCCESS on success, or error code on * Returns: CVMX_PKO_SUCCESS on success, or error code on
* failure of output * failure of output
*/ */
static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3( static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3(
......
...@@ -1345,7 +1345,7 @@ static inline void cvmx_pow_tag_sw_wait(void) ...@@ -1345,7 +1345,7 @@ static inline void cvmx_pow_tag_sw_wait(void)
* @wait: When set, call stalls until work becomes avaiable, or times out. * @wait: When set, call stalls until work becomes avaiable, or times out.
* If not set, returns immediately. * If not set, returns immediately.
* *
* Returns Returns the WQE pointer from POW. Returns NULL if no work * Returns: the WQE pointer from POW. Returns NULL if no work
* was available. * was available.
*/ */
static inline struct cvmx_wqe *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_t static inline struct cvmx_wqe *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_t
...@@ -1379,7 +1379,7 @@ static inline struct cvmx_wqe *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_ ...@@ -1379,7 +1379,7 @@ static inline struct cvmx_wqe *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_
* @wait: When set, call stalls until work becomes avaiable, or times out. * @wait: When set, call stalls until work becomes avaiable, or times out.
* If not set, returns immediately. * If not set, returns immediately.
* *
* Returns Returns the WQE pointer from POW. Returns NULL if no work * Returns: the WQE pointer from POW. Returns NULL if no work
* was available. * was available.
*/ */
static inline struct cvmx_wqe *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait) static inline struct cvmx_wqe *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait)
...@@ -1398,7 +1398,7 @@ static inline struct cvmx_wqe *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait) ...@@ -1398,7 +1398,7 @@ static inline struct cvmx_wqe *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait)
* This function waits for any previous tag switch to complete before * This function waits for any previous tag switch to complete before
* requesting the null_rd. * requesting the null_rd.
* *
* Returns Returns the POW state of type cvmx_pow_tag_type_t. * Returns: the POW state of type cvmx_pow_tag_type_t.
*/ */
static inline enum cvmx_pow_tag_type cvmx_pow_work_request_null_rd(void) static inline enum cvmx_pow_tag_type cvmx_pow_work_request_null_rd(void)
{ {
...@@ -1482,7 +1482,7 @@ static inline void cvmx_pow_work_request_async(int scr_addr, ...@@ -1482,7 +1482,7 @@ static inline void cvmx_pow_work_request_async(int scr_addr,
* @scr_addr: Scratch memory address to get result from Byte address, * @scr_addr: Scratch memory address to get result from Byte address,
* must be 8 byte aligned. * must be 8 byte aligned.
* *
* Returns Returns the WQE from the scratch register, or NULL if no * Returns: the WQE from the scratch register, or NULL if no
* work was available. * work was available.
*/ */
static inline struct cvmx_wqe *cvmx_pow_work_response_async(int scr_addr) static inline struct cvmx_wqe *cvmx_pow_work_response_async(int scr_addr)
......
...@@ -198,7 +198,7 @@ union octeon_cvmemctl { ...@@ -198,7 +198,7 @@ union octeon_cvmemctl {
* CvmMemCtl[DIDTTO] */ * CvmMemCtl[DIDTTO] */
__BITFIELD_FIELD(uint64_t didtto2:1, __BITFIELD_FIELD(uint64_t didtto2:1,
/* R/W If set, marked write-buffer entries time out /* R/W If set, marked write-buffer entries time out
* the same as as other entries; if clear, marked * the same as other entries; if clear, marked
* write-buffer entries use the maximum timeout. */ * write-buffer entries use the maximum timeout. */
__BITFIELD_FIELD(uint64_t dismarkwblongto:1, __BITFIELD_FIELD(uint64_t dismarkwblongto:1,
/* R/W If set, a merged store does not clear the /* R/W If set, a merged store does not clear the
......
...@@ -121,7 +121,7 @@ ...@@ -121,7 +121,7 @@
* operate correctly if the internal data cache refill buffer is empty. These * operate correctly if the internal data cache refill buffer is empty. These
* CACHE instructions should be separated from any potential data cache miss * CACHE instructions should be separated from any potential data cache miss
* by a load instruction to an uncached address to empty the response buffer." * by a load instruction to an uncached address to empty the response buffer."
* (Revision 2.0 device errata from IDT available on http://www.idt.com/ * (Revision 2.0 device errata from IDT available on https://www.idt.com/
* in .pdf format.) * in .pdf format.)
*/ */
#ifndef R4600_V2_HIT_CACHEOP_WAR #ifndef R4600_V2_HIT_CACHEOP_WAR
......
...@@ -5,3 +5,5 @@ generated-y += unistd_o32.h ...@@ -5,3 +5,5 @@ generated-y += unistd_o32.h
generated-y += unistd_nr_n32.h generated-y += unistd_nr_n32.h
generated-y += unistd_nr_n64.h generated-y += unistd_nr_n64.h
generated-y += unistd_nr_o32.h generated-y += unistd_nr_o32.h
generic-y += kvm_para.h
#ifndef _UAPI_ASM_MIPS_KVM_PARA_H
#define _UAPI_ASM_MIPS_KVM_PARA_H
#endif /* _UAPI_ASM_MIPS_KVM_PARA_H */
...@@ -15,6 +15,10 @@ config JZ4740_QI_LB60 ...@@ -15,6 +15,10 @@ config JZ4740_QI_LB60
bool "Qi Hardware Ben NanoNote" bool "Qi Hardware Ben NanoNote"
select MACH_JZ4740 select MACH_JZ4740
config JZ4740_RS90
bool "YLM RetroMini (RS-90)"
select MACH_JZ4725B
config JZ4770_GCW0 config JZ4770_GCW0
bool "Game Consoles Worldwide GCW Zero" bool "Game Consoles Worldwide GCW Zero"
select MACH_JZ4770 select MACH_JZ4770
...@@ -27,8 +31,16 @@ config X1000_CU1000_NEO ...@@ -27,8 +31,16 @@ config X1000_CU1000_NEO
bool "YSH & ATIL CU1000 Module with Neo backplane" bool "YSH & ATIL CU1000 Module with Neo backplane"
select MACH_X1000 select MACH_X1000
config X1830_CU1830_NEO
bool "YSH & ATIL CU1830 Module with Neo backplane"
select MACH_X1830
endchoice endchoice
config MACH_JZ4725B
bool
select SYS_HAS_CPU_MIPS32_R1
config MACH_JZ4740 config MACH_JZ4740
bool bool
select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R1
...@@ -50,3 +62,9 @@ config MACH_X1000 ...@@ -50,3 +62,9 @@ config MACH_X1000
select MIPS_CPU_SCACHE select MIPS_CPU_SCACHE
select SYS_HAS_CPU_MIPS32_R2 select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_HIGHMEM
config MACH_X1830
bool
select MIPS_CPU_SCACHE
select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_HIGHMEM
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
#include <linux/of_clk.h> #include <linux/of_clk.h>
#include <linux/of_fdt.h> #include <linux/of_fdt.h>
#include <linux/pm.h> #include <linux/pm.h>
#include <linux/sizes.h>
#include <linux/suspend.h> #include <linux/suspend.h>
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
...@@ -22,33 +23,10 @@ ...@@ -22,33 +23,10 @@
#include <asm/reboot.h> #include <asm/reboot.h>
#include <asm/time.h> #include <asm/time.h>
#define JZ4740_EMC_BASE_ADDR 0x13010000
#define JZ4740_EMC_SDRAM_CTRL 0x80
static void __init jz4740_detect_mem(void)
{
void __iomem *jz_emc_base;
u32 ctrl, bus, bank, rows, cols;
phys_addr_t size;
jz_emc_base = ioremap(JZ4740_EMC_BASE_ADDR, 0x100);
ctrl = readl(jz_emc_base + JZ4740_EMC_SDRAM_CTRL);
bus = 2 - ((ctrl >> 31) & 1);
bank = 1 + ((ctrl >> 19) & 1);
cols = 8 + ((ctrl >> 26) & 7);
rows = 11 + ((ctrl >> 20) & 3);
printk(KERN_DEBUG
"SDRAM preconfigured: bus:%u bank:%u rows:%u cols:%u\n",
bus, bank, rows, cols);
iounmap(jz_emc_base);
size = 1 << (bus + bank + cols + rows);
add_memory_region(0, size, BOOT_MEM_RAM);
}
static unsigned long __init get_board_mach_type(const void *fdt) static unsigned long __init get_board_mach_type(const void *fdt)
{ {
if (!fdt_node_check_compatible(fdt, 0, "ingenic,x2000"))
return MACH_INGENIC_X2000;
if (!fdt_node_check_compatible(fdt, 0, "ingenic,x1830")) if (!fdt_node_check_compatible(fdt, 0, "ingenic,x1830"))
return MACH_INGENIC_X1830; return MACH_INGENIC_X1830;
if (!fdt_node_check_compatible(fdt, 0, "ingenic,x1000")) if (!fdt_node_check_compatible(fdt, 0, "ingenic,x1000"))
...@@ -57,25 +35,25 @@ static unsigned long __init get_board_mach_type(const void *fdt) ...@@ -57,25 +35,25 @@ static unsigned long __init get_board_mach_type(const void *fdt)
return MACH_INGENIC_JZ4780; return MACH_INGENIC_JZ4780;
if (!fdt_node_check_compatible(fdt, 0, "ingenic,jz4770")) if (!fdt_node_check_compatible(fdt, 0, "ingenic,jz4770"))
return MACH_INGENIC_JZ4770; return MACH_INGENIC_JZ4770;
if (!fdt_node_check_compatible(fdt, 0, "ingenic,jz4725b"))
return MACH_INGENIC_JZ4725B;
return MACH_INGENIC_JZ4740; return MACH_INGENIC_JZ4740;
} }
void __init plat_mem_setup(void) void __init plat_mem_setup(void)
{ {
int offset; void *dtb = (void *)fw_passed_dtb;
void *dtb;
if (__dtb_start != __dtb_end)
dtb = __dtb_start;
else
dtb = (void *)fw_passed_dtb;
__dt_setup_arch(dtb); __dt_setup_arch(dtb);
offset = fdt_path_offset(dtb, "/memory"); /*
if (offset < 0) * Old devicetree files for the qi,lb60 board did not have a /memory
jz4740_detect_mem(); * node. Hardcode the memory info here.
*/
if (!fdt_node_check_compatible(dtb, 0, "qi,lb60") &&
fdt_path_offset(dtb, "/memory") < 0)
early_init_dt_add_memory_arch(0, SZ_32M);
mips_machtype = get_board_mach_type(dtb); mips_machtype = get_board_mach_type(dtb);
} }
...@@ -91,6 +69,8 @@ void __init device_tree_init(void) ...@@ -91,6 +69,8 @@ void __init device_tree_init(void)
const char *get_system_type(void) const char *get_system_type(void)
{ {
switch (mips_machtype) { switch (mips_machtype) {
case MACH_INGENIC_X2000:
return "X2000";
case MACH_INGENIC_X1830: case MACH_INGENIC_X1830:
return "X1830"; return "X1830";
case MACH_INGENIC_X1000: case MACH_INGENIC_X1000:
...@@ -99,6 +79,8 @@ const char *get_system_type(void) ...@@ -99,6 +79,8 @@ const char *get_system_type(void)
return "JZ4780"; return "JZ4780";
case MACH_INGENIC_JZ4770: case MACH_INGENIC_JZ4770:
return "JZ4770"; return "JZ4770";
case MACH_INGENIC_JZ4725B:
return "JZ4725B";
default: default:
return "JZ4740"; return "JZ4740";
} }
......
...@@ -93,7 +93,6 @@ obj-$(CONFIG_CRASH_DUMP) += crash_dump.o ...@@ -93,7 +93,6 @@ obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-$(CONFIG_EARLY_PRINTK_8250) += early_printk_8250.o obj-$(CONFIG_EARLY_PRINTK_8250) += early_printk_8250.o
obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o
obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o
obj-$(CONFIG_MIPSR2_TO_R6_EMULATOR) += mips-r2-to-r6-emul.o obj-$(CONFIG_MIPSR2_TO_R6_EMULATOR) += mips-r2-to-r6-emul.o
CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -x c /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -x c /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
......
...@@ -635,14 +635,14 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags) ...@@ -635,14 +635,14 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
config = read_c0_config6(); config = read_c0_config6();
if (flags & FTLB_EN) if (flags & FTLB_EN)
config |= MIPS_CONF6_MTI_FTLBEN; config |= MTI_CONF6_FTLBEN;
else else
config &= ~MIPS_CONF6_MTI_FTLBEN; config &= ~MTI_CONF6_FTLBEN;
if (flags & FTLB_SET_PROB) { if (flags & FTLB_SET_PROB) {
config &= ~(3 << MIPS_CONF6_MTI_FTLBP_SHIFT); config &= ~(3 << MTI_CONF6_FTLBP_SHIFT);
config |= calculate_ftlb_probability(c) config |= calculate_ftlb_probability(c)
<< MIPS_CONF6_MTI_FTLBP_SHIFT; << MTI_CONF6_FTLBP_SHIFT;
} }
write_c0_config6(config); write_c0_config6(config);
...@@ -662,10 +662,10 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags) ...@@ -662,10 +662,10 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
config = read_c0_config6(); config = read_c0_config6();
if (flags & FTLB_EN) if (flags & FTLB_EN)
/* Enable FTLB */ /* Enable FTLB */
write_c0_config6(config & ~MIPS_CONF6_LOONGSON_FTLBDIS); write_c0_config6(config & ~LOONGSON_CONF6_FTLBDIS);
else else
/* Disable FTLB */ /* Disable FTLB */
write_c0_config6(config | MIPS_CONF6_LOONGSON_FTLBDIS); write_c0_config6(config | LOONGSON_CONF6_FTLBDIS);
break; break;
default: default:
return 1; return 1;
...@@ -1827,6 +1827,19 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -1827,6 +1827,19 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
default: default:
break; break;
} }
/* Recent MIPS cores use the implementation-dependent ExcCode 16 for
* cache/FTLB parity exceptions.
*/
switch (__get_cpu_type(c->cputype)) {
case CPU_PROAPTIV:
case CPU_P5600:
case CPU_P6600:
case CPU_I6400:
case CPU_I6500:
c->options |= MIPS_CPU_FTLBPAREX;
break;
}
} }
static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
...@@ -2030,6 +2043,9 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -2030,6 +2043,9 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
{ {
decode_configs(c); decode_configs(c);
/* All Loongson processors covered here define ExcCode 16 as GSExc. */
c->options |= MIPS_CPU_GSEXCEX;
switch (c->processor_id & PRID_IMP_MASK) { switch (c->processor_id & PRID_IMP_MASK) {
case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */ case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */
switch (c->processor_id & PRID_REV_MASK) { switch (c->processor_id & PRID_REV_MASK) {
...@@ -2110,6 +2126,8 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -2110,6 +2126,8 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
switch (c->processor_id & PRID_IMP_MASK) { switch (c->processor_id & PRID_IMP_MASK) {
/* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
case PRID_IMP_XBURST_REV1: case PRID_IMP_XBURST_REV1:
/* /*
...@@ -2148,12 +2166,20 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -2148,12 +2166,20 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
break; break;
} }
fallthrough; fallthrough;
/* XBurst®1 with MXU2.0 SIMD ISA */
case PRID_IMP_XBURST_REV2: case PRID_IMP_XBURST_REV2:
c->cputype = CPU_XBURST; c->cputype = CPU_XBURST;
c->writecombine = _CACHE_UNCACHED_ACCELERATED; c->writecombine = _CACHE_UNCACHED_ACCELERATED;
__cpu_name[cpu] = "Ingenic XBurst"; __cpu_name[cpu] = "Ingenic XBurst";
break; break;
/* XBurst®2 with MXU2.1 SIMD ISA */
case PRID_IMP_XBURST2:
c->cputype = CPU_XBURST;
__cpu_name[cpu] = "Ingenic XBurst II";
break;
default: default:
panic("Unknown Ingenic Processor ID!"); panic("Unknown Ingenic Processor ID!");
break; break;
...@@ -2299,6 +2325,7 @@ void cpu_probe(void) ...@@ -2299,6 +2325,7 @@ void cpu_probe(void)
case PRID_COMP_LOONGSON: case PRID_COMP_LOONGSON:
cpu_probe_loongson(c, cpu); cpu_probe_loongson(c, cpu);
break; break;
case PRID_COMP_INGENIC_13:
case PRID_COMP_INGENIC_D0: case PRID_COMP_INGENIC_D0:
case PRID_COMP_INGENIC_D1: case PRID_COMP_INGENIC_D1:
case PRID_COMP_INGENIC_E1: case PRID_COMP_INGENIC_E1:
......
...@@ -498,6 +498,19 @@ NESTED(nmi_handler, PT_SIZE, sp) ...@@ -498,6 +498,19 @@ NESTED(nmi_handler, PT_SIZE, sp)
KMODE KMODE
.endm .endm
.macro __build_clear_gsexc
.set push
/*
* We need to specify a selector to access the CP0.Diag1 (GSCause)
* register. All GSExc-equipped processors have MIPS32.
*/
.set mips32
mfc0 a1, CP0_DIAGNOSTIC1
.set pop
TRACE_IRQS_ON
STI
.endm
.macro __BUILD_silent exception .macro __BUILD_silent exception
.endm .endm
...@@ -556,6 +569,7 @@ NESTED(nmi_handler, PT_SIZE, sp) ...@@ -556,6 +569,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
BUILD_HANDLER fpe fpe fpe silent /* #15 */ BUILD_HANDLER fpe fpe fpe silent /* #15 */
#endif #endif
BUILD_HANDLER ftlb ftlb none silent /* #16 */ BUILD_HANDLER ftlb ftlb none silent /* #16 */
BUILD_HANDLER gsexc gsexc gsexc silent /* #16 */
BUILD_HANDLER msa msa sti silent /* #21 */ BUILD_HANDLER msa msa sti silent /* #21 */
BUILD_HANDLER mdmx mdmx sti silent /* #22 */ BUILD_HANDLER mdmx mdmx sti silent /* #22 */
#ifdef CONFIG_HARDWARE_WATCHPOINTS #ifdef CONFIG_HARDWARE_WATCHPOINTS
......
...@@ -111,6 +111,12 @@ NESTED(kernel_entry, 16, sp) # kernel entry point ...@@ -111,6 +111,12 @@ NESTED(kernel_entry, 16, sp) # kernel entry point
move t2, a1 move t2, a1
beq a0, t1, dtb_found beq a0, t1, dtb_found
#ifdef CONFIG_BUILTIN_DTB
PTR_LA t2, __dtb_start
PTR_LA t1, __dtb_end
bne t1, t2, dtb_found
#endif /* CONFIG_BUILTIN_DTB */
li t2, 0 li t2, 0
dtb_found: dtb_found:
#endif /* CONFIG_USE_OF */ #endif /* CONFIG_USE_OF */
......
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
*/
#include <linux/mm.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <asm/mips_machine.h>
#include <asm/prom.h>
static struct mips_machine *mips_machine __initdata;
#define for_each_machine(mach) \
for ((mach) = (struct mips_machine *)&__mips_machines_start; \
(mach) && \
(unsigned long)(mach) < (unsigned long)&__mips_machines_end; \
(mach)++)
__init int mips_machtype_setup(char *id)
{
struct mips_machine *mach;
for_each_machine(mach) {
if (mach->mach_id == NULL)
continue;
if (strcmp(mach->mach_id, id) == 0) {
mips_machtype = mach->mach_type;
return 0;
}
}
pr_err("MIPS: no machine found for id '%s', supported machines:\n", id);
pr_err("%-24s %s\n", "id", "name");
for_each_machine(mach)
pr_err("%-24s %s\n", mach->mach_id, mach->mach_name);
return 1;
}
__setup("machtype=", mips_machtype_setup);
__init void mips_machine_setup(void)
{
struct mips_machine *mach;
for_each_machine(mach) {
if (mips_machtype == mach->mach_type) {
mips_machine = mach;
break;
}
}
if (!mips_machine)
return;
mips_set_machine_name(mips_machine->mach_name);
if (mips_machine->mach_setup)
mips_machine->mach_setup();
}
...@@ -497,7 +497,7 @@ static void __init mips_parse_crashkernel(void) ...@@ -497,7 +497,7 @@ static void __init mips_parse_crashkernel(void)
if (ret != 0 || crash_size <= 0) if (ret != 0 || crash_size <= 0)
return; return;
if (!memblock_find_in_range(crash_base, crash_base + crash_size, crash_size, 0)) { if (!memblock_find_in_range(crash_base, crash_base + crash_size, crash_size, 1)) {
pr_warn("Invalid memory region reserved for crash kernel\n"); pr_warn("Invalid memory region reserved for crash kernel\n");
return; return;
} }
......
...@@ -20,7 +20,7 @@ static int __init topology_init(void) ...@@ -20,7 +20,7 @@ static int __init topology_init(void)
for_each_present_cpu(i) { for_each_present_cpu(i) {
struct cpu *c = &per_cpu(cpu_devices, i); struct cpu *c = &per_cpu(cpu_devices, i);
c->hotpluggable = 1; c->hotpluggable = !!i;
ret = register_cpu(c, i); ret = register_cpu(c, i);
if (ret) if (ret)
printk(KERN_WARNING "topology_init: register_cpu %d " printk(KERN_WARNING "topology_init: register_cpu %d "
......
...@@ -90,6 +90,7 @@ extern asmlinkage void handle_tr(void); ...@@ -90,6 +90,7 @@ extern asmlinkage void handle_tr(void);
extern asmlinkage void handle_msa_fpe(void); extern asmlinkage void handle_msa_fpe(void);
extern asmlinkage void handle_fpe(void); extern asmlinkage void handle_fpe(void);
extern asmlinkage void handle_ftlb(void); extern asmlinkage void handle_ftlb(void);
extern asmlinkage void handle_gsexc(void);
extern asmlinkage void handle_msa(void); extern asmlinkage void handle_msa(void);
extern asmlinkage void handle_mdmx(void); extern asmlinkage void handle_mdmx(void);
extern asmlinkage void handle_watch(void); extern asmlinkage void handle_watch(void);
...@@ -1680,7 +1681,7 @@ __setup("nol2par", nol2parity); ...@@ -1680,7 +1681,7 @@ __setup("nol2par", nol2parity);
* Some MIPS CPUs can enable/disable for cache parity detection, but do * Some MIPS CPUs can enable/disable for cache parity detection, but do
* it different ways. * it different ways.
*/ */
static inline void parity_protection_init(void) static inline __init void parity_protection_init(void)
{ {
#define ERRCTL_PE 0x80000000 #define ERRCTL_PE 0x80000000
#define ERRCTL_L2P 0x00800000 #define ERRCTL_L2P 0x00800000
...@@ -1902,6 +1903,37 @@ asmlinkage void do_ftlb(void) ...@@ -1902,6 +1903,37 @@ asmlinkage void do_ftlb(void)
cache_parity_error(); cache_parity_error();
} }
asmlinkage void do_gsexc(struct pt_regs *regs, u32 diag1)
{
u32 exccode = (diag1 & LOONGSON_DIAG1_EXCCODE) >>
LOONGSON_DIAG1_EXCCODE_SHIFT;
enum ctx_state prev_state;
prev_state = exception_enter();
switch (exccode) {
case 0x08:
/* Undocumented exception, will trigger on certain
* also-undocumented instructions accessible from userspace.
* Processor state is not otherwise corrupted, but currently
* we don't know how to proceed. Maybe there is some
* undocumented control flag to enable the instructions?
*/
force_sig(SIGILL);
break;
default:
/* None of the other exceptions, documented or not, have
* further details given; none are encountered in the wild
* either. Panic in case some of them turn out to be fatal.
*/
show_regs(regs);
panic("Unhandled Loongson exception - GSCause = %08x", diag1);
}
exception_exit(prev_state);
}
/* /*
* SDBBP EJTAG debug exception handler. * SDBBP EJTAG debug exception handler.
* We skip the instruction and return to the next instruction. * We skip the instruction and return to the next instruction.
...@@ -2457,8 +2489,12 @@ void __init trap_init(void) ...@@ -2457,8 +2489,12 @@ void __init trap_init(void)
if (cpu_has_fpu && !cpu_has_nofpuex) if (cpu_has_fpu && !cpu_has_nofpuex)
set_except_vector(EXCCODE_FPE, handle_fpe); set_except_vector(EXCCODE_FPE, handle_fpe);
if (cpu_has_ftlbparex)
set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb); set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
if (cpu_has_gsexcex)
set_except_vector(LOONGSON_EXCCODE_GSEXC, handle_gsexc);
if (cpu_has_rixiex) { if (cpu_has_rixiex) {
set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0); set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0); set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
......
...@@ -129,7 +129,7 @@ static inline unsigned int kvm_vz_config5_guest_wrmask(struct kvm_vcpu *vcpu) ...@@ -129,7 +129,7 @@ static inline unsigned int kvm_vz_config5_guest_wrmask(struct kvm_vcpu *vcpu)
static inline unsigned int kvm_vz_config6_guest_wrmask(struct kvm_vcpu *vcpu) static inline unsigned int kvm_vz_config6_guest_wrmask(struct kvm_vcpu *vcpu)
{ {
return MIPS_CONF6_LOONGSON_INTIMER | MIPS_CONF6_LOONGSON_EXTIMER; return LOONGSON_CONF6_INTIMER | LOONGSON_CONF6_EXTIMER;
} }
/* /*
...@@ -189,7 +189,7 @@ static inline unsigned int kvm_vz_config5_user_wrmask(struct kvm_vcpu *vcpu) ...@@ -189,7 +189,7 @@ static inline unsigned int kvm_vz_config5_user_wrmask(struct kvm_vcpu *vcpu)
static inline unsigned int kvm_vz_config6_user_wrmask(struct kvm_vcpu *vcpu) static inline unsigned int kvm_vz_config6_user_wrmask(struct kvm_vcpu *vcpu)
{ {
return kvm_vz_config6_guest_wrmask(vcpu) | return kvm_vz_config6_guest_wrmask(vcpu) |
MIPS_CONF6_LOONGSON_SFBEN | MIPS_CONF6_LOONGSON_FTLBDIS; LOONGSON_CONF6_SFBEN | LOONGSON_CONF6_FTLBDIS;
} }
static gpa_t kvm_vz_gva_to_gpa_cb(gva_t gva) static gpa_t kvm_vz_gva_to_gpa_cb(gva_t gva)
......
...@@ -8,6 +8,28 @@ cflags-$(CONFIG_CPU_LOONGSON2E) += \ ...@@ -8,6 +8,28 @@ cflags-$(CONFIG_CPU_LOONGSON2E) += \
$(call cc-option,-march=loongson2e,-march=r4600) $(call cc-option,-march=loongson2e,-march=r4600)
cflags-$(CONFIG_CPU_LOONGSON2F) += \ cflags-$(CONFIG_CPU_LOONGSON2F) += \
$(call cc-option,-march=loongson2f,-march=r4600) $(call cc-option,-march=loongson2f,-march=r4600)
#
# Some versions of binutils, not currently mainline as of 2019/02/04, support
# an -mfix-loongson3-llsc flag which emits a sync prior to each ll instruction
# to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h for a
# description).
#
# We disable this in order to prevent the assembler meddling with the
# instruction that labels refer to, ie. if we label an ll instruction:
#
# 1: ll v0, 0(a0)
#
# ...then with the assembler fix applied the label may actually point at a sync
# instruction inserted by the assembler, and if we were using the label in an
# exception table the table would no longer contain the address of the ll
# instruction.
#
# Avoid this by explicitly disabling that assembler behaviour. If upstream
# binutils does not merge support for the flag then we can revisit & remove
# this later - for now it ensures vendor toolchains don't cause problems.
#
cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
# Enable the workarounds for Loongson2f # Enable the workarounds for Loongson2f
ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),) ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),)
......
...@@ -57,11 +57,11 @@ static void decode_loongson_config6(struct cpuinfo_mips *c) ...@@ -57,11 +57,11 @@ static void decode_loongson_config6(struct cpuinfo_mips *c)
{ {
u32 config6 = read_c0_config6(); u32 config6 = read_c0_config6();
if (config6 & MIPS_CONF6_LOONGSON_SFBEN) if (config6 & LOONGSON_CONF6_SFBEN)
c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SFBP; c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SFBP;
if (config6 & MIPS_CONF6_LOONGSON_LLEXC) if (config6 & LOONGSON_CONF6_LLEXC)
c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_LLEXC; c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_LLEXC;
if (config6 & MIPS_CONF6_LOONGSON_SCRAND) if (config6 & LOONGSON_CONF6_SCRAND)
c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SCRAND; c->loongson3_cpucfg_data[0] |= LOONGSON_CFG1_SCRAND;
} }
......
...@@ -126,28 +126,6 @@ void __init prom_init_env(void) ...@@ -126,28 +126,6 @@ void __init prom_init_env(void)
loongson_sysconf.cores_per_node - 1) / loongson_sysconf.cores_per_node - 1) /
loongson_sysconf.cores_per_node; loongson_sysconf.cores_per_node;
if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {
switch (read_c0_prid() & PRID_REV_MASK) {
case PRID_REV_LOONGSON3A_R1:
case PRID_REV_LOONGSON3A_R2_0:
case PRID_REV_LOONGSON3A_R2_1:
case PRID_REV_LOONGSON3A_R3_0:
case PRID_REV_LOONGSON3A_R3_1:
loongson_fdt_blob = __dtb_loongson3_4core_rs780e_begin;
break;
case PRID_REV_LOONGSON3B_R1:
case PRID_REV_LOONGSON3B_R2:
loongson_fdt_blob = __dtb_loongson3_8core_rs780e_begin;
break;
default:
break;
}
}
if (!loongson_fdt_blob)
pr_err("Failed to determine built-in Loongson64 dtb\n");
loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr; loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr;
loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr; loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr;
loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr; loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr;
...@@ -189,13 +167,57 @@ void __init prom_init_env(void) ...@@ -189,13 +167,57 @@ void __init prom_init_env(void)
vendor = id & 0xffff; vendor = id & 0xffff;
device = (id >> 16) & 0xffff; device = (id >> 16) & 0xffff;
if (vendor == PCI_VENDOR_ID_LOONGSON && device == 0x7a00) { switch (vendor) {
case PCI_VENDOR_ID_LOONGSON:
pr_info("The bridge chip is LS7A\n"); pr_info("The bridge chip is LS7A\n");
loongson_sysconf.bridgetype = LS7A; loongson_sysconf.bridgetype = LS7A;
loongson_sysconf.early_config = ls7a_early_config; loongson_sysconf.early_config = ls7a_early_config;
} else { break;
case PCI_VENDOR_ID_AMD:
case PCI_VENDOR_ID_ATI:
pr_info("The bridge chip is RS780E or SR5690\n"); pr_info("The bridge chip is RS780E or SR5690\n");
loongson_sysconf.bridgetype = RS780E; loongson_sysconf.bridgetype = RS780E;
loongson_sysconf.early_config = rs780e_early_config; loongson_sysconf.early_config = rs780e_early_config;
break;
default:
pr_info("The bridge chip is VIRTUAL\n");
loongson_sysconf.bridgetype = VIRTUAL;
loongson_sysconf.early_config = virtual_early_config;
loongson_fdt_blob = __dtb_loongson64v_4core_virtio_begin;
break;
} }
if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {
switch (read_c0_prid() & PRID_REV_MASK) {
case PRID_REV_LOONGSON3A_R1:
case PRID_REV_LOONGSON3A_R2_0:
case PRID_REV_LOONGSON3A_R2_1:
case PRID_REV_LOONGSON3A_R3_0:
case PRID_REV_LOONGSON3A_R3_1:
switch (loongson_sysconf.bridgetype) {
case LS7A:
loongson_fdt_blob = __dtb_loongson64c_4core_ls7a_begin;
break;
case RS780E:
loongson_fdt_blob = __dtb_loongson64c_4core_rs780e_begin;
break;
default:
break;
}
break;
case PRID_REV_LOONGSON3B_R1:
case PRID_REV_LOONGSON3B_R2:
if (loongson_sysconf.bridgetype == RS780E)
loongson_fdt_blob = __dtb_loongson64c_8core_rs780e_begin;
break;
default:
break;
}
} else if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G) {
if (loongson_sysconf.bridgetype == LS7A)
loongson_fdt_blob = __dtb_loongson64g_4core_ls7a_begin;
}
if (!loongson_fdt_blob)
pr_err("Failed to determine built-in Loongson64 dtb\n");
} }
...@@ -7,6 +7,8 @@ ...@@ -7,6 +7,8 @@
#include <linux/irqchip.h> #include <linux/irqchip.h>
#include <linux/logic_pio.h> #include <linux/logic_pio.h>
#include <linux/memblock.h> #include <linux/memblock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <asm/traps.h> #include <asm/traps.h>
#include <asm/smp-ops.h> #include <asm/smp-ops.h>
...@@ -40,6 +42,11 @@ void rs780e_early_config(void) ...@@ -40,6 +42,11 @@ void rs780e_early_config(void)
node_id_offset = 37; node_id_offset = 37;
} }
void virtual_early_config(void)
{
node_id_offset = 44;
}
void __init prom_init(void) void __init prom_init(void)
{ {
fw_init_cmdline(); fw_init_cmdline();
...@@ -63,41 +70,76 @@ void __init prom_free_prom_memory(void) ...@@ -63,41 +70,76 @@ void __init prom_free_prom_memory(void)
{ {
} }
static __init void reserve_pio_range(void) static int __init add_legacy_isa_io(struct fwnode_handle *fwnode, resource_size_t hw_start,
resource_size_t size)
{ {
int ret = 0;
struct logic_pio_hwaddr *range; struct logic_pio_hwaddr *range;
unsigned long vaddr;
range = kzalloc(sizeof(*range), GFP_ATOMIC); range = kzalloc(sizeof(*range), GFP_ATOMIC);
if (!range) if (!range)
return; return -ENOMEM;
range->fwnode = &of_root->fwnode; range->fwnode = fwnode;
range->size = MMIO_LOWER_RESERVED; range->size = size;
range->hw_start = LOONGSON_PCIIO_BASE; range->hw_start = hw_start;
range->flags = LOGIC_PIO_CPU_MMIO; range->flags = LOGIC_PIO_CPU_MMIO;
if (logic_pio_register_range(range)) { ret = logic_pio_register_range(range);
pr_err("Failed to reserve PIO range for legacy ISA\n"); if (ret) {
goto free_range; kfree(range);
return ret;
} }
if (WARN(range->io_start != 0, /* Legacy ISA must placed at the start of PCI_IOBASE */
"Reserved PIO range does not start from 0\n")) if (range->io_start != 0) {
goto unregister;
/*
* i8259 would access I/O space, so mapping must be done here.
* Please remove it when all drivers can be managed by logic_pio.
*/
ioremap_page_range(PCI_IOBASE, PCI_IOBASE + MMIO_LOWER_RESERVED,
LOONGSON_PCIIO_BASE,
pgprot_device(PAGE_KERNEL));
return;
unregister:
logic_pio_unregister_range(range); logic_pio_unregister_range(range);
free_range:
kfree(range); kfree(range);
return -EINVAL;
}
vaddr = PCI_IOBASE + range->io_start;
ioremap_page_range(vaddr, vaddr + size, hw_start, pgprot_device(PAGE_KERNEL));
return 0;
}
static __init void reserve_pio_range(void)
{
struct device_node *np;
for_each_node_by_name(np, "isa") {
struct of_range range;
struct of_range_parser parser;
pr_info("ISA Bridge: %pOF\n", np);
if (of_range_parser_init(&parser, np)) {
pr_info("Failed to parse resources.\n");
break;
}
for_each_of_range(&parser, &range) {
switch (range.flags & IORESOURCE_TYPE_BITS) {
case IORESOURCE_IO:
pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
range.cpu_addr,
range.cpu_addr + range.size - 1,
range.bus_addr);
if (add_legacy_isa_io(&np->fwnode, range.cpu_addr, range.size))
pr_warn("Failed to reserve legacy IO in Logic PIO\n");
break;
case IORESOURCE_MEM:
pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx\n",
range.cpu_addr,
range.cpu_addr + range.size - 1,
range.bus_addr);
break;
}
}
}
} }
void __init arch_init_irq(void) void __init arch_init_irq(void)
......
...@@ -1066,12 +1066,12 @@ static inline int alias_74k_erratum(struct cpuinfo_mips *c) ...@@ -1066,12 +1066,12 @@ static inline int alias_74k_erratum(struct cpuinfo_mips *c)
if (rev <= PRID_REV_ENCODE_332(2, 4, 0)) if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
present = 1; present = 1;
if (rev == PRID_REV_ENCODE_332(2, 4, 0)) if (rev == PRID_REV_ENCODE_332(2, 4, 0))
write_c0_config6(read_c0_config6() | MIPS_CONF6_MTI_SYND); write_c0_config6(read_c0_config6() | MTI_CONF6_SYND);
break; break;
case PRID_IMP_1074K: case PRID_IMP_1074K:
if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) { if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
present = 1; present = 1;
write_c0_config6(read_c0_config6() | MIPS_CONF6_MTI_SYND); write_c0_config6(read_c0_config6() | MTI_CONF6_SYND);
} }
break; break;
default: default:
......
# SPDX-License-Identifier: GPL-2.0
if MIPS_PARAVIRT
config MIPS_PCI_VIRTIO
def_bool y
endif # MIPS_PARAVIRT
#
# Makefile for MIPS para-virtualized specific kernel interface routines
# under Linux.
#
# This file is subject to the terms and conditions of the GNU General Public
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
# Copyright (C) 2013 Cavium, Inc.
#
obj-y := setup.o serial.o paravirt-irq.o
obj-$(CONFIG_SMP) += paravirt-smp.o
#
# Generic para-virtualized guest.
#
cflags-$(CONFIG_MIPS_PARAVIRT) += \
-I$(srctree)/arch/mips/include/asm/mach-paravirt
load-$(CONFIG_MIPS_PARAVIRT) = 0xffffffff80010000
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2013 Cavium, Inc.
*/
#include <linux/interrupt.h>
#include <linux/cpumask.h>
#include <linux/kernel.h>
#include <linux/mutex.h>
#include <asm/io.h>
#define MBOX_BITS_PER_CPU 2
static int cpunum_for_cpu(int cpu)
{
#ifdef CONFIG_SMP
return cpu_logical_map(cpu);
#else
return get_ebase_cpunum();
#endif
}
struct core_chip_data {
struct mutex core_irq_mutex;
bool current_en;
bool desired_en;
u8 bit;
};
static struct core_chip_data irq_core_chip_data[8];
static void irq_core_ack(struct irq_data *data)
{
struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
unsigned int bit = cd->bit;
/*
* We don't need to disable IRQs to make these atomic since
* they are already disabled earlier in the low level
* interrupt code.
*/
clear_c0_status(0x100 << bit);
/* The two user interrupts must be cleared manually. */
if (bit < 2)
clear_c0_cause(0x100 << bit);
}
static void irq_core_eoi(struct irq_data *data)
{
struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
/*
* We don't need to disable IRQs to make these atomic since
* they are already disabled earlier in the low level
* interrupt code.
*/
set_c0_status(0x100 << cd->bit);
}
static void irq_core_set_enable_local(void *arg)
{
struct irq_data *data = arg;
struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
unsigned int mask = 0x100 << cd->bit;
/*
* Interrupts are already disabled, so these are atomic.
*/
if (cd->desired_en)
set_c0_status(mask);
else
clear_c0_status(mask);
}
static void irq_core_disable(struct irq_data *data)
{
struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
cd->desired_en = false;
}
static void irq_core_enable(struct irq_data *data)
{
struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
cd->desired_en = true;
}
static void irq_core_bus_lock(struct irq_data *data)
{
struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
mutex_lock(&cd->core_irq_mutex);
}
static void irq_core_bus_sync_unlock(struct irq_data *data)
{
struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
if (cd->desired_en != cd->current_en) {
on_each_cpu(irq_core_set_enable_local, data, 1);
cd->current_en = cd->desired_en;
}
mutex_unlock(&cd->core_irq_mutex);
}
static struct irq_chip irq_chip_core = {
.name = "Core",
.irq_enable = irq_core_enable,
.irq_disable = irq_core_disable,
.irq_ack = irq_core_ack,
.irq_eoi = irq_core_eoi,
.irq_bus_lock = irq_core_bus_lock,
.irq_bus_sync_unlock = irq_core_bus_sync_unlock,
.irq_cpu_online = irq_core_eoi,
.irq_cpu_offline = irq_core_ack,
.flags = IRQCHIP_ONOFFLINE_ENABLED,
};
static void __init irq_init_core(void)
{
int i;
int irq;
struct core_chip_data *cd;
/* Start with a clean slate */
clear_c0_status(ST0_IM);
clear_c0_cause(CAUSEF_IP0 | CAUSEF_IP1);
for (i = 0; i < ARRAY_SIZE(irq_core_chip_data); i++) {
cd = irq_core_chip_data + i;
cd->current_en = false;
cd->desired_en = false;
cd->bit = i;
mutex_init(&cd->core_irq_mutex);
irq = MIPS_CPU_IRQ_BASE + i;
switch (i) {
case 0: /* SW0 */
case 1: /* SW1 */
case 5: /* IP5 */
case 6: /* IP6 */
case 7: /* IP7 */
irq_set_chip_data(irq, cd);
irq_set_chip_and_handler(irq, &irq_chip_core,
handle_percpu_irq);
break;
default:
break;
}
}
}
static void __iomem *mips_irq_chip;
#define MIPS_IRQ_CHIP_NUM_BITS 0
#define MIPS_IRQ_CHIP_REGS 8
static int mips_irq_cpu_stride;
static int mips_irq_chip_reg_raw;
static int mips_irq_chip_reg_src;
static int mips_irq_chip_reg_en;
static int mips_irq_chip_reg_raw_w1s;
static int mips_irq_chip_reg_raw_w1c;
static int mips_irq_chip_reg_en_w1s;
static int mips_irq_chip_reg_en_w1c;
static void irq_pci_enable(struct irq_data *data)
{
u32 mask = 1u << data->irq;
__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1s);
}
static void irq_pci_disable(struct irq_data *data)
{
u32 mask = 1u << data->irq;
__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1c);
}
static void irq_pci_ack(struct irq_data *data)
{
}
static void irq_pci_mask(struct irq_data *data)
{
u32 mask = 1u << data->irq;
__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1c);
}
static void irq_pci_unmask(struct irq_data *data)
{
u32 mask = 1u << data->irq;
__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1s);
}
static struct irq_chip irq_chip_pci = {
.name = "PCI",
.irq_enable = irq_pci_enable,
.irq_disable = irq_pci_disable,
.irq_ack = irq_pci_ack,
.irq_mask = irq_pci_mask,
.irq_unmask = irq_pci_unmask,
};
static void irq_mbox_all(struct irq_data *data, void __iomem *base)
{
int cpu;
unsigned int mbox = data->irq - MIPS_IRQ_MBOX0;
u32 mask;
WARN_ON(mbox >= MBOX_BITS_PER_CPU);
for_each_online_cpu(cpu) {
unsigned int cpuid = cpunum_for_cpu(cpu);
mask = 1 << (cpuid * MBOX_BITS_PER_CPU + mbox);
__raw_writel(mask, base + (cpuid * mips_irq_cpu_stride));
}
}
static void irq_mbox_enable(struct irq_data *data)
{
irq_mbox_all(data, mips_irq_chip + mips_irq_chip_reg_en_w1s + sizeof(u32));
}
static void irq_mbox_disable(struct irq_data *data)
{
irq_mbox_all(data, mips_irq_chip + mips_irq_chip_reg_en_w1c + sizeof(u32));
}
static void irq_mbox_ack(struct irq_data *data)
{
u32 mask;
unsigned int mbox = data->irq - MIPS_IRQ_MBOX0;
WARN_ON(mbox >= MBOX_BITS_PER_CPU);
mask = 1 << (get_ebase_cpunum() * MBOX_BITS_PER_CPU + mbox);
__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_raw_w1c + sizeof(u32));
}
void irq_mbox_ipi(int cpu, unsigned int actions)
{
unsigned int cpuid = cpunum_for_cpu(cpu);
u32 mask;
WARN_ON(actions >= (1 << MBOX_BITS_PER_CPU));
mask = actions << (cpuid * MBOX_BITS_PER_CPU);
__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_raw_w1s + sizeof(u32));
}
static void irq_mbox_cpu_onoffline(struct irq_data *data, void __iomem *base)
{
unsigned int mbox = data->irq - MIPS_IRQ_MBOX0;
unsigned int cpuid = get_ebase_cpunum();
u32 mask;
WARN_ON(mbox >= MBOX_BITS_PER_CPU);
mask = 1 << (cpuid * MBOX_BITS_PER_CPU + mbox);
__raw_writel(mask, base + (cpuid * mips_irq_cpu_stride));
}
static void irq_mbox_cpu_online(struct irq_data *data)
{
irq_mbox_cpu_onoffline(data, mips_irq_chip + mips_irq_chip_reg_en_w1s + sizeof(u32));
}
static void irq_mbox_cpu_offline(struct irq_data *data)
{
irq_mbox_cpu_onoffline(data, mips_irq_chip + mips_irq_chip_reg_en_w1c + sizeof(u32));
}
static struct irq_chip irq_chip_mbox = {
.name = "MBOX",
.irq_enable = irq_mbox_enable,
.irq_disable = irq_mbox_disable,
.irq_ack = irq_mbox_ack,
.irq_cpu_online = irq_mbox_cpu_online,
.irq_cpu_offline = irq_mbox_cpu_offline,
.flags = IRQCHIP_ONOFFLINE_ENABLED,
};
static void __init irq_pci_init(void)
{
int i, stride;
u32 num_bits;
mips_irq_chip = ioremap(0x1e010000, 4096);
num_bits = __raw_readl(mips_irq_chip + MIPS_IRQ_CHIP_NUM_BITS);
stride = 8 * (1 + ((num_bits - 1) / 64));
pr_notice("mips_irq_chip: %u bits, reg stride: %d\n", num_bits, stride);
mips_irq_chip_reg_raw = MIPS_IRQ_CHIP_REGS + 0 * stride;
mips_irq_chip_reg_raw_w1s = MIPS_IRQ_CHIP_REGS + 1 * stride;
mips_irq_chip_reg_raw_w1c = MIPS_IRQ_CHIP_REGS + 2 * stride;
mips_irq_chip_reg_src = MIPS_IRQ_CHIP_REGS + 3 * stride;
mips_irq_chip_reg_en = MIPS_IRQ_CHIP_REGS + 4 * stride;
mips_irq_chip_reg_en_w1s = MIPS_IRQ_CHIP_REGS + 5 * stride;
mips_irq_chip_reg_en_w1c = MIPS_IRQ_CHIP_REGS + 6 * stride;
mips_irq_cpu_stride = stride * 4;
for (i = 0; i < 4; i++)
irq_set_chip_and_handler(i + MIPS_IRQ_PCIA, &irq_chip_pci, handle_level_irq);
for (i = 0; i < 2; i++)
irq_set_chip_and_handler(i + MIPS_IRQ_MBOX0, &irq_chip_mbox, handle_percpu_irq);
set_c0_status(STATUSF_IP2);
}
static void irq_pci_dispatch(void)
{
unsigned int cpuid = get_ebase_cpunum();
u32 en;
en = __raw_readl(mips_irq_chip + mips_irq_chip_reg_src +
(cpuid * mips_irq_cpu_stride));
if (!en) {
en = __raw_readl(mips_irq_chip + mips_irq_chip_reg_src + (cpuid * mips_irq_cpu_stride) + sizeof(u32));
en = (en >> (2 * cpuid)) & 3;
if (!en)
spurious_interrupt();
else
do_IRQ(__ffs(en) + MIPS_IRQ_MBOX0); /* MBOX type */
} else {
do_IRQ(__ffs(en));
}
}
void __init arch_init_irq(void)
{
irq_init_core();
irq_pci_init();
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
int ip;
if (unlikely(!pending)) {
spurious_interrupt();
return;
}
ip = ffs(pending) - 1 - STATUSB_IP0;
if (ip == 2)
irq_pci_dispatch();
else
do_IRQ(MIPS_CPU_IRQ_BASE + ip);
}
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2013 Cavium, Inc.
*/
#include <linux/interrupt.h>
#include <linux/cpumask.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/sched/task_stack.h>
#include <asm/mipsregs.h>
#include <asm/setup.h>
#include <asm/time.h>
#include <asm/smp.h>
/*
* Writing the sp releases the CPU, so writes must be ordered, gp
* first, then sp.
*/
unsigned long paravirt_smp_sp[NR_CPUS];
unsigned long paravirt_smp_gp[NR_CPUS];
static int numcpus = 1;
static int __init set_numcpus(char *str)
{
int newval;
if (get_option(&str, &newval)) {
if (newval < 1 || newval >= NR_CPUS)
goto bad;
numcpus = newval;
return 0;
}
bad:
return -EINVAL;
}
early_param("numcpus", set_numcpus);
static void paravirt_smp_setup(void)
{
int id;
unsigned int cpunum = get_ebase_cpunum();
if (WARN_ON(cpunum >= NR_CPUS))
return;
/* The present CPUs are initially just the boot cpu (CPU 0). */
for (id = 0; id < NR_CPUS; id++) {
set_cpu_possible(id, id == 0);
set_cpu_present(id, id == 0);
}
__cpu_number_map[cpunum] = 0;
__cpu_logical_map[0] = cpunum;
for (id = 0; id < numcpus; id++) {
set_cpu_possible(id, true);
set_cpu_present(id, true);
__cpu_number_map[id] = id;
__cpu_logical_map[id] = id;
}
}
void irq_mbox_ipi(int cpu, unsigned int actions);
static void paravirt_send_ipi_single(int cpu, unsigned int action)
{
irq_mbox_ipi(cpu, action);
}
static void paravirt_send_ipi_mask(const struct cpumask *mask, unsigned int action)
{
unsigned int cpu;
for_each_cpu(cpu, mask)
paravirt_send_ipi_single(cpu, action);
}
static void paravirt_init_secondary(void)
{
unsigned int sr;
sr = set_c0_status(ST0_BEV);
write_c0_ebase((u32)ebase);
sr |= STATUSF_IP2; /* Interrupt controller on IP2 */
write_c0_status(sr);
irq_cpu_online();
}
static void paravirt_smp_finish(void)
{
/* to generate the first CPU timer interrupt */
write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
local_irq_enable();
}
static int paravirt_boot_secondary(int cpu, struct task_struct *idle)
{
paravirt_smp_gp[cpu] = (unsigned long)task_thread_info(idle);
smp_wmb();
paravirt_smp_sp[cpu] = __KSTK_TOS(idle);
return 0;
}
static irqreturn_t paravirt_reched_interrupt(int irq, void *dev_id)
{
scheduler_ipi();
return IRQ_HANDLED;
}
static irqreturn_t paravirt_function_interrupt(int irq, void *dev_id)
{
generic_smp_call_function_interrupt();
return IRQ_HANDLED;
}
static void paravirt_prepare_cpus(unsigned int max_cpus)
{
if (request_irq(MIPS_IRQ_MBOX0, paravirt_reched_interrupt,
IRQF_PERCPU | IRQF_NO_THREAD, "Scheduler",
paravirt_reched_interrupt)) {
panic("Cannot request_irq for SchedulerIPI");
}
if (request_irq(MIPS_IRQ_MBOX1, paravirt_function_interrupt,
IRQF_PERCPU | IRQF_NO_THREAD, "SMP-Call",
paravirt_function_interrupt)) {
panic("Cannot request_irq for SMP-Call");
}
}
const struct plat_smp_ops paravirt_smp_ops = {
.send_ipi_single = paravirt_send_ipi_single,
.send_ipi_mask = paravirt_send_ipi_mask,
.init_secondary = paravirt_init_secondary,
.smp_finish = paravirt_smp_finish,
.boot_secondary = paravirt_boot_secondary,
.smp_setup = paravirt_smp_setup,
.prepare_cpus = paravirt_prepare_cpus,
};
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2013 Cavium, Inc.
*/
#include <linux/kernel.h>
#include <linux/virtio_console.h>
#include <linux/kvm_para.h>
#include <asm/setup.h>
/*
* Emit one character to the boot console.
*/
void prom_putchar(char c)
{
kvm_hypercall3(KVM_HC_MIPS_CONSOLE_OUTPUT, 0 /* port 0 */,
(unsigned long)&c, 1 /* len == 1 */);
}
#ifdef CONFIG_VIRTIO_CONSOLE
static int paravirt_put_chars(u32 vtermno, const char *buf, int count)
{
kvm_hypercall3(KVM_HC_MIPS_CONSOLE_OUTPUT, vtermno,
(unsigned long)buf, count);
return count;
}
static int __init paravirt_cons_init(void)
{
virtio_cons_early_init(paravirt_put_chars);
return 0;
}
core_initcall(paravirt_cons_init);
#endif
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2013 Cavium, Inc.
*/
#include <linux/kernel.h>
#include <linux/kvm_para.h>
#include <asm/reboot.h>
#include <asm/bootinfo.h>
#include <asm/smp-ops.h>
#include <asm/time.h>
extern const struct plat_smp_ops paravirt_smp_ops;
const char *get_system_type(void)
{
return "MIPS Para-Virtualized Guest";
}
void __init plat_time_init(void)
{
mips_hpt_frequency = kvm_hypercall0(KVM_HC_MIPS_GET_CLOCK_FREQ);
preset_lpj = mips_hpt_frequency / (2 * HZ);
}
static void pv_machine_halt(void)
{
kvm_hypercall0(KVM_HC_MIPS_EXIT_VM);
}
/*
* Early entry point for arch setup
*/
void __init prom_init(void)
{
int i;
int argc = fw_arg0;
char **argv = (char **)fw_arg1;
#ifdef CONFIG_32BIT
set_io_port_base(KSEG1ADDR(0x1e000000));
#else /* CONFIG_64BIT */
set_io_port_base(PHYS_TO_XKSEG_UNCACHED(0x1e000000));
#endif
for (i = 0; i < argc; i++) {
strlcat(arcs_cmdline, argv[i], COMMAND_LINE_SIZE);
if (i < argc - 1)
strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
}
_machine_halt = pv_machine_halt;
register_smp_ops(&paravirt_smp_ops);
}
void __init plat_mem_setup(void)
{
/* Do nothing, the "mem=???" parser handles our memory. */
}
void __init prom_free_prom_memory(void)
{
}
...@@ -23,7 +23,6 @@ obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o ...@@ -23,7 +23,6 @@ obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
obj-$(CONFIG_PCI_AR2315) += pci-ar2315.o obj-$(CONFIG_PCI_AR2315) += pci-ar2315.o
obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-virtio-guest.o
obj-$(CONFIG_PCI_XTALK_BRIDGE) += pci-xtalk-bridge.o obj-$(CONFIG_PCI_XTALK_BRIDGE) += pci-xtalk-bridge.o
# #
# These are still pretty much in the old state, watch, go blind. # These are still pretty much in the old state, watch, go blind.
......
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2013 Cavium, Inc.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <uapi/asm/bitfield.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#define PCI_CONFIG_ADDRESS 0xcf8
#define PCI_CONFIG_DATA 0xcfc
union pci_config_address {
struct {
__BITFIELD_FIELD(unsigned enable_bit : 1, /* 31 */
__BITFIELD_FIELD(unsigned reserved : 7, /* 30 .. 24 */
__BITFIELD_FIELD(unsigned bus_number : 8, /* 23 .. 16 */
__BITFIELD_FIELD(unsigned devfn_number : 8, /* 15 .. 8 */
__BITFIELD_FIELD(unsigned register_number : 8, /* 7 .. 0 */
)))));
};
u32 w;
};
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}
int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
return ((pin + slot) % 4)+ MIPS_IRQ_PCIA;
}
static void pci_virtio_guest_write_config_addr(struct pci_bus *bus,
unsigned int devfn, int reg)
{
union pci_config_address pca = { .w = 0 };
pca.register_number = reg;
pca.devfn_number = devfn;
pca.bus_number = bus->number;
pca.enable_bit = 1;
outl(pca.w, PCI_CONFIG_ADDRESS);
}
static int pci_virtio_guest_write_config(struct pci_bus *bus,
unsigned int devfn, int reg, int size, u32 val)
{
pci_virtio_guest_write_config_addr(bus, devfn, reg);
switch (size) {
case 1:
outb(val, PCI_CONFIG_DATA + (reg & 3));
break;
case 2:
outw(val, PCI_CONFIG_DATA + (reg & 2));
break;
case 4:
outl(val, PCI_CONFIG_DATA);
break;
}
return PCIBIOS_SUCCESSFUL;
}
static int pci_virtio_guest_read_config(struct pci_bus *bus, unsigned int devfn,
int reg, int size, u32 *val)
{
pci_virtio_guest_write_config_addr(bus, devfn, reg);
switch (size) {
case 1:
*val = inb(PCI_CONFIG_DATA + (reg & 3));
break;
case 2:
*val = inw(PCI_CONFIG_DATA + (reg & 2));
break;
case 4:
*val = inl(PCI_CONFIG_DATA);
break;
}
return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops pci_virtio_guest_ops = {
.read = pci_virtio_guest_read_config,
.write = pci_virtio_guest_write_config,
};
static struct resource pci_virtio_guest_mem_resource = {
.name = "Virtio MEM",
.flags = IORESOURCE_MEM,
.start = 0x10000000,
.end = 0x1dffffff
};
static struct resource pci_virtio_guest_io_resource = {
.name = "Virtio IO",
.flags = IORESOURCE_IO,
.start = 0,
.end = 0xffff
};
static struct pci_controller pci_virtio_guest_controller = {
.pci_ops = &pci_virtio_guest_ops,
.mem_resource = &pci_virtio_guest_mem_resource,
.io_resource = &pci_virtio_guest_io_resource,
};
static int __init pci_virtio_guest_setup(void)
{
pr_err("pci_virtio_guest_setup\n");
/* Virtio comes pre-assigned */
pci_set_flags(PCI_PROBE_ONLY);
pci_virtio_guest_controller.io_map_base = mips_io_port_base;
register_pci_controller(&pci_virtio_guest_controller);
return 0;
}
arch_initcall(pci_virtio_guest_setup);
...@@ -122,6 +122,7 @@ static void *map_vdso(const char *path, size_t *_size) ...@@ -122,6 +122,7 @@ static void *map_vdso(const char *path, size_t *_size)
if (fstat(fd, &stat) != 0) { if (fstat(fd, &stat) != 0) {
fprintf(stderr, "%s: Failed to stat '%s': %s\n", program_name, fprintf(stderr, "%s: Failed to stat '%s': %s\n", program_name,
path, strerror(errno)); path, strerror(errno));
close(fd);
return NULL; return NULL;
} }
...@@ -130,6 +131,7 @@ static void *map_vdso(const char *path, size_t *_size) ...@@ -130,6 +131,7 @@ static void *map_vdso(const char *path, size_t *_size)
if (addr == MAP_FAILED) { if (addr == MAP_FAILED) {
fprintf(stderr, "%s: Failed to map '%s': %s\n", program_name, fprintf(stderr, "%s: Failed to map '%s': %s\n", program_name,
path, strerror(errno)); path, strerror(errno));
close(fd);
return NULL; return NULL;
} }
...@@ -139,6 +141,7 @@ static void *map_vdso(const char *path, size_t *_size) ...@@ -139,6 +141,7 @@ static void *map_vdso(const char *path, size_t *_size)
if (memcmp(ehdr->e_ident, ELFMAG, SELFMAG) != 0) { if (memcmp(ehdr->e_ident, ELFMAG, SELFMAG) != 0) {
fprintf(stderr, "%s: '%s' is not an ELF file\n", program_name, fprintf(stderr, "%s: '%s' is not an ELF file\n", program_name,
path); path);
close(fd);
return NULL; return NULL;
} }
...@@ -150,6 +153,7 @@ static void *map_vdso(const char *path, size_t *_size) ...@@ -150,6 +153,7 @@ static void *map_vdso(const char *path, size_t *_size)
default: default:
fprintf(stderr, "%s: '%s' has invalid ELF class\n", fprintf(stderr, "%s: '%s' has invalid ELF class\n",
program_name, path); program_name, path);
close(fd);
return NULL; return NULL;
} }
...@@ -161,6 +165,7 @@ static void *map_vdso(const char *path, size_t *_size) ...@@ -161,6 +165,7 @@ static void *map_vdso(const char *path, size_t *_size)
default: default:
fprintf(stderr, "%s: '%s' has invalid ELF data order\n", fprintf(stderr, "%s: '%s' has invalid ELF data order\n",
program_name, path); program_name, path);
close(fd);
return NULL; return NULL;
} }
...@@ -168,15 +173,18 @@ static void *map_vdso(const char *path, size_t *_size) ...@@ -168,15 +173,18 @@ static void *map_vdso(const char *path, size_t *_size)
fprintf(stderr, fprintf(stderr,
"%s: '%s' has invalid ELF machine (expected EM_MIPS)\n", "%s: '%s' has invalid ELF machine (expected EM_MIPS)\n",
program_name, path); program_name, path);
close(fd);
return NULL; return NULL;
} else if (swap_uint16(ehdr->e_type) != ET_DYN) { } else if (swap_uint16(ehdr->e_type) != ET_DYN) {
fprintf(stderr, fprintf(stderr,
"%s: '%s' has invalid ELF type (expected ET_DYN)\n", "%s: '%s' has invalid ELF type (expected ET_DYN)\n",
program_name, path); program_name, path);
close(fd);
return NULL; return NULL;
} }
*_size = stat.st_size; *_size = stat.st_size;
close(fd);
return addr; return addr;
} }
...@@ -260,7 +268,7 @@ int main(int argc, char **argv) ...@@ -260,7 +268,7 @@ int main(int argc, char **argv)
fprintf(out_file, " if (vdso_image.size != new_size)\n"); fprintf(out_file, " if (vdso_image.size != new_size)\n");
fprintf(out_file, " return -EINVAL;\n"); fprintf(out_file, " return -EINVAL;\n");
fprintf(out_file, " current->mm->context.vdso =\n"); fprintf(out_file, " current->mm->context.vdso =\n");
fprintf(out_file, " (void __user *)(new_vma->vm_start);\n"); fprintf(out_file, " (void *)(new_vma->vm_start);\n");
fprintf(out_file, " return 0;\n"); fprintf(out_file, " return 0;\n");
fprintf(out_file, "}\n"); fprintf(out_file, "}\n");
...@@ -293,10 +301,12 @@ int main(int argc, char **argv) ...@@ -293,10 +301,12 @@ int main(int argc, char **argv)
/* Calculate and write symbol offsets to <output file> */ /* Calculate and write symbol offsets to <output file> */
if (!get_symbols(dbg_vdso_path, dbg_vdso)) { if (!get_symbols(dbg_vdso_path, dbg_vdso)) {
unlink(out_path); unlink(out_path);
fclose(out_file);
return EXIT_FAILURE; return EXIT_FAILURE;
} }
fprintf(out_file, "};\n"); fprintf(out_file, "};\n");
fclose(out_file);
return EXIT_SUCCESS; return EXIT_SUCCESS;
} }
...@@ -97,7 +97,7 @@ config IMX_WEIM ...@@ -97,7 +97,7 @@ config IMX_WEIM
config MIPS_CDMM config MIPS_CDMM
bool "MIPS Common Device Memory Map (CDMM) Driver" bool "MIPS Common Device Memory Map (CDMM) Driver"
depends on CPU_MIPSR2 depends on CPU_MIPSR2 || CPU_MIPSR5
help help
Driver needed for the MIPS Common Device Memory Map bus in MIPS Driver needed for the MIPS Common Device Memory Map bus in MIPS
cores. This bus is for per-CPU tightly coupled devices such as the cores. This bus is for per-CPU tightly coupled devices such as the
......
...@@ -13,6 +13,8 @@ ...@@ -13,6 +13,8 @@
#include <linux/cpu.h> #include <linux/cpu.h>
#include <linux/cpumask.h> #include <linux/cpumask.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/smp.h> #include <linux/smp.h>
...@@ -337,9 +339,22 @@ static phys_addr_t mips_cdmm_cur_base(void) ...@@ -337,9 +339,22 @@ static phys_addr_t mips_cdmm_cur_base(void)
* Picking a suitable physical address at which to map the CDMM region is * Picking a suitable physical address at which to map the CDMM region is
* platform specific, so this weak function can be overridden by platform * platform specific, so this weak function can be overridden by platform
* code to pick a suitable value if none is configured by the bootloader. * code to pick a suitable value if none is configured by the bootloader.
* By default this method tries to find a CDMM-specific node in the system
* dtb. Note that this won't work for early serial console.
*/ */
phys_addr_t __weak mips_cdmm_phys_base(void) phys_addr_t __weak mips_cdmm_phys_base(void)
{ {
struct device_node *np;
struct resource res;
int err;
np = of_find_compatible_node(NULL, NULL, "mti,mips-cdmm");
if (np) {
err = of_address_to_resource(np, 0, &res);
if (!err)
return res.start;
}
return 0; return 0;
} }
......
...@@ -147,7 +147,6 @@ config FSL_IFC ...@@ -147,7 +147,6 @@ config FSL_IFC
config JZ4780_NEMC config JZ4780_NEMC
bool "Ingenic JZ4780 SoC NEMC driver" bool "Ingenic JZ4780 SoC NEMC driver"
default y
depends on MIPS || COMPILE_TEST depends on MIPS || COMPILE_TEST
depends on HAS_IOMEM && OF depends on HAS_IOMEM && OF
help help
......
...@@ -49,6 +49,7 @@ struct of_bus { ...@@ -49,6 +49,7 @@ struct of_bus {
u64 (*map)(__be32 *addr, const __be32 *range, u64 (*map)(__be32 *addr, const __be32 *range,
int na, int ns, int pna); int na, int ns, int pna);
int (*translate)(__be32 *addr, u64 offset, int na); int (*translate)(__be32 *addr, u64 offset, int na);
bool has_flags;
unsigned int (*get_flags)(const __be32 *addr); unsigned int (*get_flags)(const __be32 *addr);
}; };
...@@ -100,6 +101,7 @@ static unsigned int of_bus_default_get_flags(const __be32 *addr) ...@@ -100,6 +101,7 @@ static unsigned int of_bus_default_get_flags(const __be32 *addr)
return IORESOURCE_MEM; return IORESOURCE_MEM;
} }
#ifdef CONFIG_PCI
static unsigned int of_bus_pci_get_flags(const __be32 *addr) static unsigned int of_bus_pci_get_flags(const __be32 *addr)
{ {
unsigned int flags = 0; unsigned int flags = 0;
...@@ -122,7 +124,6 @@ static unsigned int of_bus_pci_get_flags(const __be32 *addr) ...@@ -122,7 +124,6 @@ static unsigned int of_bus_pci_get_flags(const __be32 *addr)
return flags; return flags;
} }
#ifdef CONFIG_PCI
/* /*
* PCI bus specific translator * PCI bus specific translator
*/ */
...@@ -364,6 +365,7 @@ static struct of_bus of_busses[] = { ...@@ -364,6 +365,7 @@ static struct of_bus of_busses[] = {
.count_cells = of_bus_pci_count_cells, .count_cells = of_bus_pci_count_cells,
.map = of_bus_pci_map, .map = of_bus_pci_map,
.translate = of_bus_pci_translate, .translate = of_bus_pci_translate,
.has_flags = true,
.get_flags = of_bus_pci_get_flags, .get_flags = of_bus_pci_get_flags,
}, },
#endif /* CONFIG_PCI */ #endif /* CONFIG_PCI */
...@@ -375,6 +377,7 @@ static struct of_bus of_busses[] = { ...@@ -375,6 +377,7 @@ static struct of_bus of_busses[] = {
.count_cells = of_bus_isa_count_cells, .count_cells = of_bus_isa_count_cells,
.map = of_bus_isa_map, .map = of_bus_isa_map,
.translate = of_bus_isa_translate, .translate = of_bus_isa_translate,
.has_flags = true,
.get_flags = of_bus_isa_get_flags, .get_flags = of_bus_isa_get_flags,
}, },
/* Default */ /* Default */
...@@ -701,6 +704,7 @@ static int parser_init(struct of_pci_range_parser *parser, ...@@ -701,6 +704,7 @@ static int parser_init(struct of_pci_range_parser *parser,
parser->na = of_bus_n_addr_cells(node); parser->na = of_bus_n_addr_cells(node);
parser->ns = of_bus_n_size_cells(node); parser->ns = of_bus_n_size_cells(node);
parser->dma = !strcmp(name, "dma-ranges"); parser->dma = !strcmp(name, "dma-ranges");
parser->bus = of_match_bus(node);
parser->range = of_get_property(node, name, &rlen); parser->range = of_get_property(node, name, &rlen);
if (parser->range == NULL) if (parser->range == NULL)
...@@ -732,6 +736,7 @@ struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser, ...@@ -732,6 +736,7 @@ struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser,
int na = parser->na; int na = parser->na;
int ns = parser->ns; int ns = parser->ns;
int np = parser->pna + na + ns; int np = parser->pna + na + ns;
int busflag_na = 0;
if (!range) if (!range)
return NULL; return NULL;
...@@ -739,12 +744,13 @@ struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser, ...@@ -739,12 +744,13 @@ struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser,
if (!parser->range || parser->range + np > parser->end) if (!parser->range || parser->range + np > parser->end)
return NULL; return NULL;
if (parser->na == 3) range->flags = parser->bus->get_flags(parser->range);
range->flags = of_bus_pci_get_flags(parser->range);
else /* A extra cell for resource flags */
range->flags = 0; if (parser->bus->has_flags)
busflag_na = 1;
range->pci_addr = of_read_number(parser->range, na); range->bus_addr = of_read_number(parser->range + busflag_na, na - busflag_na);
if (parser->dma) if (parser->dma)
range->cpu_addr = of_translate_dma_address(parser->node, range->cpu_addr = of_translate_dma_address(parser->node,
...@@ -759,11 +765,10 @@ struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser, ...@@ -759,11 +765,10 @@ struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser,
/* Now consume following elements while they are contiguous */ /* Now consume following elements while they are contiguous */
while (parser->range + np <= parser->end) { while (parser->range + np <= parser->end) {
u32 flags = 0; u32 flags = 0;
u64 pci_addr, cpu_addr, size; u64 bus_addr, cpu_addr, size;
if (parser->na == 3) flags = parser->bus->get_flags(parser->range);
flags = of_bus_pci_get_flags(parser->range); bus_addr = of_read_number(parser->range + busflag_na, na - busflag_na);
pci_addr = of_read_number(parser->range, na);
if (parser->dma) if (parser->dma)
cpu_addr = of_translate_dma_address(parser->node, cpu_addr = of_translate_dma_address(parser->node,
parser->range + na); parser->range + na);
...@@ -774,7 +779,7 @@ struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser, ...@@ -774,7 +779,7 @@ struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser,
if (flags != range->flags) if (flags != range->flags)
break; break;
if (pci_addr != range->pci_addr + range->size || if (bus_addr != range->bus_addr + range->size ||
cpu_addr != range->cpu_addr + range->size) cpu_addr != range->cpu_addr + range->size)
break; break;
......
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
#include <loongson_hwmon.h> #include <loongson_hwmon.h>
#include <loongson_regs.h> #include <loongson_regs.h>
static int csr_temp_enable = 0; static int csr_temp_enable;
/* /*
* Loongson-3 series cpu has two sensors inside, * Loongson-3 series cpu has two sensors inside,
...@@ -44,7 +44,7 @@ int loongson3_cpu_temp(int cpu) ...@@ -44,7 +44,7 @@ int loongson3_cpu_temp(int cpu)
case PRID_REV_LOONGSON3A_R3_0: case PRID_REV_LOONGSON3A_R3_0:
case PRID_REV_LOONGSON3A_R3_1: case PRID_REV_LOONGSON3A_R3_1:
default: default:
reg = (reg & 0xffff)*731/0x4000 - 273; reg = (reg & 0xffff) * 731 / 0x4000 - 273;
break; break;
} }
...@@ -55,9 +55,7 @@ int loongson3_cpu_temp(int cpu) ...@@ -55,9 +55,7 @@ int loongson3_cpu_temp(int cpu)
static int nr_packages; static int nr_packages;
static struct device *cpu_hwmon_dev; static struct device *cpu_hwmon_dev;
static ssize_t get_hwmon_name(struct device *dev, static SENSOR_DEVICE_ATTR(name, 0444, NULL, NULL, 0);
struct device_attribute *attr, char *buf);
static SENSOR_DEVICE_ATTR(name, S_IRUGO, get_hwmon_name, NULL, 0);
static struct attribute *cpu_hwmon_attributes[] = { static struct attribute *cpu_hwmon_attributes[] = {
&sensor_dev_attr_name.dev_attr.attr, &sensor_dev_attr_name.dev_attr.attr,
...@@ -69,26 +67,19 @@ static struct attribute_group cpu_hwmon_attribute_group = { ...@@ -69,26 +67,19 @@ static struct attribute_group cpu_hwmon_attribute_group = {
.attrs = cpu_hwmon_attributes, .attrs = cpu_hwmon_attributes,
}; };
/* Hwmon device get name */
static ssize_t get_hwmon_name(struct device *dev,
struct device_attribute *attr, char *buf)
{
return sprintf(buf, "cpu-hwmon\n");
}
static ssize_t get_cpu_temp(struct device *dev, static ssize_t get_cpu_temp(struct device *dev,
struct device_attribute *attr, char *buf); struct device_attribute *attr, char *buf);
static ssize_t cpu_temp_label(struct device *dev, static ssize_t cpu_temp_label(struct device *dev,
struct device_attribute *attr, char *buf); struct device_attribute *attr, char *buf);
static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, get_cpu_temp, NULL, 1); static SENSOR_DEVICE_ATTR(temp1_input, 0444, get_cpu_temp, NULL, 1);
static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, cpu_temp_label, NULL, 1); static SENSOR_DEVICE_ATTR(temp1_label, 0444, cpu_temp_label, NULL, 1);
static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, get_cpu_temp, NULL, 2); static SENSOR_DEVICE_ATTR(temp2_input, 0444, get_cpu_temp, NULL, 2);
static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, cpu_temp_label, NULL, 2); static SENSOR_DEVICE_ATTR(temp2_label, 0444, cpu_temp_label, NULL, 2);
static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, get_cpu_temp, NULL, 3); static SENSOR_DEVICE_ATTR(temp3_input, 0444, get_cpu_temp, NULL, 3);
static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, cpu_temp_label, NULL, 3); static SENSOR_DEVICE_ATTR(temp3_label, 0444, cpu_temp_label, NULL, 3);
static SENSOR_DEVICE_ATTR(temp4_input, S_IRUGO, get_cpu_temp, NULL, 4); static SENSOR_DEVICE_ATTR(temp4_input, 0444, get_cpu_temp, NULL, 4);
static SENSOR_DEVICE_ATTR(temp4_label, S_IRUGO, cpu_temp_label, NULL, 4); static SENSOR_DEVICE_ATTR(temp4_label, 0444, cpu_temp_label, NULL, 4);
static const struct attribute *hwmon_cputemp[4][3] = { static const struct attribute *hwmon_cputemp[4][3] = {
{ {
...@@ -117,6 +108,7 @@ static ssize_t cpu_temp_label(struct device *dev, ...@@ -117,6 +108,7 @@ static ssize_t cpu_temp_label(struct device *dev,
struct device_attribute *attr, char *buf) struct device_attribute *attr, char *buf)
{ {
int id = (to_sensor_dev_attr(attr))->index - 1; int id = (to_sensor_dev_attr(attr))->index - 1;
return sprintf(buf, "CPU %d Temperature\n", id); return sprintf(buf, "CPU %d Temperature\n", id);
} }
...@@ -125,6 +117,7 @@ static ssize_t get_cpu_temp(struct device *dev, ...@@ -125,6 +117,7 @@ static ssize_t get_cpu_temp(struct device *dev,
{ {
int id = (to_sensor_dev_attr(attr))->index - 1; int id = (to_sensor_dev_attr(attr))->index - 1;
int value = loongson3_cpu_temp(id); int value = loongson3_cpu_temp(id);
return sprintf(buf, "%d\n", value); return sprintf(buf, "%d\n", value);
} }
...@@ -132,7 +125,7 @@ static int create_sysfs_cputemp_files(struct kobject *kobj) ...@@ -132,7 +125,7 @@ static int create_sysfs_cputemp_files(struct kobject *kobj)
{ {
int i, ret = 0; int i, ret = 0;
for (i=0; i<nr_packages; i++) for (i = 0; i < nr_packages; i++)
ret = sysfs_create_files(kobj, hwmon_cputemp[i]); ret = sysfs_create_files(kobj, hwmon_cputemp[i]);
return ret; return ret;
...@@ -142,7 +135,7 @@ static void remove_sysfs_cputemp_files(struct kobject *kobj) ...@@ -142,7 +135,7 @@ static void remove_sysfs_cputemp_files(struct kobject *kobj)
{ {
int i; int i;
for (i=0; i<nr_packages; i++) for (i = 0; i < nr_packages; i++)
sysfs_remove_files(kobj, hwmon_cputemp[i]); sysfs_remove_files(kobj, hwmon_cputemp[i]);
} }
...@@ -151,18 +144,17 @@ static struct delayed_work thermal_work; ...@@ -151,18 +144,17 @@ static struct delayed_work thermal_work;
static void do_thermal_timer(struct work_struct *work) static void do_thermal_timer(struct work_struct *work)
{ {
int i, value, temp_max = 0; int i, value;
for (i=0; i<nr_packages; i++) { for (i = 0; i < nr_packages; i++) {
value = loongson3_cpu_temp(i); value = loongson3_cpu_temp(i);
if (value > temp_max) if (value > CPU_THERMAL_THRESHOLD) {
temp_max = value; pr_emerg("Power off due to high temp: %d\n", value);
orderly_poweroff(true);
}
} }
if (temp_max <= CPU_THERMAL_THRESHOLD)
schedule_delayed_work(&thermal_work, msecs_to_jiffies(5000)); schedule_delayed_work(&thermal_work, msecs_to_jiffies(5000));
else
orderly_poweroff(true);
} }
static int __init loongson_hwmon_init(void) static int __init loongson_hwmon_init(void)
...@@ -172,9 +164,10 @@ static int __init loongson_hwmon_init(void) ...@@ -172,9 +164,10 @@ static int __init loongson_hwmon_init(void)
pr_info("Loongson Hwmon Enter...\n"); pr_info("Loongson Hwmon Enter...\n");
if (cpu_has_csr()) if (cpu_has_csr())
csr_temp_enable = csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_TEMP; csr_temp_enable = csr_readl(LOONGSON_CSR_FEATURES) &
LOONGSON_CSRF_TEMP;
cpu_hwmon_dev = hwmon_device_register(NULL); cpu_hwmon_dev = hwmon_device_register_with_info(NULL, "cpu_hwmon", NULL, NULL, NULL);
if (IS_ERR(cpu_hwmon_dev)) { if (IS_ERR(cpu_hwmon_dev)) {
ret = PTR_ERR(cpu_hwmon_dev); ret = PTR_ERR(cpu_hwmon_dev);
pr_err("hwmon_device_register fail!\n"); pr_err("hwmon_device_register fail!\n");
...@@ -184,13 +177,6 @@ static int __init loongson_hwmon_init(void) ...@@ -184,13 +177,6 @@ static int __init loongson_hwmon_init(void)
nr_packages = loongson_sysconf.nr_cpus / nr_packages = loongson_sysconf.nr_cpus /
loongson_sysconf.cores_per_package; loongson_sysconf.cores_per_package;
ret = sysfs_create_group(&cpu_hwmon_dev->kobj,
&cpu_hwmon_attribute_group);
if (ret) {
pr_err("fail to create loongson hwmon!\n");
goto fail_sysfs_create_group_hwmon;
}
ret = create_sysfs_cputemp_files(&cpu_hwmon_dev->kobj); ret = create_sysfs_cputemp_files(&cpu_hwmon_dev->kobj);
if (ret) { if (ret) {
pr_err("fail to create cpu temperature interface!\n"); pr_err("fail to create cpu temperature interface!\n");
...@@ -205,8 +191,6 @@ static int __init loongson_hwmon_init(void) ...@@ -205,8 +191,6 @@ static int __init loongson_hwmon_init(void)
fail_create_sysfs_cputemp_files: fail_create_sysfs_cputemp_files:
sysfs_remove_group(&cpu_hwmon_dev->kobj, sysfs_remove_group(&cpu_hwmon_dev->kobj,
&cpu_hwmon_attribute_group); &cpu_hwmon_attribute_group);
fail_sysfs_create_group_hwmon:
hwmon_device_unregister(cpu_hwmon_dev); hwmon_device_unregister(cpu_hwmon_dev);
fail_hwmon_device_register: fail_hwmon_device_register:
......
...@@ -69,7 +69,7 @@ static void acpi_hw_clear_status(void) ...@@ -69,7 +69,7 @@ static void acpi_hw_clear_status(void)
outl(inl(ACPI_GPE0_BLK), ACPI_GPE0_BLK); outl(inl(ACPI_GPE0_BLK), ACPI_GPE0_BLK);
} }
void acpi_registers_setup(void) static void acpi_registers_setup(void)
{ {
u32 value; u32 value;
......
...@@ -6,8 +6,11 @@ ...@@ -6,8 +6,11 @@
#include <linux/of.h> #include <linux/of.h>
#include <linux/io.h> #include <linux/io.h>
struct of_bus;
struct of_pci_range_parser { struct of_pci_range_parser {
struct device_node *node; struct device_node *node;
struct of_bus *bus;
const __be32 *range; const __be32 *range;
const __be32 *end; const __be32 *end;
int na; int na;
...@@ -119,6 +122,7 @@ static inline void __iomem *of_iomap(struct device_node *device, int index) ...@@ -119,6 +122,7 @@ static inline void __iomem *of_iomap(struct device_node *device, int index)
return NULL; return NULL;
} }
#endif #endif
#define of_range_parser_init of_pci_range_parser_init
#if defined(CONFIG_OF_ADDRESS) && defined(CONFIG_PCI) #if defined(CONFIG_OF_ADDRESS) && defined(CONFIG_PCI)
extern const __be32 *of_get_pci_address(struct device_node *dev, int bar_no, extern const __be32 *of_get_pci_address(struct device_node *dev, int bar_no,
......
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