Commit b682242f authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'mailbox-v5.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration

Pull mailbox updates from Jassi Brar:

 - qcom:
     - enable support for ipq8074, sm1850 and sm7180
     - add child device node for qcs404
     - misc fixes

 - mediatek:
     - enable support for mt8183
     - misc rejig of cmdq driver
     - new client-reg dt property

 - armada:
     - use device-managed registration api

* tag 'mailbox-v5.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  mailbox: qcom-apcs: fix max_register value
  mailbox: qcom: Add support for IPQ8074 APCS
  dt-bindings: mailbox: qom: Add ipq8074 APPS compatible
  mailbox: qcom: Add support for Qualcomm SM8150 and SC7180 SoCs
  dt-bindings: mailbox: Add APSS shared for SM8150 and SC7180 SoCs
  mbox: qcom: replace integer with valid macro
  mbox: qcom: add APCS child device for QCS404
  mailbox: mediatek: cmdq: clear the event in cmdq initial flow
  mailbox: mediatek: cmdq: support mt8183 gce function
  mailbox: mediatek: cmdq: move the CMDQ_IRQ_MASK into cmdq driver data
  dt-binding: gce: add binding for gce client reg property
  dt-binding: gce: add gce header file for mt8183
  dt-binding: gce: remove thread-num property
  mailbox: armada-37xx-rwtm: Use device-managed registration API
parents e3a008ac 556a0964
...@@ -9,7 +9,7 @@ CMDQ driver uses mailbox framework for communication. Please refer to ...@@ -9,7 +9,7 @@ CMDQ driver uses mailbox framework for communication. Please refer to
mailbox.txt for generic information about mailbox device-tree bindings. mailbox.txt for generic information about mailbox device-tree bindings.
Required properties: Required properties:
- compatible: Must be "mediatek,mt8173-gce" - compatible: can be "mediatek,mt8173-gce" or "mediatek,mt8183-gce"
- reg: Address range of the GCE unit - reg: Address range of the GCE unit
- interrupts: The interrupt signal from the GCE block - interrupts: The interrupt signal from the GCE block
- clock: Clocks according to the common clock binding - clock: Clocks according to the common clock binding
...@@ -25,11 +25,19 @@ Required properties: ...@@ -25,11 +25,19 @@ Required properties:
Required properties for a client device: Required properties for a client device:
- mboxes: Client use mailbox to communicate with GCE, it should have this - mboxes: Client use mailbox to communicate with GCE, it should have this
property and list of phandle, mailbox specifiers. property and list of phandle, mailbox specifiers.
- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding Optional properties for a client device:
- mediatek,gce-client-reg: Specify the sub-system id which is corresponding
to the register address, it should have this property and list of phandle,
sub-system specifiers.
<&phandle subsys_number start_offset size>
phandle: Label name of a gce node.
subsys_number: specify the sub-system id which is corresponding
to the register address. to the register address.
start_offset: the start offset of register address that GCE can access.
size: the total size of register address that GCE can access.
Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'. Such as Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'
sub-system ids, thread priority, event ids. or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids.
Example: Example:
...@@ -39,7 +47,6 @@ Example: ...@@ -39,7 +47,6 @@ Example:
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_GCE>; clocks = <&infracfg CLK_INFRA_GCE>;
clock-names = "gce"; clock-names = "gce";
thread-num = CMDQ_THR_MAX_COUNT;
#mbox-cells = <3>; #mbox-cells = <3>;
}; };
...@@ -49,9 +56,9 @@ Example for a client device: ...@@ -49,9 +56,9 @@ Example for a client device:
compatible = "mediatek,mt8173-mmsys"; compatible = "mediatek,mt8173-mmsys";
mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>, mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>,
<&gce 1 CMDQ_THR_PRIO_LOWEST 1>; <&gce 1 CMDQ_THR_PRIO_LOWEST 1>;
mediatek,gce-subsys = <SUBSYS_1400XXXX>;
mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF
CMDQ_EVENT_MUTEX1_STREAM_EOF>; CMDQ_EVENT_MUTEX1_STREAM_EOF>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>,
<&gce SUBSYS_1401XXXX 0x2000 0x100>;
... ...
}; };
...@@ -12,7 +12,10 @@ platforms. ...@@ -12,7 +12,10 @@ platforms.
"qcom,msm8996-apcs-hmss-global" "qcom,msm8996-apcs-hmss-global"
"qcom,msm8998-apcs-hmss-global" "qcom,msm8998-apcs-hmss-global"
"qcom,qcs404-apcs-apps-global" "qcom,qcs404-apcs-apps-global"
"qcom,sc7180-apss-shared"
"qcom,sdm845-apss-shared" "qcom,sdm845-apss-shared"
"qcom,sm8150-apss-shared"
"qcom,ipq8074-apcs-apps-global"
- reg: - reg:
Usage: required Usage: required
......
...@@ -180,7 +180,7 @@ static int armada_37xx_mbox_probe(struct platform_device *pdev) ...@@ -180,7 +180,7 @@ static int armada_37xx_mbox_probe(struct platform_device *pdev)
mbox->controller.ops = &a37xx_mbox_ops; mbox->controller.ops = &a37xx_mbox_ops;
mbox->controller.txdone_irq = true; mbox->controller.txdone_irq = true;
ret = mbox_controller_register(&mbox->controller); ret = devm_mbox_controller_register(mbox->dev, &mbox->controller);
if (ret) { if (ret) {
dev_err(&pdev->dev, "Could not register mailbox controller\n"); dev_err(&pdev->dev, "Could not register mailbox controller\n");
return ret; return ret;
...@@ -190,17 +190,6 @@ static int armada_37xx_mbox_probe(struct platform_device *pdev) ...@@ -190,17 +190,6 @@ static int armada_37xx_mbox_probe(struct platform_device *pdev)
return ret; return ret;
} }
static int armada_37xx_mbox_remove(struct platform_device *pdev)
{
struct a37xx_mbox *mbox = platform_get_drvdata(pdev);
if (!mbox)
return -EINVAL;
mbox_controller_unregister(&mbox->controller);
return 0;
}
static const struct of_device_id armada_37xx_mbox_match[] = { static const struct of_device_id armada_37xx_mbox_match[] = {
{ .compatible = "marvell,armada-3700-rwtm-mailbox" }, { .compatible = "marvell,armada-3700-rwtm-mailbox" },
...@@ -211,7 +200,6 @@ MODULE_DEVICE_TABLE(of, armada_37xx_mbox_match); ...@@ -211,7 +200,6 @@ MODULE_DEVICE_TABLE(of, armada_37xx_mbox_match);
static struct platform_driver armada_37xx_mbox_driver = { static struct platform_driver armada_37xx_mbox_driver = {
.probe = armada_37xx_mbox_probe, .probe = armada_37xx_mbox_probe,
.remove = armada_37xx_mbox_remove,
.driver = { .driver = {
.name = DRIVER_NAME, .name = DRIVER_NAME,
.of_match_table = armada_37xx_mbox_match, .of_match_table = armada_37xx_mbox_match,
......
...@@ -18,10 +18,10 @@ ...@@ -18,10 +18,10 @@
#include <linux/of_device.h> #include <linux/of_device.h>
#define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT) #define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT)
#define CMDQ_IRQ_MASK 0xffff
#define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE) #define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE)
#define CMDQ_CURR_IRQ_STATUS 0x10 #define CMDQ_CURR_IRQ_STATUS 0x10
#define CMDQ_SYNC_TOKEN_UPDATE 0x68
#define CMDQ_THR_SLOT_CYCLES 0x30 #define CMDQ_THR_SLOT_CYCLES 0x30
#define CMDQ_THR_BASE 0x100 #define CMDQ_THR_BASE 0x100
#define CMDQ_THR_SIZE 0x80 #define CMDQ_THR_SIZE 0x80
...@@ -72,6 +72,7 @@ struct cmdq { ...@@ -72,6 +72,7 @@ struct cmdq {
void __iomem *base; void __iomem *base;
u32 irq; u32 irq;
u32 thread_nr; u32 thread_nr;
u32 irq_mask;
struct cmdq_thread *thread; struct cmdq_thread *thread;
struct clk *clock; struct clk *clock;
bool suspended; bool suspended;
...@@ -104,8 +105,12 @@ static void cmdq_thread_resume(struct cmdq_thread *thread) ...@@ -104,8 +105,12 @@ static void cmdq_thread_resume(struct cmdq_thread *thread)
static void cmdq_init(struct cmdq *cmdq) static void cmdq_init(struct cmdq *cmdq)
{ {
int i;
WARN_ON(clk_enable(cmdq->clock) < 0); WARN_ON(clk_enable(cmdq->clock) < 0);
writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
for (i = 0; i <= CMDQ_MAX_EVENT; i++)
writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
clk_disable(cmdq->clock); clk_disable(cmdq->clock);
} }
...@@ -285,11 +290,11 @@ static irqreturn_t cmdq_irq_handler(int irq, void *dev) ...@@ -285,11 +290,11 @@ static irqreturn_t cmdq_irq_handler(int irq, void *dev)
unsigned long irq_status, flags = 0L; unsigned long irq_status, flags = 0L;
int bit; int bit;
irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & CMDQ_IRQ_MASK; irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask;
if (!(irq_status ^ CMDQ_IRQ_MASK)) if (!(irq_status ^ cmdq->irq_mask))
return IRQ_NONE; return IRQ_NONE;
for_each_clear_bit(bit, &irq_status, fls(CMDQ_IRQ_MASK)) { for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) {
struct cmdq_thread *thread = &cmdq->thread[bit]; struct cmdq_thread *thread = &cmdq->thread[bit];
spin_lock_irqsave(&thread->chan->lock, flags); spin_lock_irqsave(&thread->chan->lock, flags);
...@@ -473,6 +478,9 @@ static int cmdq_probe(struct platform_device *pdev) ...@@ -473,6 +478,9 @@ static int cmdq_probe(struct platform_device *pdev)
dev_err(dev, "failed to get irq\n"); dev_err(dev, "failed to get irq\n");
return -EINVAL; return -EINVAL;
} }
cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
"mtk_cmdq", cmdq); "mtk_cmdq", cmdq);
if (err < 0) { if (err < 0) {
...@@ -489,7 +497,6 @@ static int cmdq_probe(struct platform_device *pdev) ...@@ -489,7 +497,6 @@ static int cmdq_probe(struct platform_device *pdev)
return PTR_ERR(cmdq->clock); return PTR_ERR(cmdq->clock);
} }
cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
cmdq->mbox.dev = dev; cmdq->mbox.dev = dev;
cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr, cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr,
sizeof(*cmdq->mbox.chans), GFP_KERNEL); sizeof(*cmdq->mbox.chans), GFP_KERNEL);
...@@ -537,6 +544,7 @@ static const struct dev_pm_ops cmdq_pm_ops = { ...@@ -537,6 +544,7 @@ static const struct dev_pm_ops cmdq_pm_ops = {
static const struct of_device_id cmdq_of_ids[] = { static const struct of_device_id cmdq_of_ids[] = {
{.compatible = "mediatek,mt8173-gce", .data = (void *)16}, {.compatible = "mediatek,mt8173-gce", .data = (void *)16},
{.compatible = "mediatek,mt8183-gce", .data = (void *)24},
{} {}
}; };
......
...@@ -28,7 +28,7 @@ static const struct regmap_config apcs_regmap_config = { ...@@ -28,7 +28,7 @@ static const struct regmap_config apcs_regmap_config = {
.reg_bits = 32, .reg_bits = 32,
.reg_stride = 4, .reg_stride = 4,
.val_bits = 32, .val_bits = 32,
.max_register = 0x1000, .max_register = 0xFFC,
.fast_io = true, .fast_io = true,
}; };
...@@ -47,7 +47,6 @@ static const struct mbox_chan_ops qcom_apcs_ipc_ops = { ...@@ -47,7 +47,6 @@ static const struct mbox_chan_ops qcom_apcs_ipc_ops = {
static int qcom_apcs_ipc_probe(struct platform_device *pdev) static int qcom_apcs_ipc_probe(struct platform_device *pdev)
{ {
struct device_node *np = pdev->dev.of_node;
struct qcom_apcs_ipc *apcs; struct qcom_apcs_ipc *apcs;
struct regmap *regmap; struct regmap *regmap;
struct resource *res; struct resource *res;
...@@ -55,6 +54,11 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev) ...@@ -55,6 +54,11 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
void __iomem *base; void __iomem *base;
unsigned long i; unsigned long i;
int ret; int ret;
const struct of_device_id apcs_clk_match_table[] = {
{ .compatible = "qcom,msm8916-apcs-kpss-global", },
{ .compatible = "qcom,qcs404-apcs-apps-global", },
{}
};
apcs = devm_kzalloc(&pdev->dev, sizeof(*apcs), GFP_KERNEL); apcs = devm_kzalloc(&pdev->dev, sizeof(*apcs), GFP_KERNEL);
if (!apcs) if (!apcs)
...@@ -89,10 +93,11 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev) ...@@ -89,10 +93,11 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
return ret; return ret;
} }
if (of_device_is_compatible(np, "qcom,msm8916-apcs-kpss-global")) { if (of_match_device(apcs_clk_match_table, &pdev->dev)) {
apcs->clk = platform_device_register_data(&pdev->dev, apcs->clk = platform_device_register_data(&pdev->dev,
"qcom-apcs-msm8916-clk", "qcom-apcs-msm8916-clk",
-1, NULL, 0); PLATFORM_DEVID_NONE,
NULL, 0);
if (IS_ERR(apcs->clk)) if (IS_ERR(apcs->clk))
dev_err(&pdev->dev, "failed to register APCS clk\n"); dev_err(&pdev->dev, "failed to register APCS clk\n");
} }
...@@ -118,7 +123,10 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { ...@@ -118,7 +123,10 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = {
{ .compatible = "qcom,msm8996-apcs-hmss-global", .data = (void *)16 }, { .compatible = "qcom,msm8996-apcs-hmss-global", .data = (void *)16 },
{ .compatible = "qcom,msm8998-apcs-hmss-global", .data = (void *)8 }, { .compatible = "qcom,msm8998-apcs-hmss-global", .data = (void *)8 },
{ .compatible = "qcom,qcs404-apcs-apps-global", .data = (void *)8 }, { .compatible = "qcom,qcs404-apcs-apps-global", .data = (void *)8 },
{ .compatible = "qcom,sc7180-apss-shared", .data = (void *)12 },
{ .compatible = "qcom,sdm845-apss-shared", .data = (void *)12 }, { .compatible = "qcom,sdm845-apss-shared", .data = (void *)12 },
{ .compatible = "qcom,sm8150-apss-shared", .data = (void *)12 },
{ .compatible = "qcom,ipq8074-apcs-apps-global", .data = (void *)8 },
{} {}
}; };
MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match); MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
......
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Bibby Hsieh <bibby.hsieh@mediatek.com>
*
*/
#ifndef _DT_BINDINGS_GCE_MT8183_H
#define _DT_BINDINGS_GCE_MT8183_H
#define CMDQ_NO_TIMEOUT 0xffffffff
/* GCE HW thread priority */
#define CMDQ_THR_PRIO_LOWEST 0
#define CMDQ_THR_PRIO_HIGHEST 1
/* GCE SUBSYS */
#define SUBSYS_1300XXXX 0
#define SUBSYS_1400XXXX 1
#define SUBSYS_1401XXXX 2
#define SUBSYS_1402XXXX 3
#define SUBSYS_1502XXXX 4
#define SUBSYS_1880XXXX 5
#define SUBSYS_1881XXXX 6
#define SUBSYS_1882XXXX 7
#define SUBSYS_1883XXXX 8
#define SUBSYS_1884XXXX 9
#define SUBSYS_1000XXXX 10
#define SUBSYS_1001XXXX 11
#define SUBSYS_1002XXXX 12
#define SUBSYS_1003XXXX 13
#define SUBSYS_1004XXXX 14
#define SUBSYS_1005XXXX 15
#define SUBSYS_1020XXXX 16
#define SUBSYS_1028XXXX 17
#define SUBSYS_1700XXXX 18
#define SUBSYS_1701XXXX 19
#define SUBSYS_1702XXXX 20
#define SUBSYS_1703XXXX 21
#define SUBSYS_1800XXXX 22
#define SUBSYS_1801XXXX 23
#define SUBSYS_1802XXXX 24
#define SUBSYS_1804XXXX 25
#define SUBSYS_1805XXXX 26
#define SUBSYS_1808XXXX 27
#define SUBSYS_180aXXXX 28
#define SUBSYS_180bXXXX 29
#define CMDQ_EVENT_DISP_RDMA0_SOF 0
#define CMDQ_EVENT_DISP_RDMA1_SOF 1
#define CMDQ_EVENT_MDP_RDMA0_SOF 2
#define CMDQ_EVENT_MDP_RSZ0_SOF 4
#define CMDQ_EVENT_MDP_RSZ1_SOF 5
#define CMDQ_EVENT_MDP_TDSHP_SOF 6
#define CMDQ_EVENT_MDP_WROT0_SOF 7
#define CMDQ_EVENT_MDP_WDMA0_SOF 8
#define CMDQ_EVENT_DISP_OVL0_SOF 9
#define CMDQ_EVENT_DISP_OVL0_2L_SOF 10
#define CMDQ_EVENT_DISP_OVL1_2L_SOF 11
#define CMDQ_EVENT_DISP_WDMA0_SOF 12
#define CMDQ_EVENT_DISP_COLOR0_SOF 13
#define CMDQ_EVENT_DISP_CCORR0_SOF 14
#define CMDQ_EVENT_DISP_AAL0_SOF 15
#define CMDQ_EVENT_DISP_GAMMA0_SOF 16
#define CMDQ_EVENT_DISP_DITHER0_SOF 17
#define CMDQ_EVENT_DISP_PWM0_SOF 18
#define CMDQ_EVENT_DISP_DSI0_SOF 19
#define CMDQ_EVENT_DISP_DPI0_SOF 20
#define CMDQ_EVENT_DISP_RSZ_SOF 22
#define CMDQ_EVENT_MDP_AAL_SOF 23
#define CMDQ_EVENT_MDP_CCORR_SOF 24
#define CMDQ_EVENT_DISP_DBI_SOF 25
#define CMDQ_EVENT_DISP_RDMA0_EOF 26
#define CMDQ_EVENT_DISP_RDMA1_EOF 27
#define CMDQ_EVENT_MDP_RDMA0_EOF 28
#define CMDQ_EVENT_MDP_RSZ0_EOF 30
#define CMDQ_EVENT_MDP_RSZ1_EOF 31
#define CMDQ_EVENT_MDP_TDSHP_EOF 32
#define CMDQ_EVENT_MDP_WROT0_EOF 33
#define CMDQ_EVENT_MDP_WDMA0_EOF 34
#define CMDQ_EVENT_DISP_OVL0_EOF 35
#define CMDQ_EVENT_DISP_OVL0_2L_EOF 36
#define CMDQ_EVENT_DISP_OVL1_2L_EOF 37
#define CMDQ_EVENT_DISP_WDMA0_EOF 38
#define CMDQ_EVENT_DISP_COLOR0_EOF 39
#define CMDQ_EVENT_DISP_CCORR0_EOF 40
#define CMDQ_EVENT_DISP_AAL0_EOF 41
#define CMDQ_EVENT_DISP_GAMMA0_EOF 42
#define CMDQ_EVENT_DISP_DITHER0_EOF 43
#define CMDQ_EVENT_DSI0_EOF 44
#define CMDQ_EVENT_DPI0_EOF 45
#define CMDQ_EVENT_DISP_RSZ_EOF 47
#define CMDQ_EVENT_MDP_AAL_EOF 48
#define CMDQ_EVENT_MDP_CCORR_EOF 49
#define CMDQ_EVENT_DBI_EOF 50
#define CMDQ_EVENT_MUTEX_STREAM_DONE0 130
#define CMDQ_EVENT_MUTEX_STREAM_DONE1 131
#define CMDQ_EVENT_MUTEX_STREAM_DONE2 132
#define CMDQ_EVENT_MUTEX_STREAM_DONE3 133
#define CMDQ_EVENT_MUTEX_STREAM_DONE4 134
#define CMDQ_EVENT_MUTEX_STREAM_DONE5 135
#define CMDQ_EVENT_MUTEX_STREAM_DONE6 136
#define CMDQ_EVENT_MUTEX_STREAM_DONE7 137
#define CMDQ_EVENT_MUTEX_STREAM_DONE8 138
#define CMDQ_EVENT_MUTEX_STREAM_DONE9 139
#define CMDQ_EVENT_MUTEX_STREAM_DONE10 140
#define CMDQ_EVENT_MUTEX_STREAM_DONE11 141
#define CMDQ_EVENT_DISP_RDMA0_BUF_UNDERRUN_EVEN 142
#define CMDQ_EVENT_DISP_RDMA1_BUF_UNDERRUN_EVEN 143
#define CMDQ_EVENT_DSI0_TE_EVENT 144
#define CMDQ_EVENT_DSI0_IRQ_EVENT 145
#define CMDQ_EVENT_DSI0_DONE_EVENT 146
#define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE 150
#define CMDQ_EVENT_MDP_WDMA_SW_RST_DONE 151
#define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE 152
#define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE 154
#define CMDQ_EVENT_DISP_OVL0_FRAME_RST_DONE_PULE 155
#define CMDQ_EVENT_DISP_OVL0_2L_FRAME_RST_DONE_ULSE 156
#define CMDQ_EVENT_DISP_OVL1_2L_FRAME_RST_DONE_ULSE 157
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_0 257
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_1 258
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_2 259
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_3 260
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_4 261
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_5 262
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_6 263
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_7 264
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_8 265
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_9 266
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_10 267
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_11 268
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_12 269
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_13 270
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_14 271
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_15 272
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_16 273
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_17 274
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_18 275
#define CMDQ_EVENT_AMD_FRAME_DONE 276
#define CMDQ_EVENT_DVE_DONE 277
#define CMDQ_EVENT_WMFE_DONE 278
#define CMDQ_EVENT_RSC_DONE 279
#define CMDQ_EVENT_MFB_DONE 280
#define CMDQ_EVENT_WPE_A_DONE 281
#define CMDQ_EVENT_SPE_B_DONE 282
#define CMDQ_EVENT_OCC_DONE 283
#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 289
#define CMDQ_EVENT_JPG_ENC_CMDQ_DONE 290
#define CMDQ_EVENT_JPG_DEC_CMDQ_DONE 291
#define CMDQ_EVENT_VENC_CMDQ_MB_DONE 292
#define CMDQ_EVENT_VENC_CMDQ_128BYTE_DONE 293
#define CMDQ_EVENT_ISP_FRAME_DONE_A 321
#define CMDQ_EVENT_ISP_FRAME_DONE_B 322
#define CMDQ_EVENT_CAMSV0_PASS1_DONE 323
#define CMDQ_EVENT_CAMSV1_PASS1_DONE 324
#define CMDQ_EVENT_CAMSV2_PASS1_DONE 325
#define CMDQ_EVENT_TSF_DONE 326
#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 327
#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 328
#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 329
#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 330
#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 331
#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 332
#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 333
#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 334
#define CMDQ_EVENT_IPU_CORE0_DONE0 353
#define CMDQ_EVENT_IPU_CORE0_DONE1 354
#define CMDQ_EVENT_IPU_CORE0_DONE2 355
#define CMDQ_EVENT_IPU_CORE0_DONE3 356
#define CMDQ_EVENT_IPU_CORE1_DONE0 385
#define CMDQ_EVENT_IPU_CORE1_DONE1 386
#define CMDQ_EVENT_IPU_CORE1_DONE2 387
#define CMDQ_EVENT_IPU_CORE1_DONE3 388
#endif
...@@ -20,6 +20,9 @@ ...@@ -20,6 +20,9 @@
#define CMDQ_WFE_WAIT BIT(15) #define CMDQ_WFE_WAIT BIT(15)
#define CMDQ_WFE_WAIT_VALUE 0x1 #define CMDQ_WFE_WAIT_VALUE 0x1
/** cmdq event maximum */
#define CMDQ_MAX_EVENT 0x3ff
/* /*
* CMDQ_CODE_MASK: * CMDQ_CODE_MASK:
* set write mask * set write mask
......
...@@ -13,9 +13,6 @@ ...@@ -13,9 +13,6 @@
#define CMDQ_NO_TIMEOUT 0xffffffffu #define CMDQ_NO_TIMEOUT 0xffffffffu
/** cmdq event maximum */
#define CMDQ_MAX_EVENT 0x3ff
struct cmdq_pkt; struct cmdq_pkt;
struct cmdq_client { struct cmdq_client {
......
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