Commit b7dfee24 authored by Marek Vasut's avatar Marek Vasut Committed by Philipp Zabel

gpu: ipu-v3: Fix CSI selection for VDIC

The description of the CSI_SEL bit in the i.MX6 reference manual is
incorrect. It states "This bit defines which CSI is the input to the
IC. This bit is effective only if IC_INPUT is bit cleared".

From experiment it was found this is in fact not correct. The CSI_SEL
bit selects which CSI is input to _both_ the VDIC _and_ the IC. If the
IC_INPUT bit is set so that the IC is receiving from the VDIC, the IC
ignores the CSI_SEL bit, but CSI_SEL still selects which CSI the VDIC
receives from in that case.
Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Signed-off-by: default avatarSteve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
parent e36aecba
...@@ -725,15 +725,16 @@ void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi) ...@@ -725,15 +725,16 @@ void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
spin_lock_irqsave(&ipu->lock, flags); spin_lock_irqsave(&ipu->lock, flags);
val = ipu_cm_read(ipu, IPU_CONF); val = ipu_cm_read(ipu, IPU_CONF);
if (vdi) { if (vdi)
val |= IPU_CONF_IC_INPUT; val |= IPU_CONF_IC_INPUT;
} else { else
val &= ~IPU_CONF_IC_INPUT; val &= ~IPU_CONF_IC_INPUT;
if (csi_id == 1) if (csi_id == 1)
val |= IPU_CONF_CSI_SEL; val |= IPU_CONF_CSI_SEL;
else else
val &= ~IPU_CONF_CSI_SEL; val &= ~IPU_CONF_CSI_SEL;
}
ipu_cm_write(ipu, val, IPU_CONF); ipu_cm_write(ipu, val, IPU_CONF);
spin_unlock_irqrestore(&ipu->lock, flags); spin_unlock_irqrestore(&ipu->lock, flags);
......
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