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Commit b99b64df authored by Kumar Gala's avatar Kumar Gala Committed by Linus Torvalds
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[PATCH] ppc32: add performance counters to cpu_spec 

Adds the number of performance monitor counters each PowerPC processor has
to the cpu table.  Makes oprofile support a bit cleaner since we dont need
a case statement on processor version to determine the number of counters.
Signed-off-by: default avatarKumar Gala <kumar.gala@freescale.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 8d62a3ff
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Showing with 865 additions and 530 deletions
arch/ppc/kernel/cputable.c
View file @ b99b64df
...@@ -48,12 +48,21 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe ...@@ -48,12 +48,21 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe
*/ */
#ifdef CONFIG_ALTIVEC #ifdef CONFIG_ALTIVEC
#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
#define PPC_FEATURE_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC #define PPC_FEATURE_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
#else #else
#define CPU_FTR_ALTIVEC_COMP 0 #define CPU_FTR_ALTIVEC_COMP 0
#define PPC_FEATURE_ALTIVEC_COMP 0 #define PPC_FEATURE_ALTIVEC_COMP 0
#endif #endif
/* We only set the spe features if the kernel was compiled with
* spe support
*/
#ifdef CONFIG_SPE
#define PPC_FEATURE_SPE_COMP PPC_FEATURE_HAS_SPE
#else
#define PPC_FEATURE_SPE_COMP 0
#endif
/* We need to mark all pages as being coherent if we're SMP or we /* We need to mark all pages as being coherent if we're SMP or we
* have a 74[45]x and an MPC107 host bridge. * have a 74[45]x and an MPC107 host bridge.
*/ */
...@@ -76,555 +85,875 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe ...@@ -76,555 +85,875 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe
struct cpu_spec cpu_specs[] = { struct cpu_spec cpu_specs[] = {
#if CLASSIC_PPC #if CLASSIC_PPC
{ /* 601 */ { /* 601 */
0xffff0000, 0x00010000, "601", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x00010000,
CPU_FTR_601 | CPU_FTR_HPTE_TABLE, .cpu_name = "601",
COMMON_PPC | PPC_FEATURE_601_INSTR | PPC_FEATURE_UNIFIED_CACHE, .cpu_features = CPU_FTR_COMMON | CPU_FTR_601 |
32, 32, CPU_FTR_HPTE_TABLE,
__setup_cpu_601 .cpu_user_features = COMMON_PPC | PPC_FEATURE_601_INSTR |
}, PPC_FEATURE_UNIFIED_CACHE,
{ /* 603 */ .icache_bsize = 32,
0xffff0000, 0x00030000, "603", .dcache_bsize = 32,
CPU_FTR_COMMON | .num_pmcs = 0,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_setup = __setup_cpu_601
CPU_FTR_MAYBE_CAN_NAP, },
COMMON_PPC, { /* 603 */
32, 32, .pvr_mask = 0xffff0000,
__setup_cpu_603 .pvr_value = 0x00030000,
}, .cpu_name = "603",
{ /* 603e */ .cpu_features = CPU_FTR_COMMON |
0xffff0000, 0x00060000, "603e", CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
CPU_FTR_COMMON | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_user_features = COMMON_PPC,
CPU_FTR_MAYBE_CAN_NAP, .icache_bsize = 32,
COMMON_PPC, .dcache_bsize = 32,
32, 32, .num_pmcs = 0,
__setup_cpu_603 .cpu_setup = __setup_cpu_603
}, },
{ /* 603ev */ { /* 603e */
0xffff0000, 0x00070000, "603ev", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x00060000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_name = "603e",
CPU_FTR_MAYBE_CAN_NAP, .cpu_features = CPU_FTR_COMMON |
COMMON_PPC, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
32, 32, CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
__setup_cpu_603 .cpu_user_features = COMMON_PPC,
}, .icache_bsize = 32,
{ /* 604 */ .dcache_bsize = 32,
0xffff0000, 0x00040000, "604", .num_pmcs = 0,
CPU_FTR_COMMON | .cpu_setup = __setup_cpu_603
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | },
CPU_FTR_HPTE_TABLE, { /* 603ev */
COMMON_PPC, .pvr_mask = 0xffff0000,
32, 32, .pvr_value = 0x00070000,
__setup_cpu_604 .cpu_name = "603ev",
}, .cpu_features = CPU_FTR_COMMON |
{ /* 604e */ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
0xfffff000, 0x00090000, "604e", CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
CPU_FTR_COMMON | .cpu_user_features = COMMON_PPC,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | .icache_bsize = 32,
CPU_FTR_HPTE_TABLE, .dcache_bsize = 32,
COMMON_PPC, .num_pmcs = 0,
32, 32, .cpu_setup = __setup_cpu_603
__setup_cpu_604 },
}, { /* 604 */
{ /* 604r */ .pvr_mask = 0xffff0000,
0xffff0000, 0x00090000, "604r", .pvr_value = 0x00040000,
CPU_FTR_COMMON | .cpu_name = "604",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_HPTE_TABLE, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
COMMON_PPC, CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
32, 32, .cpu_user_features = COMMON_PPC,
__setup_cpu_604 .icache_bsize = 32,
}, .dcache_bsize = 32,
{ /* 604ev */ .num_pmcs = 2,
0xffff0000, 0x000a0000, "604ev", .cpu_setup = __setup_cpu_604
CPU_FTR_COMMON | },
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | { /* 604e */
CPU_FTR_HPTE_TABLE, .pvr_mask = 0xfffff000,
COMMON_PPC, .pvr_value = 0x00090000,
32, 32, .cpu_name = "604e",
__setup_cpu_604 .cpu_features = CPU_FTR_COMMON |
}, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
{ /* 740/750 (0x4202, don't support TAU ?) */ CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
0xffffffff, 0x00084202, "740/750", .cpu_user_features = COMMON_PPC,
CPU_FTR_COMMON | .icache_bsize = 32,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .dcache_bsize = 32,
CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, .num_pmcs = 4,
COMMON_PPC, .cpu_setup = __setup_cpu_604
32, 32, },
__setup_cpu_750 { /* 604r */
}, .pvr_mask = 0xffff0000,
{ /* 745/755 */ .pvr_value = 0x00090000,
0xfffff000, 0x00083000, "745/755", .cpu_name = "604r",
CPU_FTR_COMMON | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
COMMON_PPC, .cpu_user_features = COMMON_PPC,
32, 32, .icache_bsize = 32,
__setup_cpu_750 .dcache_bsize = 32,
}, .num_pmcs = 4,
{ /* 750CX (80100 and 8010x?) */ .cpu_setup = __setup_cpu_604
0xfffffff0, 0x00080100, "750CX", },
CPU_FTR_COMMON | { /* 604ev */
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .pvr_mask = 0xffff0000,
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, .pvr_value = 0x000a0000,
COMMON_PPC, .cpu_name = "604ev",
32, 32, .cpu_features = CPU_FTR_COMMON |
__setup_cpu_750cx CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
}, CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
{ /* 750CX (82201 and 82202) */ .cpu_user_features = COMMON_PPC,
0xfffffff0, 0x00082200, "750CX", .icache_bsize = 32,
CPU_FTR_COMMON | .dcache_bsize = 32,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .num_pmcs = 4,
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, .cpu_setup = __setup_cpu_604
COMMON_PPC, },
32, 32, { /* 740/750 (0x4202, don't support TAU ?) */
__setup_cpu_750cx .pvr_mask = 0xffffffff,
}, .pvr_value = 0x00084202,
{ /* 750CXe (82214) */ .cpu_name = "740/750",
0xfffffff0, 0x00082210, "750CXe", .cpu_features = CPU_FTR_COMMON |
CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, CPU_FTR_MAYBE_CAN_NAP,
COMMON_PPC, .cpu_user_features = COMMON_PPC,
32, 32, .icache_bsize = 32,
__setup_cpu_750cx .dcache_bsize = 32,
}, .num_pmcs = 4,
{ /* 750FX rev 1.x */ .cpu_setup = __setup_cpu_750
0xffffff00, 0x70000100, "750FX", },
CPU_FTR_COMMON | { /* 745/755 */
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .pvr_mask = 0xfffff000,
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | .pvr_value = 0x00083000,
CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM, .cpu_name = "745/755",
COMMON_PPC, .cpu_features = CPU_FTR_COMMON |
32, 32, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
__setup_cpu_750 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
}, CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
{ /* 750FX rev 2.0 must disable HID0[DPM] */ .cpu_user_features = COMMON_PPC,
0xffffffff, 0x70000200, "750FX", .icache_bsize = 32,
CPU_FTR_COMMON | .dcache_bsize = 32,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .num_pmcs = 4,
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | .cpu_setup = __setup_cpu_750
CPU_FTR_NO_DPM, },
COMMON_PPC, { /* 750CX (80100 and 8010x?) */
32, 32, .pvr_mask = 0xfffffff0,
__setup_cpu_750 .pvr_value = 0x00080100,
}, .cpu_name = "750CX",
{ /* 750FX (All revs except 2.0) */ .cpu_features = CPU_FTR_COMMON |
0xffff0000, 0x70000000, "750FX", CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
CPU_FTR_COMMON | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | .cpu_user_features = COMMON_PPC,
CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS, .icache_bsize = 32,
COMMON_PPC, .dcache_bsize = 32,
32, 32, .num_pmcs = 4,
__setup_cpu_750fx .cpu_setup = __setup_cpu_750cx
}, },
{ /* 750GX */ { /* 750CX (82201 and 82202) */
0xffff0000, 0x70020000, "750GX", .pvr_mask = 0xfffffff0,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .pvr_value = 0x00082200,
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | .cpu_name = "750CX",
CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS, .cpu_features = CPU_FTR_COMMON |
COMMON_PPC, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
32, 32, CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
__setup_cpu_750fx CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
}, .cpu_user_features = COMMON_PPC,
{ /* 740/750 (L2CR bit need fixup for 740) */ .icache_bsize = 32,
0xffff0000, 0x00080000, "740/750", .dcache_bsize = 32,
CPU_FTR_COMMON | .num_pmcs = 4,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_setup = __setup_cpu_750cx
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, },
COMMON_PPC, { /* 750CXe (82214) */
32, 32, .pvr_mask = 0xfffffff0,
__setup_cpu_750 .pvr_value = 0x00082210,
}, .cpu_name = "750CXe",
{ /* 7400 rev 1.1 ? (no TAU) */ .cpu_features = CPU_FTR_COMMON |
0xffffffff, 0x000c1101, "7400 (1.1)", CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
CPU_FTR_COMMON | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | .cpu_user_features = COMMON_PPC,
CPU_FTR_MAYBE_CAN_NAP, .icache_bsize = 32,
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, .dcache_bsize = 32,
32, 32, .num_pmcs = 4,
__setup_cpu_7400 .cpu_setup = __setup_cpu_750cx
}, },
{ /* 7400 */ { /* 750FX rev 1.x */
0xffff0000, 0x000c0000, "7400", .pvr_mask = 0xffffff00,
CPU_FTR_COMMON | .pvr_value = 0x70000100,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_name = "750FX",
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_MAYBE_CAN_NAP, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
32, 32, CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
__setup_cpu_7400 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
}, .cpu_user_features = COMMON_PPC,
{ /* 7410 */ .icache_bsize = 32,
0xffff0000, 0x800c0000, "7410", .dcache_bsize = 32,
CPU_FTR_COMMON | .num_pmcs = 4,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_setup = __setup_cpu_750
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | },
CPU_FTR_MAYBE_CAN_NAP, { /* 750FX rev 2.0 must disable HID0[DPM] */
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, .pvr_mask = 0xffffffff,
32, 32, .pvr_value = 0x70000200,
__setup_cpu_7410 .cpu_name = "750FX",
}, .cpu_features = CPU_FTR_COMMON |
{ /* 7450 2.0 - no doze/nap */ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
0xffffffff, 0x80000200, "7450", CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
CPU_FTR_COMMON | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_NO_DPM,
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | .cpu_user_features = COMMON_PPC,
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT, .icache_bsize = 32,
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, .dcache_bsize = 32,
32, 32, .num_pmcs = 4,
__setup_cpu_745x .cpu_setup = __setup_cpu_750
}, },
{ /* 7450 2.1 */ { /* 750FX (All revs except 2.0) */
0xffffffff, 0x80000201, "7450", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x70000000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | .cpu_name = "750FX",
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT, CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
32, 32, CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
__setup_cpu_745x .cpu_user_features = COMMON_PPC,
}, .icache_bsize = 32,
{ /* 7450 2.3 and newer */ .dcache_bsize = 32,
0xffff0000, 0x80000000, "7450", .num_pmcs = 4,
CPU_FTR_COMMON | .cpu_setup = __setup_cpu_750fx
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | },
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | { /* 750GX */
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | .pvr_mask = 0xffff0000,
CPU_FTR_NEED_COHERENT, .pvr_value = 0x70020000,
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, .cpu_name = "750GX",
32, 32, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
__setup_cpu_745x CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
}, CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE |
{ /* 7455 rev 1.x */ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_DUAL_PLL_750FX |
0xffffff00, 0x80010100, "7455", CPU_FTR_HAS_HIGH_BATS,
CPU_FTR_COMMON | .cpu_user_features = COMMON_PPC,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | .icache_bsize = 32,
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | .dcache_bsize = 32,
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | .num_pmcs = 4,
CPU_FTR_NEED_COHERENT, .cpu_setup = __setup_cpu_750fx
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, },
32, 32, { /* 740/750 (L2CR bit need fixup for 740) */
__setup_cpu_745x .pvr_mask = 0xffff0000,
}, .pvr_value = 0x00080000,
{ /* 7455 rev 2.0 */ .cpu_name = "740/750",
0xffffffff, 0x80010200, "7455", .cpu_features = CPU_FTR_COMMON |
CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | .cpu_user_features = COMMON_PPC,
CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS, .icache_bsize = 32,
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, .dcache_bsize = 32,
32, 32, .num_pmcs = 4,
__setup_cpu_745x .cpu_setup = __setup_cpu_750
}, },
{ /* 7455 others */ { /* 7400 rev 1.1 ? (no TAU) */
0xffff0000, 0x80010000, "7455", .pvr_mask = 0xffffffff,
CPU_FTR_COMMON | .pvr_value = 0x000c1101,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | .cpu_name = "7400 (1.1)",
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT, CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
32, 32, .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
__setup_cpu_745x .icache_bsize = 32,
}, .dcache_bsize = 32,
{ /* 7447/7457 Rev 1.0 */ .num_pmcs = 4,
0xffffffff, 0x80020100, "7447/7457", .cpu_setup = __setup_cpu_7400
CPU_FTR_COMMON | },
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | { /* 7400 */
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | .pvr_mask = 0xffff0000,
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | .pvr_value = 0x000c0000,
CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC, .cpu_name = "7400",
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, .cpu_features = CPU_FTR_COMMON |
32, 32, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
__setup_cpu_745x CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
}, CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
{ /* 7447/7457 Rev 1.1 */ CPU_FTR_MAYBE_CAN_NAP,
0xffffffff, 0x80020101, "7447/7457", .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
CPU_FTR_COMMON | .icache_bsize = 32,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | .dcache_bsize = 32,
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | .num_pmcs = 4,
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | .cpu_setup = __setup_cpu_7400
CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC, },
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, { /* 7410 */
32, 32, .pvr_mask = 0xffff0000,
__setup_cpu_745x .pvr_value = 0x800c0000,
}, .cpu_name = "7410",
{ /* 7447/7457 Rev 1.2 and later */ .cpu_features = CPU_FTR_COMMON |
0xffff0000, 0x80020000, "7447/7457", CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
CPU_FTR_COMMON | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | CPU_FTR_MAYBE_CAN_NAP,
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT, .icache_bsize = 32,
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, .dcache_bsize = 32,
32, 32, .num_pmcs = 4,
__setup_cpu_745x .cpu_setup = __setup_cpu_7410
}, },
{ /* 7447A */ { /* 7450 2.0 - no doze/nap */
0xffff0000, 0x80030000, "7447A", .pvr_mask = 0xffffffff,
CPU_FTR_COMMON | .pvr_value = 0x80000200,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | .cpu_name = "7450",
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT, CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
32, 32, CPU_FTR_NEED_COHERENT,
__setup_cpu_745x .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
}, .icache_bsize = 32,
{ /* 82xx (8240, 8245, 8260 are all 603e cores) */ .dcache_bsize = 32,
0x7fff0000, 0x00810000, "82xx", .num_pmcs = 6,
CPU_FTR_COMMON | .cpu_setup = __setup_cpu_745x
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB, },
COMMON_PPC, { /* 7450 2.1 */
32, 32, .pvr_mask = 0xffffffff,
__setup_cpu_603 .pvr_value = 0x80000201,
}, .cpu_name = "7450",
{ /* All G2_LE (603e core, plus some) have the same pvr */ .cpu_features = CPU_FTR_COMMON |
0x7fff0000, 0x00820000, "G2_LE", CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS, CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
COMMON_PPC, CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
32, 32, CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
__setup_cpu_603 CPU_FTR_NEED_COHERENT,
}, .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
{ /* default match, we assume split I/D cache & TB (non-601)... */ .icache_bsize = 32,
0x00000000, 0x00000000, "(generic PPC)", .dcache_bsize = 32,
CPU_FTR_COMMON | .num_pmcs = 6,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, .cpu_setup = __setup_cpu_745x
COMMON_PPC, },
32, 32, { /* 7450 2.3 and newer */
__setup_cpu_generic .pvr_mask = 0xffff0000,
}, .pvr_value = 0x80000000,
.cpu_name = "7450",
.cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
.cpu_setup = __setup_cpu_745x
},
{ /* 7455 rev 1.x */
.pvr_mask = 0xffffff00,
.pvr_value = 0x80010100,
.cpu_name = "7455",
.cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
.cpu_setup = __setup_cpu_745x
},
{ /* 7455 rev 2.0 */
.pvr_mask = 0xffffffff,
.pvr_value = 0x80010200,
.cpu_name = "7455",
.cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
.cpu_setup = __setup_cpu_745x
},
{ /* 7455 others */
.pvr_mask = 0xffff0000,
.pvr_value = 0x80010000,
.cpu_name = "7455",
.cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
CPU_FTR_NEED_COHERENT,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
.cpu_setup = __setup_cpu_745x
},
{ /* 7447/7457 Rev 1.0 */
.pvr_mask = 0xffffffff,
.pvr_value = 0x80020100,
.cpu_name = "7447/7457",
.cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
.cpu_setup = __setup_cpu_745x
},
{ /* 7447/7457 Rev 1.1 */
.pvr_mask = 0xffffffff,
.pvr_value = 0x80020101,
.cpu_name = "7447/7457",
.cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
.cpu_setup = __setup_cpu_745x
},
{ /* 7447/7457 Rev 1.2 and later */
.pvr_mask = 0xffff0000,
.pvr_value = 0x80020000,
.cpu_name = "7447/7457",
.cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
CPU_FTR_NEED_COHERENT,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
.cpu_setup = __setup_cpu_745x
},
{ /* 7447A */
.pvr_mask = 0xffff0000,
.pvr_value = 0x80030000,
.cpu_name = "7447A",
.cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
.cpu_setup = __setup_cpu_745x
},
{ /* 82xx (8240, 8245, 8260 are all 603e cores) */
.pvr_mask = 0x7fff0000,
.pvr_value = 0x00810000,
.cpu_name = "82xx",
.cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
CPU_FTR_USE_TB,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = __setup_cpu_603
},
{ /* All G2_LE (603e core, plus some) have the same pvr */
.pvr_mask = 0x7fff0000,
.pvr_value = 0x00820000,
.cpu_name = "G2_LE",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = __setup_cpu_603
},
{ /* default match, we assume split I/D cache & TB (non-601)... */
.pvr_mask = 0x00000000,
.pvr_value = 0x00000000,
.cpu_name = "(generic PPC)",
.cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HPTE_TABLE,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = __setup_cpu_generic
},
#endif /* CLASSIC_PPC */ #endif /* CLASSIC_PPC */
#ifdef CONFIG_PPC64BRIDGE #ifdef CONFIG_PPC64BRIDGE
{ /* Power3 */ { /* Power3 */
0xffff0000, 0x00400000, "Power3 (630)", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x00400000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, .cpu_name = "Power3 (630)",
COMMON_PPC | PPC_FEATURE_64, .cpu_features = CPU_FTR_COMMON |
128, 128, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
__setup_cpu_power3 CPU_FTR_HPTE_TABLE,
}, .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
{ /* Power3+ */ .icache_bsize = 128,
0xffff0000, 0x00410000, "Power3 (630+)", .dcache_bsize = 128,
CPU_FTR_COMMON | .num_pmcs = 8,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, .cpu_setup = __setup_cpu_power3
COMMON_PPC | PPC_FEATURE_64, },
128, 128, { /* Power3+ */
__setup_cpu_power3 .pvr_mask = 0xffff0000,
}, .pvr_value = 0x00410000,
.cpu_name = "Power3 (630+)",
.cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HPTE_TABLE,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
.cpu_setup = __setup_cpu_power3
},
{ /* I-star */ { /* I-star */
0xffff0000, 0x00360000, "I-star", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x00360000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, .cpu_name = "I-star",
COMMON_PPC | PPC_FEATURE_64, .cpu_features = CPU_FTR_COMMON |
128, 128, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
__setup_cpu_power3 CPU_FTR_HPTE_TABLE,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
.cpu_setup = __setup_cpu_power3
}, },
{ /* S-star */ { /* S-star */
0xffff0000, 0x00370000, "S-star", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x00370000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, .cpu_name = "S-star",
COMMON_PPC | PPC_FEATURE_64, .cpu_features = CPU_FTR_COMMON |
128, 128, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
__setup_cpu_power3 CPU_FTR_HPTE_TABLE,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
.cpu_setup = __setup_cpu_power3
}, },
#endif /* CONFIG_PPC64BRIDGE */ #endif /* CONFIG_PPC64BRIDGE */
#ifdef CONFIG_POWER4 #ifdef CONFIG_POWER4
{ /* Power4 */ { /* Power4 */
0xffff0000, 0x00350000, "Power4", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x00350000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, .cpu_name = "Power4",
COMMON_PPC | PPC_FEATURE_64, .cpu_features = CPU_FTR_COMMON |
128, 128, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
__setup_cpu_power4 CPU_FTR_HPTE_TABLE,
}, .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
{ /* PPC970 */ .icache_bsize = 128,
0xffff0000, 0x00390000, "PPC970", .dcache_bsize = 128,
CPU_FTR_COMMON | .num_pmcs = 8,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .cpu_setup = __setup_cpu_power4
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP, },
COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP, { /* PPC970 */
128, 128, .pvr_mask = 0xffff0000,
__setup_cpu_ppc970 .pvr_value = 0x00390000,
}, .cpu_name = "PPC970",
{ /* PPC970FX */ .cpu_features = CPU_FTR_COMMON |
0xffff0000, 0x003c0000, "PPC970FX", CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_COMMON | CPU_FTR_HPTE_TABLE |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP, .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP, PPC_FEATURE_ALTIVEC_COMP,
128, 128, .icache_bsize = 128,
__setup_cpu_ppc970 .dcache_bsize = 128,
}, .num_pmcs = 8,
.cpu_setup = __setup_cpu_ppc970
},
{ /* PPC970FX */
.pvr_mask = 0xffff0000,
.pvr_value = 0x003c0000,
.cpu_name = "PPC970FX",
.cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HPTE_TABLE |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
.cpu_setup = __setup_cpu_ppc970
},
#endif /* CONFIG_POWER4 */ #endif /* CONFIG_POWER4 */
#ifdef CONFIG_8xx #ifdef CONFIG_8xx
{ /* 8xx */ { /* 8xx */
0xffff0000, 0x00500000, "8xx", .pvr_mask = 0xffff0000,
.pvr_value = 0x00500000,
.cpu_name = "8xx",
/* CPU_FTR_MAYBE_CAN_DOZE is possible, /* CPU_FTR_MAYBE_CAN_DOZE is possible,
* if the 8xx code is there.... */ * if the 8xx code is there.... */
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, CPU_FTR_USE_TB,
16, 16, .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
__setup_cpu_8xx /* Empty */ .icache_bsize = 16,
}, .dcache_bsize = 16,
.num_pmcs = 0,
.cpu_setup = __setup_cpu_8xx /* Empty */
},
#endif /* CONFIG_8xx */ #endif /* CONFIG_8xx */
#ifdef CONFIG_40x #ifdef CONFIG_40x
{ /* 403GC */ { /* 403GC */
0xffffff00, 0x00200200, "403GC", .pvr_mask = 0xffffff00,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x00200200,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, .cpu_name = "403GC",
16, 16, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_403 */ CPU_FTR_USE_TB,
}, .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
{ /* 403GCX */ .icache_bsize = 16,
0xffffff00, 0x00201400, "403GCX", .dcache_bsize = 16,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .num_pmcs = 0,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, .cpu_setup = 0, /*__setup_cpu_403 */
16, 16, },
0, /*__setup_cpu_403 */ { /* 403GCX */
}, .pvr_mask = 0xffffff00,
{ /* 403G ?? */ .pvr_value = 0x00201400,
0xffff0000, 0x00200000, "403G ??", .cpu_name = "403GCX",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, CPU_FTR_USE_TB,
16, 16, .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
0, /*__setup_cpu_403 */ .icache_bsize = 16,
}, .dcache_bsize = 16,
{ /* 405GP */ .num_pmcs = 0,
0xffff0000, 0x40110000, "405GP", .cpu_setup = 0, /*__setup_cpu_403 */
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, },
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, { /* 403G ?? */
32, 32, .pvr_mask = 0xffff0000,
0, /*__setup_cpu_405 */ .pvr_value = 0x00200000,
}, .cpu_name = "403G ??",
{ /* STB 03xxx */ .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0xffff0000, 0x40130000, "STB03xxx", CPU_FTR_USE_TB,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, .icache_bsize = 16,
32, 32, .dcache_bsize = 16,
0, /*__setup_cpu_405 */ .num_pmcs = 0,
}, .cpu_setup = 0, /*__setup_cpu_403 */
{ /* STB 04xxx */ },
0xffff0000, 0x41810000, "STB04xxx", { /* 405GP */
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_mask = 0xffff0000,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, .pvr_value = 0x40110000,
32, 32, .cpu_name = "405GP",
0, /*__setup_cpu_405 */ .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
}, CPU_FTR_USE_TB,
{ /* NP405L */ .cpu_user_features = PPC_FEATURE_32 |
0xffff0000, 0x41610000, "NP405L", PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .icache_bsize = 32,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, .dcache_bsize = 32,
32, 32, .num_pmcs = 0,
0, /*__setup_cpu_405 */ .cpu_setup = 0, /*__setup_cpu_405 */
}, },
{ /* NP4GS3 */ { /* STB 03xxx */
0xffff0000, 0x40B10000, "NP4GS3", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x40130000,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, .cpu_name = "STB03xxx",
32, 32, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_405 */ CPU_FTR_USE_TB,
}, .cpu_user_features = PPC_FEATURE_32 |
{ /* NP405H */ PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
0xffff0000, 0x41410000, "NP405H", .icache_bsize = 32,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .dcache_bsize = 32,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, .num_pmcs = 0,
32, 32, .cpu_setup = 0, /*__setup_cpu_405 */
0, /*__setup_cpu_405 */ },
}, { /* STB 04xxx */
{ /* 405GPr */ .pvr_mask = 0xffff0000,
0xffff0000, 0x50910000, "405GPr", .pvr_value = 0x41810000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .cpu_name = "STB04xxx",
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
32, 32, CPU_FTR_USE_TB,
0, /*__setup_cpu_405 */ .cpu_user_features = PPC_FEATURE_32 |
}, PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
{ /* STBx25xx */ .icache_bsize = 32,
0xffff0000, 0x51510000, "STBx25xx", .dcache_bsize = 32,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .num_pmcs = 0,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, .cpu_setup = 0, /*__setup_cpu_405 */
32, 32, },
0, /*__setup_cpu_405 */ { /* NP405L */
}, .pvr_mask = 0xffff0000,
{ /* 405LP */ .pvr_value = 0x41610000,
0xffff0000, 0x41F10000, "405LP", .cpu_name = "NP405L",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, CPU_FTR_USE_TB,
32, 32, .cpu_user_features = PPC_FEATURE_32 |
0, /*__setup_cpu_405 */ PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
}, .icache_bsize = 32,
{ /* Xilinx Virtex-II Pro */ .dcache_bsize = 32,
0xffff0000, 0x20010000, "Virtex-II Pro", .num_pmcs = 0,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .cpu_setup = 0, /*__setup_cpu_405 */
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, },
32, 32, { /* NP4GS3 */
0, /*__setup_cpu_405 */ .pvr_mask = 0xffff0000,
}, .pvr_value = 0x40B10000,
.cpu_name = "NP4GS3",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_405 */
},
{ /* NP405H */
.pvr_mask = 0xffff0000,
.pvr_value = 0x41410000,
.cpu_name = "NP405H",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_405 */
},
{ /* 405GPr */
.pvr_mask = 0xffff0000,
.pvr_value = 0x50910000,
.cpu_name = "405GPr",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_405 */
},
{ /* STBx25xx */
.pvr_mask = 0xffff0000,
.pvr_value = 0x51510000,
.cpu_name = "STBx25xx",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_405 */
},
{ /* 405LP */
.pvr_mask = 0xffff0000,
.pvr_value = 0x41F10000,
.cpu_name = "405LP",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_405 */
},
{ /* Xilinx Virtex-II Pro */
.pvr_mask = 0xffff0000,
.pvr_value = 0x20010000,
.cpu_name = "Virtex-II Pro",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_405 */
},
#endif /* CONFIG_40x */ #endif /* CONFIG_40x */
#ifdef CONFIG_44x #ifdef CONFIG_44x
{ /* 440GP Rev. B */ { /* 440GP Rev. B */
0xf0000fff, 0x40000440, "440GP Rev. B", .pvr_mask = 0xf0000fff,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x40000440,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, .cpu_name = "440GP Rev. B",
32, 32, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_440 */ CPU_FTR_USE_TB,
}, .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
{ /* 440GP Rev. C */ .icache_bsize = 32,
0xf0000fff, 0x40000481, "440GP Rev. C", .dcache_bsize = 32,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .num_pmcs = 0,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, .cpu_setup = 0, /*__setup_cpu_440 */
32, 32, },
0, /*__setup_cpu_440 */ { /* 440GP Rev. C */
}, .pvr_mask = 0xf0000fff,
{ /* 440GX Rev. A */ .pvr_value = 0x40000481,
0xf0000fff, 0x50000850, "440GX Rev. A", .cpu_name = "440GP Rev. C",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, CPU_FTR_USE_TB,
32, 32, .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
0, /*__setup_cpu_440 */ .icache_bsize = 32,
}, .dcache_bsize = 32,
{ /* 440GX Rev. B */ .num_pmcs = 0,
0xf0000fff, 0x50000851, "440GX Rev. B", .cpu_setup = 0, /*__setup_cpu_440 */
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, },
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, { /* 440GX Rev. A */
32, 32, .pvr_mask = 0xf0000fff,
0, /*__setup_cpu_440 */ .pvr_value = 0x50000850,
}, .cpu_name = "440GX Rev. A",
{ /* 440GX Rev. C */ .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0xf0000fff, 0x50000892, "440GX Rev. C", CPU_FTR_USE_TB,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, .icache_bsize = 32,
32, 32, .dcache_bsize = 32,
0, /*__setup_cpu_440 */ .num_pmcs = 0,
}, .cpu_setup = 0, /*__setup_cpu_440 */
},
{ /* 440GX Rev. B */
.pvr_mask = 0xf0000fff,
.pvr_value = 0x50000851,
.cpu_name = "440GX Rev. B",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_440 */
},
{ /* 440GX Rev. C */
.pvr_mask = 0xf0000fff,
.pvr_value = 0x50000892,
.cpu_name = "440GX Rev. C",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_440 */
},
#endif /* CONFIG_44x */ #endif /* CONFIG_44x */
#ifdef CONFIG_E500 #ifdef CONFIG_E500
{ /* e500 */ { /* e500 */
0xffff0000, 0x80200000, "e500", .pvr_mask = 0xffff0000,
/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ .pvr_value = 0x80200000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .cpu_name = "e500",
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
32, 32, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_e500 */ CPU_FTR_USE_TB,
}, .cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
PPC_FEATURE_HAS_EFP_SINGLE,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
.cpu_setup = 0, /*__setup_cpu_e500 */
},
#endif #endif
#if !CLASSIC_PPC #if !CLASSIC_PPC
{ /* default match */ { /* default match */
0x00000000, 0x00000000, "(generic PPC)", .pvr_mask = 0x00000000,
CPU_FTR_COMMON, .pvr_value = 0x00000000,
PPC_FEATURE_32, .cpu_name = "(generic PPC)",
32, 32, .cpu_features = CPU_FTR_COMMON,
0, .cpu_user_features = PPC_FEATURE_32,
} .icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0,
}
#endif /* !CLASSIC_PPC */ #endif /* !CLASSIC_PPC */
}; };
include/asm-ppc/cputable.h
View file @ b99b64df
...@@ -21,6 +21,9 @@ ...@@ -21,6 +21,9 @@
#define PPC_FEATURE_HAS_MMU 0x04000000 #define PPC_FEATURE_HAS_MMU 0x04000000
#define PPC_FEATURE_HAS_4xxMAC 0x02000000 #define PPC_FEATURE_HAS_4xxMAC 0x02000000
#define PPC_FEATURE_UNIFIED_CACHE 0x01000000 #define PPC_FEATURE_UNIFIED_CACHE 0x01000000
#define PPC_FEATURE_HAS_SPE 0x00800000
#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
#ifdef __KERNEL__ #ifdef __KERNEL__
...@@ -46,6 +49,9 @@ struct cpu_spec { ...@@ -46,6 +49,9 @@ struct cpu_spec {
unsigned int icache_bsize; unsigned int icache_bsize;
unsigned int dcache_bsize; unsigned int dcache_bsize;
/* number of performance monitor counters */
unsigned int num_pmcs;
/* this is called to initialize various CPU bits like L1 cache, /* this is called to initialize various CPU bits like L1 cache,
* BHT, SPD, etc... from head.S before branching to identify_machine * BHT, SPD, etc... from head.S before branching to identify_machine
*/ */
......
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