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Commit b99b64df authored by Kumar Gala's avatar Kumar Gala Committed by Linus Torvalds
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[PATCH] ppc32: add performance counters to cpu_spec 

Adds the number of performance monitor counters each PowerPC processor has
to the cpu table.  Makes oprofile support a bit cleaner since we dont need
a case statement on processor version to determine the number of counters.
Signed-off-by: default avatarKumar Gala <kumar.gala@freescale.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 8d62a3ff
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Showing with 865 additions and 530 deletions
arch/ppc/kernel/cputable.c
View file @ b99b64df
...@@ -54,6 +54,15 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe ...@@ -54,6 +54,15 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe
#define PPC_FEATURE_ALTIVEC_COMP 0 #define PPC_FEATURE_ALTIVEC_COMP 0
#endif #endif
/* We only set the spe features if the kernel was compiled with
* spe support
*/
#ifdef CONFIG_SPE
#define PPC_FEATURE_SPE_COMP PPC_FEATURE_HAS_SPE
#else
#define PPC_FEATURE_SPE_COMP 0
#endif
/* We need to mark all pages as being coherent if we're SMP or we /* We need to mark all pages as being coherent if we're SMP or we
* have a 74[45]x and an MPC107 host bridge. * have a 74[45]x and an MPC107 host bridge.
*/ */
...@@ -77,554 +86,874 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe ...@@ -77,554 +86,874 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe
struct cpu_spec cpu_specs[] = { struct cpu_spec cpu_specs[] = {
#if CLASSIC_PPC #if CLASSIC_PPC
{ /* 601 */ { /* 601 */
0xffff0000, 0x00010000, "601", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x00010000,
CPU_FTR_601 | CPU_FTR_HPTE_TABLE, .cpu_name = "601",
COMMON_PPC | PPC_FEATURE_601_INSTR | PPC_FEATURE_UNIFIED_CACHE, .cpu_features = CPU_FTR_COMMON | CPU_FTR_601 |
32, 32, CPU_FTR_HPTE_TABLE,
__setup_cpu_601 .cpu_user_features = COMMON_PPC | PPC_FEATURE_601_INSTR |
PPC_FEATURE_UNIFIED_CACHE,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = __setup_cpu_601
}, },
{ /* 603 */ { /* 603 */
0xffff0000, 0x00030000, "603", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x00030000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_name = "603",
CPU_FTR_MAYBE_CAN_NAP, .cpu_features = CPU_FTR_COMMON |
COMMON_PPC, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
32, 32, CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
__setup_cpu_603 .cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = __setup_cpu_603
}, },
{ /* 603e */ { /* 603e */
0xffff0000, 0x00060000, "603e", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x00060000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_name = "603e",
CPU_FTR_MAYBE_CAN_NAP, .cpu_features = CPU_FTR_COMMON |
COMMON_PPC, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
32, 32, CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
__setup_cpu_603 .cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = __setup_cpu_603
}, },
{ /* 603ev */ { /* 603ev */
0xffff0000, 0x00070000, "603ev", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x00070000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_name = "603ev",
CPU_FTR_MAYBE_CAN_NAP, .cpu_features = CPU_FTR_COMMON |
COMMON_PPC, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
32, 32, CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
__setup_cpu_603 .cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = __setup_cpu_603
}, },
{ /* 604 */ { /* 604 */
0xffff0000, 0x00040000, "604", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x00040000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | .cpu_name = "604",
CPU_FTR_HPTE_TABLE, .cpu_features = CPU_FTR_COMMON |
COMMON_PPC, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
32, 32, CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
__setup_cpu_604 .cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 2,
.cpu_setup = __setup_cpu_604
}, },
{ /* 604e */ { /* 604e */
0xfffff000, 0x00090000, "604e", .pvr_mask = 0xfffff000,
CPU_FTR_COMMON | .pvr_value = 0x00090000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | .cpu_name = "604e",
CPU_FTR_HPTE_TABLE, .cpu_features = CPU_FTR_COMMON |
COMMON_PPC, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
32, 32, CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
__setup_cpu_604 .cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
.cpu_setup = __setup_cpu_604
}, },
{ /* 604r */ { /* 604r */
0xffff0000, 0x00090000, "604r", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x00090000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | .cpu_name = "604r",
CPU_FTR_HPTE_TABLE, .cpu_features = CPU_FTR_COMMON |
COMMON_PPC, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
32, 32, CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
__setup_cpu_604 .cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
.cpu_setup = __setup_cpu_604
}, },
{ /* 604ev */ { /* 604ev */
0xffff0000, 0x000a0000, "604ev", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x000a0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | .cpu_name = "604ev",
CPU_FTR_HPTE_TABLE, .cpu_features = CPU_FTR_COMMON |
COMMON_PPC, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
32, 32, CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
__setup_cpu_604 .cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
.cpu_setup = __setup_cpu_604
}, },
{ /* 740/750 (0x4202, don't support TAU ?) */ { /* 740/750 (0x4202, don't support TAU ?) */
0xffffffff, 0x00084202, "740/750", .pvr_mask = 0xffffffff,
CPU_FTR_COMMON | .pvr_value = 0x00084202,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_name = "740/750",
CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, .cpu_features = CPU_FTR_COMMON |
COMMON_PPC, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
32, 32, CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE |
__setup_cpu_750 CPU_FTR_MAYBE_CAN_NAP,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
.cpu_setup = __setup_cpu_750
}, },
{ /* 745/755 */ { /* 745/755 */
0xfffff000, 0x00083000, "745/755", .pvr_mask = 0xfffff000,
CPU_FTR_COMMON | .pvr_value = 0x00083000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_name = "745/755",
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, .cpu_features = CPU_FTR_COMMON |
COMMON_PPC, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
32, 32, CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
__setup_cpu_750 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
.cpu_setup = __setup_cpu_750
}, },
{ /* 750CX (80100 and 8010x?) */ { /* 750CX (80100 and 8010x?) */
0xfffffff0, 0x00080100, "750CX", .pvr_mask = 0xfffffff0,
CPU_FTR_COMMON | .pvr_value = 0x00080100,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_name = "750CX",
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, .cpu_features = CPU_FTR_COMMON |
COMMON_PPC, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
32, 32, CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
__setup_cpu_750cx CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
.cpu_setup = __setup_cpu_750cx
}, },
{ /* 750CX (82201 and 82202) */ { /* 750CX (82201 and 82202) */
0xfffffff0, 0x00082200, "750CX", .pvr_mask = 0xfffffff0,
CPU_FTR_COMMON | .pvr_value = 0x00082200,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_name = "750CX",
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, .cpu_features = CPU_FTR_COMMON |
COMMON_PPC, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
32, 32, CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
__setup_cpu_750cx CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
.cpu_setup = __setup_cpu_750cx
}, },
{ /* 750CXe (82214) */ { /* 750CXe (82214) */
0xfffffff0, 0x00082210, "750CXe", .pvr_mask = 0xfffffff0,
CPU_FTR_COMMON | .pvr_value = 0x00082210,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_name = "750CXe",
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, .cpu_features = CPU_FTR_COMMON |
COMMON_PPC, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
32, 32, CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
__setup_cpu_750cx CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
.cpu_setup = __setup_cpu_750cx
}, },
{ /* 750FX rev 1.x */ { /* 750FX rev 1.x */
0xffffff00, 0x70000100, "750FX", .pvr_mask = 0xffffff00,
CPU_FTR_COMMON | .pvr_value = 0x70000100,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_name = "750FX",
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM, CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
COMMON_PPC, .cpu_user_features = COMMON_PPC,
32, 32, .icache_bsize = 32,
__setup_cpu_750 .dcache_bsize = 32,
.num_pmcs = 4,
.cpu_setup = __setup_cpu_750
}, },
{ /* 750FX rev 2.0 must disable HID0[DPM] */ { /* 750FX rev 2.0 must disable HID0[DPM] */
0xffffffff, 0x70000200, "750FX", .pvr_mask = 0xffffffff,
CPU_FTR_COMMON | .pvr_value = 0x70000200,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_name = "750FX",
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_NO_DPM, CPU_FTR_NO_DPM,
COMMON_PPC, .cpu_user_features = COMMON_PPC,
32, 32, .icache_bsize = 32,
__setup_cpu_750 .dcache_bsize = 32,
.num_pmcs = 4,
.cpu_setup = __setup_cpu_750
}, },
{ /* 750FX (All revs except 2.0) */ { /* 750FX (All revs except 2.0) */
0xffff0000, 0x70000000, "750FX", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x70000000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_name = "750FX",
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS, CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
COMMON_PPC, .cpu_user_features = COMMON_PPC,
32, 32, .icache_bsize = 32,
__setup_cpu_750fx .dcache_bsize = 32,
.num_pmcs = 4,
.cpu_setup = __setup_cpu_750fx
}, },
{ /* 750GX */ { /* 750GX */
0xffff0000, 0x70020000, "750GX", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .pvr_value = 0x70020000,
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | .cpu_name = "750GX",
CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
COMMON_PPC, CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
32, 32, CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE |
__setup_cpu_750fx CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_DUAL_PLL_750FX |
CPU_FTR_HAS_HIGH_BATS,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
.cpu_setup = __setup_cpu_750fx
}, },
{ /* 740/750 (L2CR bit need fixup for 740) */ { /* 740/750 (L2CR bit need fixup for 740) */
0xffff0000, 0x00080000, "740/750", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x00080000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_name = "740/750",
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, .cpu_features = CPU_FTR_COMMON |
COMMON_PPC, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
32, 32, CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
__setup_cpu_750 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
.cpu_setup = __setup_cpu_750
}, },
{ /* 7400 rev 1.1 ? (no TAU) */ { /* 7400 rev 1.1 ? (no TAU) */
0xffffffff, 0x000c1101, "7400 (1.1)", .pvr_mask = 0xffffffff,
CPU_FTR_COMMON | .pvr_value = 0x000c1101,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_name = "7400 (1.1)",
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_MAYBE_CAN_NAP, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
32, 32, CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
__setup_cpu_7400 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
.cpu_setup = __setup_cpu_7400
}, },
{ /* 7400 */ { /* 7400 */
0xffff0000, 0x000c0000, "7400", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x000c0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_name = "7400",
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
CPU_FTR_MAYBE_CAN_NAP, CPU_FTR_MAYBE_CAN_NAP,
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
32, 32, .icache_bsize = 32,
__setup_cpu_7400 .dcache_bsize = 32,
.num_pmcs = 4,
.cpu_setup = __setup_cpu_7400
}, },
{ /* 7410 */ { /* 7410 */
0xffff0000, 0x800c0000, "7410", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x800c0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .cpu_name = "7410",
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
CPU_FTR_MAYBE_CAN_NAP, CPU_FTR_MAYBE_CAN_NAP,
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
32, 32, .icache_bsize = 32,
__setup_cpu_7410 .dcache_bsize = 32,
.num_pmcs = 4,
.cpu_setup = __setup_cpu_7410
}, },
{ /* 7450 2.0 - no doze/nap */ { /* 7450 2.0 - no doze/nap */
0xffffffff, 0x80000200, "7450", .pvr_mask = 0xffffffff,
CPU_FTR_COMMON | .pvr_value = 0x80000200,
.cpu_name = "7450",
.cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT, CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, CPU_FTR_NEED_COHERENT,
32, 32, .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
__setup_cpu_745x .icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
.cpu_setup = __setup_cpu_745x
}, },
{ /* 7450 2.1 */ { /* 7450 2.1 */
0xffffffff, 0x80000201, "7450", .pvr_mask = 0xffffffff,
CPU_FTR_COMMON | .pvr_value = 0x80000201,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | .cpu_name = "7450",
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT, CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
32, 32, CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
__setup_cpu_745x CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
CPU_FTR_NEED_COHERENT,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
.cpu_setup = __setup_cpu_745x
}, },
{ /* 7450 2.3 and newer */ { /* 7450 2.3 and newer */
0xffff0000, 0x80000000, "7450", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x80000000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | .cpu_name = "7450",
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_NEED_COHERENT, CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
32, 32, CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
__setup_cpu_745x CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
.cpu_setup = __setup_cpu_745x
}, },
{ /* 7455 rev 1.x */ { /* 7455 rev 1.x */
0xffffff00, 0x80010100, "7455", .pvr_mask = 0xffffff00,
CPU_FTR_COMMON | .pvr_value = 0x80010100,
.cpu_name = "7455",
.cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NEED_COHERENT, CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
32, 32, .icache_bsize = 32,
__setup_cpu_745x .dcache_bsize = 32,
.num_pmcs = 6,
.cpu_setup = __setup_cpu_745x
}, },
{ /* 7455 rev 2.0 */ { /* 7455 rev 2.0 */
0xffffffff, 0x80010200, "7455", .pvr_mask = 0xffffffff,
CPU_FTR_COMMON | .pvr_value = 0x80010200,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | .cpu_name = "7455",
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS, CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
32, 32, CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
__setup_cpu_745x CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
.cpu_setup = __setup_cpu_745x
}, },
{ /* 7455 others */ { /* 7455 others */
0xffff0000, 0x80010000, "7455", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x80010000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | .cpu_name = "7455",
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT, CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
32, 32, CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
__setup_cpu_745x CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
CPU_FTR_NEED_COHERENT,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
.cpu_setup = __setup_cpu_745x
}, },
{ /* 7447/7457 Rev 1.0 */ { /* 7447/7457 Rev 1.0 */
0xffffffff, 0x80020100, "7447/7457", .pvr_mask = 0xffffffff,
CPU_FTR_COMMON | .pvr_value = 0x80020100,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | .cpu_name = "7447/7457",
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC, CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
32, 32, CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
__setup_cpu_745x CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
.cpu_setup = __setup_cpu_745x
}, },
{ /* 7447/7457 Rev 1.1 */ { /* 7447/7457 Rev 1.1 */
0xffffffff, 0x80020101, "7447/7457", .pvr_mask = 0xffffffff,
CPU_FTR_COMMON | .pvr_value = 0x80020101,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | .cpu_name = "7447/7457",
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC, CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
32, 32, CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
__setup_cpu_745x CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
.cpu_setup = __setup_cpu_745x
}, },
{ /* 7447/7457 Rev 1.2 and later */ { /* 7447/7457 Rev 1.2 and later */
0xffff0000, 0x80020000, "7447/7457", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x80020000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | .cpu_name = "7447/7457",
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT, CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
32, 32, CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
__setup_cpu_745x CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
CPU_FTR_NEED_COHERENT,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
.cpu_setup = __setup_cpu_745x
}, },
{ /* 7447A */ { /* 7447A */
0xffff0000, 0x80030000, "7447A", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x80030000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | .cpu_name = "7447A",
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | .cpu_features = CPU_FTR_COMMON |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT, CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
32, 32, .icache_bsize = 32,
__setup_cpu_745x .dcache_bsize = 32,
.num_pmcs = 6,
.cpu_setup = __setup_cpu_745x
}, },
{ /* 82xx (8240, 8245, 8260 are all 603e cores) */ { /* 82xx (8240, 8245, 8260 are all 603e cores) */
0x7fff0000, 0x00810000, "82xx", .pvr_mask = 0x7fff0000,
CPU_FTR_COMMON | .pvr_value = 0x00810000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB, .cpu_name = "82xx",
COMMON_PPC, .cpu_features = CPU_FTR_COMMON |
32, 32, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
__setup_cpu_603 CPU_FTR_USE_TB,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = __setup_cpu_603
}, },
{ /* All G2_LE (603e core, plus some) have the same pvr */ { /* All G2_LE (603e core, plus some) have the same pvr */
0x7fff0000, 0x00820000, "G2_LE", .pvr_mask = 0x7fff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | .pvr_value = 0x00820000,
.cpu_name = "G2_LE",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS, CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
COMMON_PPC, .cpu_user_features = COMMON_PPC,
32, 32, .icache_bsize = 32,
__setup_cpu_603 .dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = __setup_cpu_603
}, },
{ /* default match, we assume split I/D cache & TB (non-601)... */ { /* default match, we assume split I/D cache & TB (non-601)... */
0x00000000, 0x00000000, "(generic PPC)", .pvr_mask = 0x00000000,
CPU_FTR_COMMON | .pvr_value = 0x00000000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, .cpu_name = "(generic PPC)",
COMMON_PPC, .cpu_features = CPU_FTR_COMMON |
32, 32, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
__setup_cpu_generic CPU_FTR_HPTE_TABLE,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = __setup_cpu_generic
}, },
#endif /* CLASSIC_PPC */ #endif /* CLASSIC_PPC */
#ifdef CONFIG_PPC64BRIDGE #ifdef CONFIG_PPC64BRIDGE
{ /* Power3 */ { /* Power3 */
0xffff0000, 0x00400000, "Power3 (630)", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x00400000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, .cpu_name = "Power3 (630)",
COMMON_PPC | PPC_FEATURE_64, .cpu_features = CPU_FTR_COMMON |
128, 128, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
__setup_cpu_power3 CPU_FTR_HPTE_TABLE,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
.cpu_setup = __setup_cpu_power3
}, },
{ /* Power3+ */ { /* Power3+ */
0xffff0000, 0x00410000, "Power3 (630+)", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x00410000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, .cpu_name = "Power3 (630+)",
COMMON_PPC | PPC_FEATURE_64, .cpu_features = CPU_FTR_COMMON |
128, 128, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
__setup_cpu_power3 CPU_FTR_HPTE_TABLE,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
.cpu_setup = __setup_cpu_power3
}, },
{ /* I-star */ { /* I-star */
0xffff0000, 0x00360000, "I-star", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x00360000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, .cpu_name = "I-star",
COMMON_PPC | PPC_FEATURE_64, .cpu_features = CPU_FTR_COMMON |
128, 128, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
__setup_cpu_power3 CPU_FTR_HPTE_TABLE,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
.cpu_setup = __setup_cpu_power3
}, },
{ /* S-star */ { /* S-star */
0xffff0000, 0x00370000, "S-star", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x00370000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, .cpu_name = "S-star",
COMMON_PPC | PPC_FEATURE_64, .cpu_features = CPU_FTR_COMMON |
128, 128, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
__setup_cpu_power3 CPU_FTR_HPTE_TABLE,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
.cpu_setup = __setup_cpu_power3
}, },
#endif /* CONFIG_PPC64BRIDGE */ #endif /* CONFIG_PPC64BRIDGE */
#ifdef CONFIG_POWER4 #ifdef CONFIG_POWER4
{ /* Power4 */ { /* Power4 */
0xffff0000, 0x00350000, "Power4", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x00350000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, .cpu_name = "Power4",
COMMON_PPC | PPC_FEATURE_64, .cpu_features = CPU_FTR_COMMON |
128, 128, CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
__setup_cpu_power4 CPU_FTR_HPTE_TABLE,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
.cpu_setup = __setup_cpu_power4
}, },
{ /* PPC970 */ { /* PPC970 */
0xffff0000, 0x00390000, "PPC970", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x00390000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .cpu_name = "PPC970",
.cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HPTE_TABLE |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP, CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP, .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
128, 128, PPC_FEATURE_ALTIVEC_COMP,
__setup_cpu_ppc970 .icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
.cpu_setup = __setup_cpu_ppc970
}, },
{ /* PPC970FX */ { /* PPC970FX */
0xffff0000, 0x003c0000, "PPC970FX", .pvr_mask = 0xffff0000,
CPU_FTR_COMMON | .pvr_value = 0x003c0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .cpu_name = "PPC970FX",
.cpu_features = CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HPTE_TABLE |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP, CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP, .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
128, 128, PPC_FEATURE_ALTIVEC_COMP,
__setup_cpu_ppc970 .icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
.cpu_setup = __setup_cpu_ppc970
}, },
#endif /* CONFIG_POWER4 */ #endif /* CONFIG_POWER4 */
#ifdef CONFIG_8xx #ifdef CONFIG_8xx
{ /* 8xx */ { /* 8xx */
0xffff0000, 0x00500000, "8xx", .pvr_mask = 0xffff0000,
.pvr_value = 0x00500000,
.cpu_name = "8xx",
/* CPU_FTR_MAYBE_CAN_DOZE is possible, /* CPU_FTR_MAYBE_CAN_DOZE is possible,
* if the 8xx code is there.... */ * if the 8xx code is there.... */
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, CPU_FTR_USE_TB,
16, 16, .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
__setup_cpu_8xx /* Empty */ .icache_bsize = 16,
.dcache_bsize = 16,
.num_pmcs = 0,
.cpu_setup = __setup_cpu_8xx /* Empty */
}, },
#endif /* CONFIG_8xx */ #endif /* CONFIG_8xx */
#ifdef CONFIG_40x #ifdef CONFIG_40x
{ /* 403GC */ { /* 403GC */
0xffffff00, 0x00200200, "403GC", .pvr_mask = 0xffffff00,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x00200200,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, .cpu_name = "403GC",
16, 16, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_403 */ CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 16,
.dcache_bsize = 16,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_403 */
}, },
{ /* 403GCX */ { /* 403GCX */
0xffffff00, 0x00201400, "403GCX", .pvr_mask = 0xffffff00,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x00201400,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, .cpu_name = "403GCX",
16, 16, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_403 */ CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 16,
.dcache_bsize = 16,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_403 */
}, },
{ /* 403G ?? */ { /* 403G ?? */
0xffff0000, 0x00200000, "403G ??", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x00200000,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, .cpu_name = "403G ??",
16, 16, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_403 */ CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 16,
.dcache_bsize = 16,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_403 */
}, },
{ /* 405GP */ { /* 405GP */
0xffff0000, 0x40110000, "405GP", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x40110000,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, .cpu_name = "405GP",
32, 32, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_405 */ CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_405 */
}, },
{ /* STB 03xxx */ { /* STB 03xxx */
0xffff0000, 0x40130000, "STB03xxx", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x40130000,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, .cpu_name = "STB03xxx",
32, 32, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_405 */ CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_405 */
}, },
{ /* STB 04xxx */ { /* STB 04xxx */
0xffff0000, 0x41810000, "STB04xxx", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x41810000,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, .cpu_name = "STB04xxx",
32, 32, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_405 */ CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_405 */
}, },
{ /* NP405L */ { /* NP405L */
0xffff0000, 0x41610000, "NP405L", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x41610000,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, .cpu_name = "NP405L",
32, 32, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_405 */ CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_405 */
}, },
{ /* NP4GS3 */ { /* NP4GS3 */
0xffff0000, 0x40B10000, "NP4GS3", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x40B10000,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, .cpu_name = "NP4GS3",
32, 32, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_405 */ CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_405 */
}, },
{ /* NP405H */ { /* NP405H */
0xffff0000, 0x41410000, "NP405H", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x41410000,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, .cpu_name = "NP405H",
32, 32, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_405 */ CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_405 */
}, },
{ /* 405GPr */ { /* 405GPr */
0xffff0000, 0x50910000, "405GPr", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x50910000,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, .cpu_name = "405GPr",
32, 32, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_405 */ CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_405 */
}, },
{ /* STBx25xx */ { /* STBx25xx */
0xffff0000, 0x51510000, "STBx25xx", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x51510000,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, .cpu_name = "STBx25xx",
32, 32, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_405 */ CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_405 */
}, },
{ /* 405LP */ { /* 405LP */
0xffff0000, 0x41F10000, "405LP", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x41F10000,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, .cpu_name = "405LP",
32, 32, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_405 */ CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_405 */
}, },
{ /* Xilinx Virtex-II Pro */ { /* Xilinx Virtex-II Pro */
0xffff0000, 0x20010000, "Virtex-II Pro", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x20010000,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, .cpu_name = "Virtex-II Pro",
32, 32, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_405 */ CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_405 */
}, },
#endif /* CONFIG_40x */ #endif /* CONFIG_40x */
#ifdef CONFIG_44x #ifdef CONFIG_44x
{ /* 440GP Rev. B */ { /* 440GP Rev. B */
0xf0000fff, 0x40000440, "440GP Rev. B", .pvr_mask = 0xf0000fff,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x40000440,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, .cpu_name = "440GP Rev. B",
32, 32, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_440 */ CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_440 */
}, },
{ /* 440GP Rev. C */ { /* 440GP Rev. C */
0xf0000fff, 0x40000481, "440GP Rev. C", .pvr_mask = 0xf0000fff,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x40000481,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, .cpu_name = "440GP Rev. C",
32, 32, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_440 */ CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_440 */
}, },
{ /* 440GX Rev. A */ { /* 440GX Rev. A */
0xf0000fff, 0x50000850, "440GX Rev. A", .pvr_mask = 0xf0000fff,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x50000850,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, .cpu_name = "440GX Rev. A",
32, 32, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_440 */ CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_440 */
}, },
{ /* 440GX Rev. B */ { /* 440GX Rev. B */
0xf0000fff, 0x50000851, "440GX Rev. B", .pvr_mask = 0xf0000fff,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x50000851,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, .cpu_name = "440GX Rev. B",
32, 32, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_440 */ CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_440 */
}, },
{ /* 440GX Rev. C */ { /* 440GX Rev. C */
0xf0000fff, 0x50000892, "440GX Rev. C", .pvr_mask = 0xf0000fff,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .pvr_value = 0x50000892,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, .cpu_name = "440GX Rev. C",
32, 32, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0, /*__setup_cpu_440 */ CPU_FTR_USE_TB,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0, /*__setup_cpu_440 */
}, },
#endif /* CONFIG_44x */ #endif /* CONFIG_44x */
#ifdef CONFIG_E500 #ifdef CONFIG_E500
{ /* e500 */ { /* e500 */
0xffff0000, 0x80200000, "e500", .pvr_mask = 0xffff0000,
.pvr_value = 0x80200000,
.cpu_name = "e500",
/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, CPU_FTR_USE_TB,
32, 32, .cpu_user_features = PPC_FEATURE_32 |
0, /*__setup_cpu_e500 */ PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
PPC_FEATURE_HAS_EFP_SINGLE,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
.cpu_setup = 0, /*__setup_cpu_e500 */
}, },
#endif #endif
#if !CLASSIC_PPC #if !CLASSIC_PPC
{ /* default match */ { /* default match */
0x00000000, 0x00000000, "(generic PPC)", .pvr_mask = 0x00000000,
CPU_FTR_COMMON, .pvr_value = 0x00000000,
PPC_FEATURE_32, .cpu_name = "(generic PPC)",
32, 32, .cpu_features = CPU_FTR_COMMON,
0, .cpu_user_features = PPC_FEATURE_32,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 0,
.cpu_setup = 0,
} }
#endif /* !CLASSIC_PPC */ #endif /* !CLASSIC_PPC */
}; };
include/asm-ppc/cputable.h
View file @ b99b64df
...@@ -21,6 +21,9 @@ ...@@ -21,6 +21,9 @@
#define PPC_FEATURE_HAS_MMU 0x04000000 #define PPC_FEATURE_HAS_MMU 0x04000000
#define PPC_FEATURE_HAS_4xxMAC 0x02000000 #define PPC_FEATURE_HAS_4xxMAC 0x02000000
#define PPC_FEATURE_UNIFIED_CACHE 0x01000000 #define PPC_FEATURE_UNIFIED_CACHE 0x01000000
#define PPC_FEATURE_HAS_SPE 0x00800000
#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
#ifdef __KERNEL__ #ifdef __KERNEL__
...@@ -46,6 +49,9 @@ struct cpu_spec { ...@@ -46,6 +49,9 @@ struct cpu_spec {
unsigned int icache_bsize; unsigned int icache_bsize;
unsigned int dcache_bsize; unsigned int dcache_bsize;
/* number of performance monitor counters */
unsigned int num_pmcs;
/* this is called to initialize various CPU bits like L1 cache, /* this is called to initialize various CPU bits like L1 cache,
* BHT, SPD, etc... from head.S before branching to identify_machine * BHT, SPD, etc... from head.S before branching to identify_machine
*/ */
......
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