Commit bb81bf62 authored by Jiasen Lin's avatar Jiasen Lin Committed by Jon Mason

NTB: Fix an error in get link status

The offset of PCIe Capability Header for AMD and HYGON NTB is 0x64,
but the macro which named "AMD_LINK_STATUS_OFFSET" is defined as 0x68.
It is offset of Device Capabilities Reg rather than Link Control Reg.

This code trigger an error in get link statsus:

	cat /sys/kernel/debug/ntb_hw_amd/0000:43:00.1/info
		LNK STA -               0x8fa1
		Link Status -           Up
		Link Speed -            PCI-E Gen 0
		Link Width -            x0

This patch use pcie_capability_read_dword to get link status.
After fix this issue, we can get link status accurately:

	cat /sys/kernel/debug/ntb_hw_amd/0000:43:00.1/info
		LNK STA -               0x11030042
		Link Status -           Up
		Link Speed -            PCI-E Gen 3
		Link Width -            x16

Fixes: a1b36958 ("NTB: Add support for AMD PCI-Express Non-Transparent Bridge")
Signed-off-by: default avatarJiasen Lin <linjiasen@hygon.cn>
Signed-off-by: default avatarJon Mason <jdmason@kudzu.us>
parent bb6d3fb3
......@@ -855,8 +855,8 @@ static int amd_poll_link(struct amd_ntb_dev *ndev)
ndev->cntl_sta = reg;
rc = pci_read_config_dword(ndev->ntb.pdev,
AMD_LINK_STATUS_OFFSET, &stat);
rc = pcie_capability_read_dword(ndev->ntb.pdev,
PCI_EXP_LNKCTL, &stat);
if (rc)
return 0;
ndev->lnk_sta = stat;
......
......@@ -53,7 +53,6 @@
#include <linux/pci.h>
#define AMD_LINK_HB_TIMEOUT msecs_to_jiffies(1000)
#define AMD_LINK_STATUS_OFFSET 0x68
#define NTB_LIN_STA_ACTIVE_BIT 0x00000002
#define NTB_LNK_STA_SPEED_MASK 0x000F0000
#define NTB_LNK_STA_WIDTH_MASK 0x03F00000
......
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