Commit bc797691 authored by Tero Kristo's avatar Tero Kristo

ARM: dts: omap2 clock data

This patch creates a unique node for each clock in the OMAP2 power,
reset and clock manager (PRCM).
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
parent f7c66b71
/*
* Device Tree Source for OMAP2420 clock data
*
* Copyright (C) 2014 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&prcm_clocks {
sys_clkout2_src_gate: sys_clkout2_src_gate {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&core_ck>;
ti,bit-shift = <15>;
reg = <0x0070>;
};
sys_clkout2_src_mux: sys_clkout2_src_mux {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
ti,bit-shift = <8>;
reg = <0x0070>;
};
sys_clkout2_src: sys_clkout2_src {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
};
sys_clkout2: sys_clkout2 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkout2_src>;
ti,bit-shift = <11>;
ti,max-div = <64>;
reg = <0x0070>;
ti,index-power-of-two;
};
dsp_gate_ick: dsp_gate_ick {
#clock-cells = <0>;
compatible = "ti,composite-interface-clock";
clocks = <&dsp_fck>;
ti,bit-shift = <1>;
reg = <0x0810>;
};
dsp_div_ick: dsp_div_ick {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&dsp_fck>;
ti,bit-shift = <5>;
ti,max-div = <3>;
reg = <0x0840>;
ti,index-starts-at-one;
};
dsp_ick: dsp_ick {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
};
iva1_gate_ifck: iva1_gate_ifck {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&core_ck>;
ti,bit-shift = <10>;
reg = <0x0800>;
};
iva1_div_ifck: iva1_div_ifck {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&core_ck>;
ti,bit-shift = <8>;
reg = <0x0840>;
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
};
iva1_ifck: iva1_ifck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
};
iva1_ifck_div: iva1_ifck_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&iva1_ifck>;
clock-mult = <1>;
clock-div = <2>;
};
iva1_mpu_int_ifck: iva1_mpu_int_ifck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&iva1_ifck_div>;
ti,bit-shift = <8>;
reg = <0x0800>;
};
wdt3_ick: wdt3_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <28>;
reg = <0x0210>;
};
wdt3_fck: wdt3_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_32k_ck>;
ti,bit-shift = <28>;
reg = <0x0200>;
};
mmc_ick: mmc_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <26>;
reg = <0x0210>;
};
mmc_fck: mmc_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_96m_ck>;
ti,bit-shift = <26>;
reg = <0x0200>;
};
eac_ick: eac_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <24>;
reg = <0x0210>;
};
eac_fck: eac_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_96m_ck>;
ti,bit-shift = <24>;
reg = <0x0200>;
};
i2c1_fck: i2c1_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_12m_ck>;
ti,bit-shift = <19>;
reg = <0x0200>;
};
i2c2_fck: i2c2_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_12m_ck>;
ti,bit-shift = <20>;
reg = <0x0200>;
};
vlynq_ick: vlynq_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l3_ck>;
ti,bit-shift = <3>;
reg = <0x0210>;
};
vlynq_gate_fck: vlynq_gate_fck {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&core_ck>;
ti,bit-shift = <3>;
reg = <0x0200>;
};
core_d18_ck: core_d18_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&core_ck>;
clock-mult = <1>;
clock-div = <18>;
};
vlynq_mux_fck: vlynq_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>;
ti,bit-shift = <15>;
reg = <0x0240>;
};
vlynq_fck: vlynq_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>;
};
};
&prcm_clockdomains {
gfx_clkdm: gfx_clkdm {
compatible = "ti,clockdomain";
clocks = <&gfx_ick>;
};
core_l3_clkdm: core_l3_clkdm {
compatible = "ti,clockdomain";
clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>;
};
wkup_clkdm: wkup_clkdm {
compatible = "ti,clockdomain";
clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
<&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
<&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>;
};
iva1_clkdm: iva1_clkdm {
compatible = "ti,clockdomain";
clocks = <&iva1_mpu_int_ifck>;
};
dss_clkdm: dss_clkdm {
compatible = "ti,clockdomain";
clocks = <&dss_ick>, <&dss_54m_fck>;
};
core_l4_clkdm: core_l4_clkdm {
compatible = "ti,clockdomain";
clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
<&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
<&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
<&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>,
<&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
<&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>,
<&uart3_ick>, <&uart3_fck>, <&cam_ick>,
<&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>,
<&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>,
<&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>,
<&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>,
<&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>,
<&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
<&pka_ick>;
};
};
&func_96m_ck {
compatible = "fixed-factor-clock";
clocks = <&apll96_ck>;
clock-mult = <1>;
clock-div = <1>;
};
&dsp_div_fck {
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
};
&ssi_ssr_sst_div_fck {
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
};
......@@ -14,6 +14,32 @@ / {
compatible = "ti,omap2420", "ti,omap2";
ocp {
prcm: prcm@48008000 {
compatible = "ti,omap2-prcm";
reg = <0x48008000 0x1000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prcm_clockdomains: clockdomains {
};
};
scrm: scrm@48000000 {
compatible = "ti,omap2-scrm";
reg = <0x48000000 0x1000>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
counter32k: counter@48004000 {
compatible = "ti,omap-counter32k";
reg = <0x48004000 0x20>;
......@@ -148,3 +174,6 @@ &i2c1 {
&i2c2 {
compatible = "ti,omap2420-i2c";
};
/include/ "omap24xx-clocks.dtsi"
/include/ "omap2420-clocks.dtsi"
/*
* Device Tree Source for OMAP2430 clock data
*
* Copyright (C) 2014 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&scrm_clocks {
mcbsp3_mux_fck: mcbsp3_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
reg = <0x02e8>;
};
mcbsp3_fck: mcbsp3_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
};
mcbsp4_mux_fck: mcbsp4_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
ti,bit-shift = <2>;
reg = <0x02e8>;
};
mcbsp4_fck: mcbsp4_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
};
mcbsp5_mux_fck: mcbsp5_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
ti,bit-shift = <4>;
reg = <0x02e8>;
};
mcbsp5_fck: mcbsp5_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
};
};
&prcm_clocks {
iva2_1_gate_ick: iva2_1_gate_ick {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&dsp_fck>;
ti,bit-shift = <0>;
reg = <0x0800>;
};
iva2_1_div_ick: iva2_1_div_ick {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&dsp_fck>;
ti,bit-shift = <5>;
ti,max-div = <3>;
reg = <0x0840>;
ti,index-starts-at-one;
};
iva2_1_ick: iva2_1_ick {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
};
mdm_gate_ick: mdm_gate_ick {
#clock-cells = <0>;
compatible = "ti,composite-interface-clock";
clocks = <&core_ck>;
ti,bit-shift = <0>;
reg = <0x0c10>;
};
mdm_div_ick: mdm_div_ick {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&core_ck>;
reg = <0x0c40>;
ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>;
};
mdm_ick: mdm_ick {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&mdm_gate_ick>, <&mdm_div_ick>;
};
mdm_osc_ck: mdm_osc_ck {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&osc_ck>;
ti,bit-shift = <1>;
reg = <0x0c00>;
};
mcbsp3_ick: mcbsp3_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <3>;
reg = <0x0214>;
};
mcbsp3_gate_fck: mcbsp3_gate_fck {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&mcbsp_clks>;
ti,bit-shift = <3>;
reg = <0x0204>;
};
mcbsp4_ick: mcbsp4_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <4>;
reg = <0x0214>;
};
mcbsp4_gate_fck: mcbsp4_gate_fck {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&mcbsp_clks>;
ti,bit-shift = <4>;
reg = <0x0204>;
};
mcbsp5_ick: mcbsp5_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <5>;
reg = <0x0214>;
};
mcbsp5_gate_fck: mcbsp5_gate_fck {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&mcbsp_clks>;
ti,bit-shift = <5>;
reg = <0x0204>;
};
mcspi3_ick: mcspi3_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <9>;
reg = <0x0214>;
};
mcspi3_fck: mcspi3_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_48m_ck>;
ti,bit-shift = <9>;
reg = <0x0204>;
};
icr_ick: icr_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&sys_ck>;
ti,bit-shift = <6>;
reg = <0x0410>;
};
i2chs1_fck: i2chs1_fck {
#clock-cells = <0>;
compatible = "ti,omap2430-interface-clock";
clocks = <&func_96m_ck>;
ti,bit-shift = <19>;
reg = <0x0204>;
};
i2chs2_fck: i2chs2_fck {
#clock-cells = <0>;
compatible = "ti,omap2430-interface-clock";
clocks = <&func_96m_ck>;
ti,bit-shift = <20>;
reg = <0x0204>;
};
usbhs_ick: usbhs_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l3_ck>;
ti,bit-shift = <6>;
reg = <0x0214>;
};
mmchs1_ick: mmchs1_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <7>;
reg = <0x0214>;
};
mmchs1_fck: mmchs1_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_96m_ck>;
ti,bit-shift = <7>;
reg = <0x0204>;
};
mmchs2_ick: mmchs2_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <8>;
reg = <0x0214>;
};
mmchs2_fck: mmchs2_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_96m_ck>;
ti,bit-shift = <8>;
reg = <0x0204>;
};
gpio5_ick: gpio5_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <10>;
reg = <0x0214>;
};
gpio5_fck: gpio5_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_32k_ck>;
ti,bit-shift = <10>;
reg = <0x0204>;
};
mdm_intc_ick: mdm_intc_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <11>;
reg = <0x0214>;
};
mmchsdb1_fck: mmchsdb1_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_32k_ck>;
ti,bit-shift = <16>;
reg = <0x0204>;
};
mmchsdb2_fck: mmchsdb2_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_32k_ck>;
ti,bit-shift = <17>;
reg = <0x0204>;
};
};
&prcm_clockdomains {
gfx_clkdm: gfx_clkdm {
compatible = "ti,clockdomain";
clocks = <&gfx_ick>;
};
core_l3_clkdm: core_l3_clkdm {
compatible = "ti,clockdomain";
clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>;
};
wkup_clkdm: wkup_clkdm {
compatible = "ti,clockdomain";
clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
<&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
<&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>,
<&icr_ick>;
};
dss_clkdm: dss_clkdm {
compatible = "ti,clockdomain";
clocks = <&dss_ick>, <&dss_54m_fck>;
};
core_l4_clkdm: core_l4_clkdm {
compatible = "ti,clockdomain";
clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
<&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
<&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
<&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
<&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>,
<&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
<&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>,
<&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>,
<&uart3_fck>, <&cam_ick>, <&mailboxes_ick>,
<&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>,
<&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>,
<&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>,
<&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
<&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>,
<&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>,
<&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>,
<&mmchsdb2_fck>;
};
mdm_clkdm: mdm_clkdm {
compatible = "ti,clockdomain";
clocks = <&mdm_osc_ck>;
};
};
&func_96m_ck {
compatible = "ti,mux-clock";
clocks = <&apll96_ck>, <&alt_ck>;
ti,bit-shift = <4>;
reg = <0x0540>;
};
&dsp_div_fck {
ti,max-div = <4>;
ti,index-starts-at-one;
};
&ssi_ssr_sst_div_fck {
ti,max-div = <5>;
ti,index-starts-at-one;
};
......@@ -14,6 +14,32 @@ / {
compatible = "ti,omap2430", "ti,omap2";
ocp {
prcm: prcm@49006000 {
compatible = "ti,omap2-prcm";
reg = <0x49006000 0x1000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prcm_clockdomains: clockdomains {
};
};
scrm: scrm@49002000 {
compatible = "ti,omap2-scrm";
reg = <0x49002000 0x1000>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
counter32k: counter@49020000 {
compatible = "ti,omap-counter32k";
reg = <0x49020000 0x20>;
......@@ -255,3 +281,6 @@ &i2c1 {
&i2c2 {
compatible = "ti,omap2430-i2c";
};
/include/ "omap24xx-clocks.dtsi"
/include/ "omap2430-clocks.dtsi"
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