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Commit bda7f4ee authored by Devin Heitmueller's avatar Devin Heitmueller Committed by Mauro Carvalho Chehab
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[media] s5h1432: fix codingstyle issues 

Run Lindent and fix a few spacing issues.

This patch makes no functional change to the driver.
Signed-off-by: default avatarDevin Heitmueller <dheitmueller@hauppauge.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent 9dfde557
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Inline Side-by-side
Showing with 152 additions and 170 deletions
drivers/media/dvb/frontends/s5h1432.c
View file @ bda7f4ee
......@@ -53,14 +53,13 @@ static int debug;
printk(arg); \
} while (0)
static int s5h1432_writereg(struct s5h1432_state *state,
u8 addr, u8 reg, u8 data)
{
int ret;
u8 buf[] = { reg, data };
struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = 2 };
struct i2c_msg msg = {.addr = addr, .flags = 0, .buf = buf, .len = 2 };
ret = i2c_transfer(state->i2c, &msg, 1);
......@@ -78,8 +77,9 @@ static u8 s5h1432_readreg(struct s5h1432_state *state, u8 addr, u8 reg)
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{ .addr = addr, .flags = 0, .buf = b0, .len = 1 },
{ .addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
{.addr = addr, .flags = 0, .buf = b0, .len = 1},
{.addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 1}
};
ret = i2c_transfer(state->i2c, msg, 2);
......@@ -94,15 +94,14 @@ static int s5h1432_sleep(struct dvb_frontend *fe)
return 0;
}
static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe,
u32 bandwidth)
{
struct s5h1432_state *state = fe->demodulator_priv;
u8 reg = 0;
/* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2*/
/* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2 */
reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E);
reg &= ~(0x0C);
switch (bandwidth) {
......@@ -124,65 +123,53 @@ static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
static int s5h1432_set_IF(struct dvb_frontend *fe, u32 ifFreqHz)
{
struct s5h1432_state *state = fe->demodulator_priv;
switch (ifFreqHz) {
case TAIWAN_HI_IF_FREQ_44_MHZ:
{
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x55);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x55);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0x15);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x15);
break;
}
case EUROPE_HI_IF_FREQ_36_MHZ:
{
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x00);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x00);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0x40);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x40);
break;
}
case IF_FREQ_6_MHZ:
{
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x00);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x00);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xe0);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xe0);
break;
}
case IF_FREQ_3point3_MHZ:
{
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x66);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x66);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEE);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
break;
}
case IF_FREQ_3point5_MHZ:
{
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x55);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x55);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xED);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xED);
break;
}
case IF_FREQ_4_MHZ:
{
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0xAA);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0xAA);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEA);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0xAA);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0xAA);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEA);
break;
}
default:
{
u32 value = 0;
value = (u32) (((48000 - (ifFreqHz / 1000)) * 512 *
(u32) 32768) / (48 * 1000));
printk(KERN_INFO "Default IFFreq %d :reg value = 0x%x \n",
printk(KERN_INFO
"Default IFFreq %d :reg value = 0x%x \n",
ifFreqHz, value);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 ,
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4,
(u8) value & 0xFF);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 ,
(u8)(value>>8) & 0xFF);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 ,
(u8)(value>>16) & 0xFF);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5,
(u8) (value >> 8) & 0xFF);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7,
(u8) (value >> 16) & 0xFF);
break;
}
......@@ -199,10 +186,11 @@ static int s5h1432_set_frontend(struct dvb_frontend *fe,
struct s5h1432_state *state = fe->demodulator_priv;
if (p->frequency == state->current_frequency) {
/*current_frequency = p->frequency;*/
/*state->current_frequency = p->frequency;*/
/*current_frequency = p->frequency; */
/*state->current_frequency = p->frequency; */
} else {
fe->ops.tuner_ops.set_params(fe, p); msleep(300);
fe->ops.tuner_ops.set_params(fe, p);
msleep(300);
s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
switch (p->u.ofdm.bandwidth) {
case BANDWIDTH_6_MHZ:
......@@ -220,14 +208,13 @@ static int s5h1432_set_frontend(struct dvb_frontend *fe,
default:
return 0;
}
/*fe->ops.tuner_ops.set_params(fe, p);*/
/*fe->ops.tuner_ops.set_params(fe, p); */
/*Soft Reset chip*/
msleep(30);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
msleep(30);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
switch (p->u.ofdm.bandwidth) {
case BANDWIDTH_6_MHZ:
......@@ -245,8 +232,8 @@ static int s5h1432_set_frontend(struct dvb_frontend *fe,
default:
return 0;
}
/*fe->ops.tuner_ops.set_params(fe,p);*/
/*Soft Reset chip*/
/*fe->ops.tuner_ops.set_params(fe,p); */
/*Soft Reset chip*/
msleep(30);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
msleep(30);
......@@ -259,7 +246,6 @@ static int s5h1432_set_frontend(struct dvb_frontend *fe,
return 0;
}
static int s5h1432_init(struct dvb_frontend *fe)
{
struct s5h1432_state *state = fe->demodulator_priv;
......@@ -268,9 +254,8 @@ static int s5h1432_init(struct dvb_frontend *fe)
state->current_frequency = 0;
printk(KERN_INFO " s5h1432_init().\n");
/*Set VSB mode as default, this also does a soft reset*/
/*Initialize registers*/
/*Set VSB mode as default, this also does a soft reset */
/*Initialize registers */
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04, 0xa8);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05, 0x01);
......@@ -290,25 +275,25 @@ static int s5h1432_init(struct dvb_frontend *fe)
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc, 0x9c);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA, 0x00);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1, 0x94);
/* s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4, 0xa1);*/
/* s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4, 0xa1); */
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9, 0x00);
/*For NXP tuner*/
/*For NXP tuner*/
/*Set 3.3MHz as default IF frequency*/
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x66);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x66);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEE);
/*Set 3.3MHz as default IF frequency */
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
/* Set reg 0x1E to get the full dynamic range */
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x31);
/*Mode setting in demod*/
/* Mode setting in demod */
reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42);
reg |= 0x80;
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg);
/*Serial mode*/
/* Serial mode */
/*Soft Reset chip*/
/* Soft Reset chip */
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
msleep(30);
......@@ -318,14 +303,11 @@ static int s5h1432_init(struct dvb_frontend *fe)
return 0;
}
static int s5h1432_read_status(struct dvb_frontend *fe, fe_status_t *status)
{
return 0;
}
static int s5h1432_read_signal_strength(struct dvb_frontend *fe,
u16 *signal_strength)
{
......@@ -397,6 +379,7 @@ struct dvb_frontend *s5h1432_attach(const struct s5h1432_config *config,
kfree(state);
return NULL;
}
EXPORT_SYMBOL(s5h1432_attach);
static struct dvb_frontend_ops s5h1432_ops = {
......@@ -411,8 +394,7 @@ static struct dvb_frontend_ops s5h1432_ops = {
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER
},
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER},
.init = s5h1432_init,
.sleep = s5h1432_sleep,
......
drivers/media/dvb/frontends/s5h1432.h
View file @ bda7f4ee
......@@ -79,8 +79,8 @@ struct s5h1432_config {
extern struct dvb_frontend *s5h1432_attach(const struct s5h1432_config *config,
struct i2c_adapter *i2c);
#else
static inline struct dvb_frontend *s5h1432_attach(
const struct s5h1432_config *config,
static inline struct dvb_frontend *s5h1432_attach(const struct s5h1432_config
*config,
struct i2c_adapter *i2c)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
......
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