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Commit c5011872 authored by Eric Bernstein's avatar Eric Bernstein Committed by Alex Deucher
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drm/amd/display: Make DCN stream encoder shareable 

Signed-off-by: default avatarEric Bernstein <eric.bernstein@amd.com>
Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent dc002a2e
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Showing with 343 additions and 421 deletions
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
View file @ c5011872
......@@ -26,27 +26,10 @@
#include "dc_bios_types.h"
#include "dce_stream_encoder.h"
#include "reg_helper.h"
#include "hw_shared.h"
#define DC_LOGGER \
enc110->base.ctx->logger
enum DP_PIXEL_ENCODING {
DP_PIXEL_ENCODING_RGB444 = 0x00000000,
DP_PIXEL_ENCODING_YCBCR422 = 0x00000001,
DP_PIXEL_ENCODING_YCBCR444 = 0x00000002,
DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003,
DP_PIXEL_ENCODING_Y_ONLY = 0x00000004,
DP_PIXEL_ENCODING_YCBCR420 = 0x00000005,
DP_PIXEL_ENCODING_RESERVED = 0x00000006,
};
enum DP_COMPONENT_DEPTH {
DP_COMPONENT_DEPTH_6BPC = 0x00000000,
DP_COMPONENT_DEPTH_8BPC = 0x00000001,
DP_COMPONENT_DEPTH_10BPC = 0x00000002,
DP_COMPONENT_DEPTH_12BPC = 0x00000003,
DP_COMPONENT_DEPTH_16BPC = 0x00000004,
DP_COMPONENT_DEPTH_RESERVED = 0x00000005,
};
#define REG(reg)\
......@@ -314,11 +297,11 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
switch (crtc_timing->pixel_encoding) {
case PIXEL_ENCODING_YCBCR422:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
DP_PIXEL_ENCODING_YCBCR422);
DP_PIXEL_ENCODING_TYPE_YCBCR422);
break;
case PIXEL_ENCODING_YCBCR444:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
DP_PIXEL_ENCODING_YCBCR444);
DP_PIXEL_ENCODING_TYPE_YCBCR444);
if (crtc_timing->flags.Y_ONLY)
if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
......@@ -326,7 +309,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
* Color depth of Y-only could be
* 8, 10, 12, 16 bits */
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
DP_PIXEL_ENCODING_Y_ONLY);
DP_PIXEL_ENCODING_TYPE_Y_ONLY);
/* Note: DP_MSA_MISC1 bit 7 is the indicator
* of Y-only mode.
* This bit is set in HW if register
......@@ -334,7 +317,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
break;
case PIXEL_ENCODING_YCBCR420:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
DP_PIXEL_ENCODING_YCBCR420);
DP_PIXEL_ENCODING_TYPE_YCBCR420);
if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
......@@ -345,7 +328,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
break;
default:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
DP_PIXEL_ENCODING_RGB444);
DP_PIXEL_ENCODING_TYPE_RGB444);
break;
}
......@@ -363,20 +346,20 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
break;
case COLOR_DEPTH_888:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_8BPC);
DP_COMPONENT_PIXEL_DEPTH_8BPC);
break;
case COLOR_DEPTH_101010:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_10BPC);
DP_COMPONENT_PIXEL_DEPTH_10BPC);
break;
case COLOR_DEPTH_121212:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_12BPC);
DP_COMPONENT_PIXEL_DEPTH_12BPC);
break;
default:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_6BPC);
DP_COMPONENT_PIXEL_DEPTH_6BPC);
break;
}
......
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
View file @ c5011872
......@@ -26,29 +26,11 @@
#include "dc_bios_types.h"
#include "dcn10_stream_encoder.h"
#include "reg_helper.h"
#include "hw_shared.h"
#define DC_LOGGER \
enc1->base.ctx->logger
enum DP_PIXEL_ENCODING {
DP_PIXEL_ENCODING_RGB444 = 0x00000000,
DP_PIXEL_ENCODING_YCBCR422 = 0x00000001,
DP_PIXEL_ENCODING_YCBCR444 = 0x00000002,
DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003,
DP_PIXEL_ENCODING_Y_ONLY = 0x00000004,
DP_PIXEL_ENCODING_YCBCR420 = 0x00000005,
DP_PIXEL_ENCODING_RESERVED = 0x00000006,
};
enum DP_COMPONENT_DEPTH {
DP_COMPONENT_DEPTH_6BPC = 0x00000000,
DP_COMPONENT_DEPTH_8BPC = 0x00000001,
DP_COMPONENT_DEPTH_10BPC = 0x00000002,
DP_COMPONENT_DEPTH_12BPC = 0x00000003,
DP_COMPONENT_DEPTH_16BPC = 0x00000004,
DP_COMPONENT_DEPTH_RESERVED = 0x00000005,
};
#define REG(reg)\
......@@ -70,7 +52,7 @@ enum {
#define CTX \
enc1->base.ctx
static void enc1_update_generic_info_packet(
void enc1_update_generic_info_packet(
struct dcn10_stream_encoder *enc1,
uint32_t packet_index,
const struct dc_info_packet *info_packet)
......@@ -260,7 +242,7 @@ static void enc1_update_hdmi_info_packet(
}
/* setup stream encoder in dp mode */
static void enc1_stream_encoder_dp_set_stream_attribute(
void enc1_stream_encoder_dp_set_stream_attribute(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
enum dc_color_space output_color_space)
......@@ -284,11 +266,11 @@ static void enc1_stream_encoder_dp_set_stream_attribute(
switch (crtc_timing->pixel_encoding) {
case PIXEL_ENCODING_YCBCR422:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
DP_PIXEL_ENCODING_YCBCR422);
DP_PIXEL_ENCODING_TYPE_YCBCR422);
break;
case PIXEL_ENCODING_YCBCR444:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
DP_PIXEL_ENCODING_YCBCR444);
DP_PIXEL_ENCODING_TYPE_YCBCR444);
if (crtc_timing->flags.Y_ONLY)
if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
......@@ -297,7 +279,7 @@ static void enc1_stream_encoder_dp_set_stream_attribute(
* 8, 10, 12, 16 bits
*/
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
DP_PIXEL_ENCODING_Y_ONLY);
DP_PIXEL_ENCODING_TYPE_Y_ONLY);
/* Note: DP_MSA_MISC1 bit 7 is the indicator
* of Y-only mode.
* This bit is set in HW if register
......@@ -306,12 +288,12 @@ static void enc1_stream_encoder_dp_set_stream_attribute(
break;
case PIXEL_ENCODING_YCBCR420:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
DP_PIXEL_ENCODING_YCBCR420);
DP_PIXEL_ENCODING_TYPE_YCBCR420);
REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
break;
default:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
DP_PIXEL_ENCODING_RGB444);
DP_PIXEL_ENCODING_TYPE_RGB444);
break;
}
......@@ -326,20 +308,20 @@ static void enc1_stream_encoder_dp_set_stream_attribute(
break;
case COLOR_DEPTH_888:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_8BPC);
DP_COMPONENT_PIXEL_DEPTH_8BPC);
break;
case COLOR_DEPTH_101010:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_10BPC);
DP_COMPONENT_PIXEL_DEPTH_10BPC);
break;
case COLOR_DEPTH_121212:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_12BPC);
DP_COMPONENT_PIXEL_DEPTH_12BPC);
break;
default:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_6BPC);
DP_COMPONENT_PIXEL_DEPTH_6BPC);
break;
}
......@@ -485,7 +467,7 @@ static void enc1_stream_encoder_set_stream_attribute_helper(
}
/* setup stream encoder in hdmi mode */
static void enc1_stream_encoder_hdmi_set_stream_attribute(
void enc1_stream_encoder_hdmi_set_stream_attribute(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
int actual_pix_clk_khz,
......@@ -591,7 +573,7 @@ static void enc1_stream_encoder_hdmi_set_stream_attribute(
}
/* setup stream encoder in dvi mode */
static void enc1_stream_encoder_dvi_set_stream_attribute(
void enc1_stream_encoder_dvi_set_stream_attribute(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
bool is_dual_link)
......@@ -616,7 +598,7 @@ static void enc1_stream_encoder_dvi_set_stream_attribute(
enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
}
static void enc1_stream_encoder_set_mst_bandwidth(
void enc1_stream_encoder_set_mst_bandwidth(
struct stream_encoder *enc,
struct fixed31_32 avg_time_slots_per_mtp)
{
......@@ -699,7 +681,7 @@ static void enc1_stream_encoder_stop_hdmi_info_packets(
HDMI_GENERIC1_SEND, 0);
}
static void enc1_stream_encoder_update_dp_info_packets(
void enc1_stream_encoder_update_dp_info_packets(
struct stream_encoder *enc,
const struct encoder_info_frame *info_frame)
{
......@@ -742,7 +724,7 @@ static void enc1_stream_encoder_update_dp_info_packets(
REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
}
static void enc1_stream_encoder_stop_dp_info_packets(
void enc1_stream_encoder_stop_dp_info_packets(
struct stream_encoder *enc)
{
/* stop generic packets on DP */
......@@ -770,7 +752,7 @@ static void enc1_stream_encoder_stop_dp_info_packets(
}
static void enc1_stream_encoder_dp_blank(
void enc1_stream_encoder_dp_blank(
struct stream_encoder *enc)
{
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
......@@ -823,7 +805,7 @@ static void enc1_stream_encoder_dp_blank(
}
/* output video stream to link encoder */
static void enc1_stream_encoder_dp_unblank(
void enc1_stream_encoder_dp_unblank(
struct stream_encoder *enc,
const struct encoder_unblank_param *param)
{
......@@ -885,7 +867,7 @@ static void enc1_stream_encoder_dp_unblank(
REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
}
static void enc1_stream_encoder_set_avmute(
void enc1_stream_encoder_set_avmute(
struct stream_encoder *enc,
bool enable)
{
......@@ -1442,7 +1424,7 @@ void enc1_se_hdmi_audio_disable(
}
static void enc1_setup_stereo_sync(
void enc1_setup_stereo_sync(
struct stream_encoder *enc,
int tg_inst, bool enable)
{
......
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
View file @ c5011872
......@@ -31,7 +31,8 @@
#define DCN10STRENC_FROM_STRENC(stream_encoder)\
container_of(stream_encoder, struct dcn10_stream_encoder, base)
#define SE_COMMON_REG_LIST_BASE(id) \
#define SE_COMMON_DCN_REG_LIST(id) \
SRI(AFMT_CNTL, DIG, id), \
SRI(AFMT_GENERIC_0, DIG, id), \
SRI(AFMT_GENERIC_1, DIG, id), \
SRI(AFMT_GENERIC_2, DIG, id), \
......@@ -43,6 +44,7 @@
SRI(AFMT_GENERIC_HDR, DIG, id), \
SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id), \
SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \
SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \
SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
......@@ -51,9 +53,12 @@
SRI(AFMT_60958_2, DIG, id), \
SRI(DIG_FE_CNTL, DIG, id), \
SRI(HDMI_CONTROL, DIG, id), \
SRI(HDMI_DB_CONTROL, DIG, id), \
SRI(HDMI_GC, DIG, id), \
SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
......@@ -65,7 +70,13 @@
SRI(HDMI_ACR_44_1, DIG, id),\
SRI(HDMI_ACR_48_0, DIG, id),\
SRI(HDMI_ACR_48_1, DIG, id),\
SRI(TMDS_CNTL, DIG, id), \
SRI(DP_DB_CNTL, DP, id), \
SRI(DP_MSA_MISC, DP, id), \
SRI(DP_MSA_COLORIMETRY, DP, id), \
SRI(DP_MSA_TIMING_PARAM1, DP, id), \
SRI(DP_MSA_TIMING_PARAM2, DP, id), \
SRI(DP_MSA_TIMING_PARAM3, DP, id), \
SRI(DP_MSA_TIMING_PARAM4, DP, id), \
SRI(DP_MSE_RATE_CNTL, DP, id), \
SRI(DP_MSE_RATE_UPDATE, DP, id), \
SRI(DP_PIXEL_FORMAT, DP, id), \
......@@ -79,19 +90,74 @@
SRI(DP_SEC_TIMESTAMP, DP, id)
#define SE_DCN_REG_LIST(id)\
SE_COMMON_REG_LIST_BASE(id),\
SRI(AFMT_CNTL, DIG, id),\
SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id),\
SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
SRI(DP_DB_CNTL, DP, id), \
SRI(DP_MSA_MISC, DP, id), \
SRI(DP_MSA_COLORIMETRY, DP, id), \
SRI(DP_MSA_TIMING_PARAM1, DP, id), \
SRI(DP_MSA_TIMING_PARAM2, DP, id), \
SRI(DP_MSA_TIMING_PARAM3, DP, id), \
SRI(DP_MSA_TIMING_PARAM4, DP, id), \
SRI(HDMI_DB_CONTROL, DIG, id)
SE_COMMON_DCN_REG_LIST(id)
struct dcn10_stream_enc_registers {
uint32_t AFMT_CNTL;
uint32_t AFMT_AVI_INFO0;
uint32_t AFMT_AVI_INFO1;
uint32_t AFMT_AVI_INFO2;
uint32_t AFMT_AVI_INFO3;
uint32_t AFMT_GENERIC_0;
uint32_t AFMT_GENERIC_1;
uint32_t AFMT_GENERIC_2;
uint32_t AFMT_GENERIC_3;
uint32_t AFMT_GENERIC_4;
uint32_t AFMT_GENERIC_5;
uint32_t AFMT_GENERIC_6;
uint32_t AFMT_GENERIC_7;
uint32_t AFMT_GENERIC_HDR;
uint32_t AFMT_INFOFRAME_CONTROL0;
uint32_t AFMT_VBI_PACKET_CONTROL;
uint32_t AFMT_VBI_PACKET_CONTROL1;
uint32_t AFMT_AUDIO_PACKET_CONTROL;
uint32_t AFMT_AUDIO_PACKET_CONTROL2;
uint32_t AFMT_AUDIO_SRC_CONTROL;
uint32_t AFMT_60958_0;
uint32_t AFMT_60958_1;
uint32_t AFMT_60958_2;
uint32_t DIG_FE_CNTL;
uint32_t DP_MSE_RATE_CNTL;
uint32_t DP_MSE_RATE_UPDATE;
uint32_t DP_PIXEL_FORMAT;
uint32_t DP_SEC_CNTL;
uint32_t DP_STEER_FIFO;
uint32_t DP_VID_M;
uint32_t DP_VID_N;
uint32_t DP_VID_STREAM_CNTL;
uint32_t DP_VID_TIMING;
uint32_t DP_SEC_AUD_N;
uint32_t DP_SEC_TIMESTAMP;
uint32_t HDMI_CONTROL;
uint32_t HDMI_GC;
uint32_t HDMI_GENERIC_PACKET_CONTROL0;
uint32_t HDMI_GENERIC_PACKET_CONTROL1;
uint32_t HDMI_GENERIC_PACKET_CONTROL2;
uint32_t HDMI_GENERIC_PACKET_CONTROL3;
uint32_t HDMI_GENERIC_PACKET_CONTROL4;
uint32_t HDMI_GENERIC_PACKET_CONTROL5;
uint32_t HDMI_INFOFRAME_CONTROL0;
uint32_t HDMI_INFOFRAME_CONTROL1;
uint32_t HDMI_VBI_PACKET_CONTROL;
uint32_t HDMI_AUDIO_PACKET_CONTROL;
uint32_t HDMI_ACR_PACKET_CONTROL;
uint32_t HDMI_ACR_32_0;
uint32_t HDMI_ACR_32_1;
uint32_t HDMI_ACR_44_0;
uint32_t HDMI_ACR_44_1;
uint32_t HDMI_ACR_48_0;
uint32_t HDMI_ACR_48_1;
uint32_t DP_DB_CNTL;
uint32_t DP_MSA_MISC;
uint32_t DP_MSA_COLORIMETRY;
uint32_t DP_MSA_TIMING_PARAM1;
uint32_t DP_MSA_TIMING_PARAM2;
uint32_t DP_MSA_TIMING_PARAM3;
uint32_t DP_MSA_TIMING_PARAM4;
uint32_t HDMI_DB_CONTROL;
};
#define SE_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
......@@ -221,348 +287,151 @@
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh)
#define SE_REG_FIELD_LIST_DCN1_0(type) \
type AFMT_GENERIC_INDEX;\
type AFMT_GENERIC_HB0;\
type AFMT_GENERIC_HB1;\
type AFMT_GENERIC_HB2;\
type AFMT_GENERIC_HB3;\
type AFMT_GENERIC_LOCK_STATUS;\
type AFMT_GENERIC_CONFLICT;\
type AFMT_GENERIC_CONFLICT_CLR;\
type AFMT_GENERIC0_FRAME_UPDATE_PENDING;\
type AFMT_GENERIC1_FRAME_UPDATE_PENDING;\
type AFMT_GENERIC2_FRAME_UPDATE_PENDING;\
type AFMT_GENERIC3_FRAME_UPDATE_PENDING;\
type AFMT_GENERIC4_FRAME_UPDATE_PENDING;\
type AFMT_GENERIC5_FRAME_UPDATE_PENDING;\
type AFMT_GENERIC6_FRAME_UPDATE_PENDING;\
type AFMT_GENERIC7_FRAME_UPDATE_PENDING;\
type AFMT_GENERIC0_FRAME_UPDATE;\
type AFMT_GENERIC1_FRAME_UPDATE;\
type AFMT_GENERIC2_FRAME_UPDATE;\
type AFMT_GENERIC3_FRAME_UPDATE;\
type AFMT_GENERIC4_FRAME_UPDATE;\
type AFMT_GENERIC5_FRAME_UPDATE;\
type AFMT_GENERIC6_FRAME_UPDATE;\
type AFMT_GENERIC7_FRAME_UPDATE;\
type HDMI_GENERIC0_CONT;\
type HDMI_GENERIC0_SEND;\
type HDMI_GENERIC0_LINE;\
type HDMI_GENERIC1_CONT;\
type HDMI_GENERIC1_SEND;\
type HDMI_GENERIC1_LINE;\
type HDMI_GENERIC2_CONT;\
type HDMI_GENERIC2_SEND;\
type HDMI_GENERIC2_LINE;\
type HDMI_GENERIC3_CONT;\
type HDMI_GENERIC3_SEND;\
type HDMI_GENERIC3_LINE;\
type HDMI_GENERIC4_CONT;\
type HDMI_GENERIC4_SEND;\
type HDMI_GENERIC4_LINE;\
type HDMI_GENERIC5_CONT;\
type HDMI_GENERIC5_SEND;\
type HDMI_GENERIC5_LINE;\
type HDMI_GENERIC6_CONT;\
type HDMI_GENERIC6_SEND;\
type HDMI_GENERIC6_LINE;\
type HDMI_GENERIC7_CONT;\
type HDMI_GENERIC7_SEND;\
type HDMI_GENERIC7_LINE;\
type DP_PIXEL_ENCODING;\
type DP_COMPONENT_DEPTH;\
type HDMI_PACKET_GEN_VERSION;\
type HDMI_KEEPOUT_MODE;\
type HDMI_DEEP_COLOR_ENABLE;\
type HDMI_CLOCK_CHANNEL_RATE;\
type HDMI_DEEP_COLOR_DEPTH;\
type HDMI_GC_CONT;\
type HDMI_GC_SEND;\
type HDMI_NULL_SEND;\
type HDMI_DATA_SCRAMBLE_EN;\
type HDMI_AUDIO_INFO_SEND;\
type AFMT_AUDIO_INFO_UPDATE;\
type HDMI_AUDIO_INFO_LINE;\
type HDMI_GC_AVMUTE;\
type DP_MSE_RATE_X;\
type DP_MSE_RATE_Y;\
type DP_MSE_RATE_UPDATE_PENDING;\
type DP_SEC_GSP0_ENABLE;\
type DP_SEC_STREAM_ENABLE;\
type DP_SEC_GSP1_ENABLE;\
type DP_SEC_GSP2_ENABLE;\
type DP_SEC_GSP3_ENABLE;\
type DP_SEC_GSP4_ENABLE;\
type DP_SEC_GSP5_ENABLE;\
type DP_SEC_GSP6_ENABLE;\
type DP_SEC_GSP7_ENABLE;\
type DP_SEC_MPG_ENABLE;\
type DP_VID_STREAM_DIS_DEFER;\
type DP_VID_STREAM_ENABLE;\
type DP_VID_STREAM_STATUS;\
type DP_STEER_FIFO_RESET;\
type DP_VID_M_N_GEN_EN;\
type DP_VID_N;\
type DP_VID_M;\
type DIG_START;\
type AFMT_AUDIO_SRC_SELECT;\
type AFMT_AUDIO_CHANNEL_ENABLE;\
type HDMI_AUDIO_PACKETS_PER_LINE;\
type HDMI_AUDIO_DELAY_EN;\
type AFMT_60958_CS_UPDATE;\
type AFMT_AUDIO_LAYOUT_OVRD;\
type AFMT_60958_OSF_OVRD;\
type HDMI_ACR_AUTO_SEND;\
type HDMI_ACR_SOURCE;\
type HDMI_ACR_AUDIO_PRIORITY;\
type HDMI_ACR_CTS_32;\
type HDMI_ACR_N_32;\
type HDMI_ACR_CTS_44;\
type HDMI_ACR_N_44;\
type HDMI_ACR_CTS_48;\
type HDMI_ACR_N_48;\
type AFMT_60958_CS_CHANNEL_NUMBER_L;\
type AFMT_60958_CS_CLOCK_ACCURACY;\
type AFMT_60958_CS_CHANNEL_NUMBER_R;\
type AFMT_60958_CS_CHANNEL_NUMBER_2;\
type AFMT_60958_CS_CHANNEL_NUMBER_3;\
type AFMT_60958_CS_CHANNEL_NUMBER_4;\
type AFMT_60958_CS_CHANNEL_NUMBER_5;\
type AFMT_60958_CS_CHANNEL_NUMBER_6;\
type AFMT_60958_CS_CHANNEL_NUMBER_7;\
type DP_SEC_AUD_N;\
type DP_SEC_TIMESTAMP_MODE;\
type DP_SEC_ASP_ENABLE;\
type DP_SEC_ATP_ENABLE;\
type DP_SEC_AIP_ENABLE;\
type DP_SEC_ACM_ENABLE;\
type AFMT_AUDIO_SAMPLE_SEND;\
type AFMT_AUDIO_CLOCK_EN;\
type TMDS_PIXEL_ENCODING;\
type TMDS_COLOR_FORMAT;\
type DIG_STEREOSYNC_SELECT;\
type DIG_STEREOSYNC_GATE_EN;\
type DP_DB_DISABLE;\
type DP_MSA_MISC0;\
type DP_MSA_HTOTAL;\
type DP_MSA_VTOTAL;\
type DP_MSA_HSTART;\
type DP_MSA_VSTART;\
type DP_MSA_HSYNCWIDTH;\
type DP_MSA_HSYNCPOLARITY;\
type DP_MSA_VSYNCWIDTH;\
type DP_MSA_VSYNCPOLARITY;\
type DP_MSA_HWIDTH;\
type DP_MSA_VHEIGHT;\
type HDMI_DB_DISABLE;\
type DP_VID_N_MUL;\
type DP_VID_M_DOUBLE_VALUE_EN
struct dcn10_stream_encoder_shift {
uint8_t AFMT_GENERIC_INDEX;
uint8_t AFMT_GENERIC_HB0;
uint8_t AFMT_GENERIC_HB1;
uint8_t AFMT_GENERIC_HB2;
uint8_t AFMT_GENERIC_HB3;
uint8_t AFMT_GENERIC_LOCK_STATUS;
uint8_t AFMT_GENERIC_CONFLICT;
uint8_t AFMT_GENERIC_CONFLICT_CLR;
uint8_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
uint8_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
uint8_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
uint8_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
uint8_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
uint8_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
uint8_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
uint8_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
uint8_t AFMT_GENERIC0_FRAME_UPDATE;
uint8_t AFMT_GENERIC1_FRAME_UPDATE;
uint8_t AFMT_GENERIC2_FRAME_UPDATE;
uint8_t AFMT_GENERIC3_FRAME_UPDATE;
uint8_t AFMT_GENERIC4_FRAME_UPDATE;
uint8_t AFMT_GENERIC5_FRAME_UPDATE;
uint8_t AFMT_GENERIC6_FRAME_UPDATE;
uint8_t AFMT_GENERIC7_FRAME_UPDATE;
uint8_t HDMI_GENERIC0_CONT;
uint8_t HDMI_GENERIC0_SEND;
uint8_t HDMI_GENERIC0_LINE;
uint8_t HDMI_GENERIC1_CONT;
uint8_t HDMI_GENERIC1_SEND;
uint8_t HDMI_GENERIC1_LINE;
uint8_t HDMI_GENERIC2_CONT;
uint8_t HDMI_GENERIC2_SEND;
uint8_t HDMI_GENERIC2_LINE;
uint8_t HDMI_GENERIC3_CONT;
uint8_t HDMI_GENERIC3_SEND;
uint8_t HDMI_GENERIC3_LINE;
uint8_t HDMI_GENERIC4_CONT;
uint8_t HDMI_GENERIC4_SEND;
uint8_t HDMI_GENERIC4_LINE;
uint8_t HDMI_GENERIC5_CONT;
uint8_t HDMI_GENERIC5_SEND;
uint8_t HDMI_GENERIC5_LINE;
uint8_t HDMI_GENERIC6_CONT;
uint8_t HDMI_GENERIC6_SEND;
uint8_t HDMI_GENERIC6_LINE;
uint8_t HDMI_GENERIC7_CONT;
uint8_t HDMI_GENERIC7_SEND;
uint8_t HDMI_GENERIC7_LINE;
uint8_t DP_PIXEL_ENCODING;
uint8_t DP_COMPONENT_DEPTH;
uint8_t HDMI_PACKET_GEN_VERSION;
uint8_t HDMI_KEEPOUT_MODE;
uint8_t HDMI_DEEP_COLOR_ENABLE;
uint8_t HDMI_CLOCK_CHANNEL_RATE;
uint8_t HDMI_DEEP_COLOR_DEPTH;
uint8_t HDMI_GC_CONT;
uint8_t HDMI_GC_SEND;
uint8_t HDMI_NULL_SEND;
uint8_t HDMI_DATA_SCRAMBLE_EN;
uint8_t HDMI_AUDIO_INFO_SEND;
uint8_t AFMT_AUDIO_INFO_UPDATE;
uint8_t HDMI_AUDIO_INFO_LINE;
uint8_t HDMI_GC_AVMUTE;
uint8_t DP_MSE_RATE_X;
uint8_t DP_MSE_RATE_Y;
uint8_t DP_MSE_RATE_UPDATE_PENDING;
uint8_t DP_SEC_GSP0_ENABLE;
uint8_t DP_SEC_STREAM_ENABLE;
uint8_t DP_SEC_GSP1_ENABLE;
uint8_t DP_SEC_GSP2_ENABLE;
uint8_t DP_SEC_GSP3_ENABLE;
uint8_t DP_SEC_GSP4_ENABLE;
uint8_t DP_SEC_GSP5_ENABLE;
uint8_t DP_SEC_GSP6_ENABLE;
uint8_t DP_SEC_GSP7_ENABLE;
uint8_t DP_SEC_MPG_ENABLE;
uint8_t DP_VID_STREAM_DIS_DEFER;
uint8_t DP_VID_STREAM_ENABLE;
uint8_t DP_VID_STREAM_STATUS;
uint8_t DP_STEER_FIFO_RESET;
uint8_t DP_VID_M_N_GEN_EN;
uint8_t DP_VID_N;
uint8_t DP_VID_M;
uint8_t DIG_START;
uint8_t AFMT_AUDIO_SRC_SELECT;
uint8_t AFMT_AUDIO_CHANNEL_ENABLE;
uint8_t HDMI_AUDIO_PACKETS_PER_LINE;
uint8_t HDMI_AUDIO_DELAY_EN;
uint8_t AFMT_60958_CS_UPDATE;
uint8_t AFMT_AUDIO_LAYOUT_OVRD;
uint8_t AFMT_60958_OSF_OVRD;
uint8_t HDMI_ACR_AUTO_SEND;
uint8_t HDMI_ACR_SOURCE;
uint8_t HDMI_ACR_AUDIO_PRIORITY;
uint8_t HDMI_ACR_CTS_32;
uint8_t HDMI_ACR_N_32;
uint8_t HDMI_ACR_CTS_44;
uint8_t HDMI_ACR_N_44;
uint8_t HDMI_ACR_CTS_48;
uint8_t HDMI_ACR_N_48;
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_L;
uint8_t AFMT_60958_CS_CLOCK_ACCURACY;
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_R;
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_2;
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_3;
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_4;
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_5;
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_6;
uint8_t AFMT_60958_CS_CHANNEL_NUMBER_7;
uint8_t DP_SEC_AUD_N;
uint8_t DP_SEC_TIMESTAMP_MODE;
uint8_t DP_SEC_ASP_ENABLE;
uint8_t DP_SEC_ATP_ENABLE;
uint8_t DP_SEC_AIP_ENABLE;
uint8_t DP_SEC_ACM_ENABLE;
uint8_t AFMT_AUDIO_SAMPLE_SEND;
uint8_t AFMT_AUDIO_CLOCK_EN;
uint8_t TMDS_PIXEL_ENCODING;
uint8_t TMDS_COLOR_FORMAT;
uint8_t DIG_STEREOSYNC_SELECT;
uint8_t DIG_STEREOSYNC_GATE_EN;
uint8_t DP_DB_DISABLE;
uint8_t DP_MSA_MISC0;
uint8_t DP_MSA_HTOTAL;
uint8_t DP_MSA_VTOTAL;
uint8_t DP_MSA_HSTART;
uint8_t DP_MSA_VSTART;
uint8_t DP_MSA_HSYNCWIDTH;
uint8_t DP_MSA_HSYNCPOLARITY;
uint8_t DP_MSA_VSYNCWIDTH;
uint8_t DP_MSA_VSYNCPOLARITY;
uint8_t DP_MSA_HWIDTH;
uint8_t DP_MSA_VHEIGHT;
uint8_t HDMI_DB_DISABLE;
uint8_t DP_VID_N_MUL;
uint8_t DP_VID_M_DOUBLE_VALUE_EN;
SE_REG_FIELD_LIST_DCN1_0(uint8_t);
};
struct dcn10_stream_encoder_mask {
uint32_t AFMT_GENERIC_INDEX;
uint32_t AFMT_GENERIC_HB0;
uint32_t AFMT_GENERIC_HB1;
uint32_t AFMT_GENERIC_HB2;
uint32_t AFMT_GENERIC_HB3;
uint32_t AFMT_GENERIC_LOCK_STATUS;
uint32_t AFMT_GENERIC_CONFLICT;
uint32_t AFMT_GENERIC_CONFLICT_CLR;
uint32_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
uint32_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
uint32_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
uint32_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
uint32_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
uint32_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
uint32_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
uint32_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
uint32_t AFMT_GENERIC0_FRAME_UPDATE;
uint32_t AFMT_GENERIC1_FRAME_UPDATE;
uint32_t AFMT_GENERIC2_FRAME_UPDATE;
uint32_t AFMT_GENERIC3_FRAME_UPDATE;
uint32_t AFMT_GENERIC4_FRAME_UPDATE;
uint32_t AFMT_GENERIC5_FRAME_UPDATE;
uint32_t AFMT_GENERIC6_FRAME_UPDATE;
uint32_t AFMT_GENERIC7_FRAME_UPDATE;
uint32_t HDMI_GENERIC0_CONT;
uint32_t HDMI_GENERIC0_SEND;
uint32_t HDMI_GENERIC0_LINE;
uint32_t HDMI_GENERIC1_CONT;
uint32_t HDMI_GENERIC1_SEND;
uint32_t HDMI_GENERIC1_LINE;
uint32_t HDMI_GENERIC2_CONT;
uint32_t HDMI_GENERIC2_SEND;
uint32_t HDMI_GENERIC2_LINE;
uint32_t HDMI_GENERIC3_CONT;
uint32_t HDMI_GENERIC3_SEND;
uint32_t HDMI_GENERIC3_LINE;
uint32_t HDMI_GENERIC4_CONT;
uint32_t HDMI_GENERIC4_SEND;
uint32_t HDMI_GENERIC4_LINE;
uint32_t HDMI_GENERIC5_CONT;
uint32_t HDMI_GENERIC5_SEND;
uint32_t HDMI_GENERIC5_LINE;
uint32_t HDMI_GENERIC6_CONT;
uint32_t HDMI_GENERIC6_SEND;
uint32_t HDMI_GENERIC6_LINE;
uint32_t HDMI_GENERIC7_CONT;
uint32_t HDMI_GENERIC7_SEND;
uint32_t HDMI_GENERIC7_LINE;
uint32_t DP_PIXEL_ENCODING;
uint32_t DP_COMPONENT_DEPTH;
uint32_t HDMI_PACKET_GEN_VERSION;
uint32_t HDMI_KEEPOUT_MODE;
uint32_t HDMI_DEEP_COLOR_ENABLE;
uint32_t HDMI_CLOCK_CHANNEL_RATE;
uint32_t HDMI_DEEP_COLOR_DEPTH;
uint32_t HDMI_GC_CONT;
uint32_t HDMI_GC_SEND;
uint32_t HDMI_NULL_SEND;
uint32_t HDMI_DATA_SCRAMBLE_EN;
uint32_t HDMI_AUDIO_INFO_SEND;
uint32_t AFMT_AUDIO_INFO_UPDATE;
uint32_t HDMI_AUDIO_INFO_LINE;
uint32_t HDMI_GC_AVMUTE;
uint32_t DP_MSE_RATE_X;
uint32_t DP_MSE_RATE_Y;
uint32_t DP_MSE_RATE_UPDATE_PENDING;
uint32_t DP_SEC_GSP0_ENABLE;
uint32_t DP_SEC_STREAM_ENABLE;
uint32_t DP_SEC_GSP1_ENABLE;
uint32_t DP_SEC_GSP2_ENABLE;
uint32_t DP_SEC_GSP3_ENABLE;
uint32_t DP_SEC_GSP4_ENABLE;
uint32_t DP_SEC_GSP5_ENABLE;
uint32_t DP_SEC_GSP6_ENABLE;
uint32_t DP_SEC_GSP7_ENABLE;
uint32_t DP_SEC_MPG_ENABLE;
uint32_t DP_VID_STREAM_DIS_DEFER;
uint32_t DP_VID_STREAM_ENABLE;
uint32_t DP_VID_STREAM_STATUS;
uint32_t DP_STEER_FIFO_RESET;
uint32_t DP_VID_M_N_GEN_EN;
uint32_t DP_VID_N;
uint32_t DP_VID_M;
uint32_t DIG_START;
uint32_t AFMT_AUDIO_SRC_SELECT;
uint32_t AFMT_AUDIO_CHANNEL_ENABLE;
uint32_t HDMI_AUDIO_PACKETS_PER_LINE;
uint32_t HDMI_AUDIO_DELAY_EN;
uint32_t AFMT_60958_CS_UPDATE;
uint32_t AFMT_AUDIO_LAYOUT_OVRD;
uint32_t AFMT_60958_OSF_OVRD;
uint32_t HDMI_ACR_AUTO_SEND;
uint32_t HDMI_ACR_SOURCE;
uint32_t HDMI_ACR_AUDIO_PRIORITY;
uint32_t HDMI_ACR_CTS_32;
uint32_t HDMI_ACR_N_32;
uint32_t HDMI_ACR_CTS_44;
uint32_t HDMI_ACR_N_44;
uint32_t HDMI_ACR_CTS_48;
uint32_t HDMI_ACR_N_48;
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_L;
uint32_t AFMT_60958_CS_CLOCK_ACCURACY;
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_R;
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_2;
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_3;
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_4;
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_5;
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_6;
uint32_t AFMT_60958_CS_CHANNEL_NUMBER_7;
uint32_t DP_SEC_AUD_N;
uint32_t DP_SEC_TIMESTAMP_MODE;
uint32_t DP_SEC_ASP_ENABLE;
uint32_t DP_SEC_ATP_ENABLE;
uint32_t DP_SEC_AIP_ENABLE;
uint32_t DP_SEC_ACM_ENABLE;
uint32_t AFMT_AUDIO_SAMPLE_SEND;
uint32_t AFMT_AUDIO_CLOCK_EN;
uint32_t TMDS_PIXEL_ENCODING;
uint32_t DIG_STEREOSYNC_SELECT;
uint32_t DIG_STEREOSYNC_GATE_EN;
uint32_t TMDS_COLOR_FORMAT;
uint32_t DP_DB_DISABLE;
uint32_t DP_MSA_MISC0;
uint32_t DP_MSA_HTOTAL;
uint32_t DP_MSA_VTOTAL;
uint32_t DP_MSA_HSTART;
uint32_t DP_MSA_VSTART;
uint32_t DP_MSA_HSYNCWIDTH;
uint32_t DP_MSA_HSYNCPOLARITY;
uint32_t DP_MSA_VSYNCWIDTH;
uint32_t DP_MSA_VSYNCPOLARITY;
uint32_t DP_MSA_HWIDTH;
uint32_t DP_MSA_VHEIGHT;
uint32_t HDMI_DB_DISABLE;
uint32_t DP_VID_N_MUL;
uint32_t DP_VID_M_DOUBLE_VALUE_EN;
};
struct dcn10_stream_enc_registers {
uint32_t AFMT_CNTL;
uint32_t AFMT_AVI_INFO0;
uint32_t AFMT_AVI_INFO1;
uint32_t AFMT_AVI_INFO2;
uint32_t AFMT_AVI_INFO3;
uint32_t AFMT_GENERIC_0;
uint32_t AFMT_GENERIC_1;
uint32_t AFMT_GENERIC_2;
uint32_t AFMT_GENERIC_3;
uint32_t AFMT_GENERIC_4;
uint32_t AFMT_GENERIC_5;
uint32_t AFMT_GENERIC_6;
uint32_t AFMT_GENERIC_7;
uint32_t AFMT_GENERIC_HDR;
uint32_t AFMT_INFOFRAME_CONTROL0;
uint32_t AFMT_VBI_PACKET_CONTROL;
uint32_t AFMT_VBI_PACKET_CONTROL1;
uint32_t AFMT_AUDIO_PACKET_CONTROL;
uint32_t AFMT_AUDIO_PACKET_CONTROL2;
uint32_t AFMT_AUDIO_SRC_CONTROL;
uint32_t AFMT_60958_0;
uint32_t AFMT_60958_1;
uint32_t AFMT_60958_2;
uint32_t DIG_FE_CNTL;
uint32_t DP_MSE_RATE_CNTL;
uint32_t DP_MSE_RATE_UPDATE;
uint32_t DP_PIXEL_FORMAT;
uint32_t DP_SEC_CNTL;
uint32_t DP_STEER_FIFO;
uint32_t DP_VID_M;
uint32_t DP_VID_N;
uint32_t DP_VID_STREAM_CNTL;
uint32_t DP_VID_TIMING;
uint32_t DP_SEC_AUD_N;
uint32_t DP_SEC_TIMESTAMP;
uint32_t HDMI_CONTROL;
uint32_t HDMI_GC;
uint32_t HDMI_GENERIC_PACKET_CONTROL0;
uint32_t HDMI_GENERIC_PACKET_CONTROL1;
uint32_t HDMI_GENERIC_PACKET_CONTROL2;
uint32_t HDMI_GENERIC_PACKET_CONTROL3;
uint32_t HDMI_GENERIC_PACKET_CONTROL4;
uint32_t HDMI_GENERIC_PACKET_CONTROL5;
uint32_t HDMI_INFOFRAME_CONTROL0;
uint32_t HDMI_INFOFRAME_CONTROL1;
uint32_t HDMI_VBI_PACKET_CONTROL;
uint32_t HDMI_AUDIO_PACKET_CONTROL;
uint32_t HDMI_ACR_PACKET_CONTROL;
uint32_t HDMI_ACR_32_0;
uint32_t HDMI_ACR_32_1;
uint32_t HDMI_ACR_44_0;
uint32_t HDMI_ACR_44_1;
uint32_t HDMI_ACR_48_0;
uint32_t HDMI_ACR_48_1;
uint32_t TMDS_CNTL;
uint32_t DP_DB_CNTL;
uint32_t DP_MSA_MISC;
uint32_t DP_MSA_COLORIMETRY;
uint32_t DP_MSA_TIMING_PARAM1;
uint32_t DP_MSA_TIMING_PARAM2;
uint32_t DP_MSA_TIMING_PARAM3;
uint32_t DP_MSA_TIMING_PARAM4;
uint32_t HDMI_DB_CONTROL;
SE_REG_FIELD_LIST_DCN1_0(uint32_t);
};
struct dcn10_stream_encoder {
......@@ -581,4 +450,75 @@ void dcn10_stream_encoder_construct(
const struct dcn10_stream_encoder_shift *se_shift,
const struct dcn10_stream_encoder_mask *se_mask);
void enc1_update_generic_info_packet(
struct dcn10_stream_encoder *enc1,
uint32_t packet_index,
const struct dc_info_packet *info_packet);
void enc1_stream_encoder_dp_set_stream_attribute(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
enum dc_color_space output_color_space);
void enc1_stream_encoder_hdmi_set_stream_attribute(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
int actual_pix_clk_khz,
bool enable_audio);
void enc1_stream_encoder_dvi_set_stream_attribute(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
bool is_dual_link);
void enc1_stream_encoder_set_mst_bandwidth(
struct stream_encoder *enc,
struct fixed31_32 avg_time_slots_per_mtp);
void enc1_stream_encoder_update_dp_info_packets(
struct stream_encoder *enc,
const struct encoder_info_frame *info_frame);
void enc1_stream_encoder_stop_dp_info_packets(
struct stream_encoder *enc);
void enc1_stream_encoder_dp_blank(
struct stream_encoder *enc);
void enc1_stream_encoder_dp_unblank(
struct stream_encoder *enc,
const struct encoder_unblank_param *param);
void enc1_setup_stereo_sync(
struct stream_encoder *enc,
int tg_inst, bool enable);
void enc1_stream_encoder_set_avmute(
struct stream_encoder *enc,
bool enable);
void enc1_se_audio_mute_control(
struct stream_encoder *enc,
bool mute);
void enc1_se_dp_audio_setup(
struct stream_encoder *enc,
unsigned int az_inst,
struct audio_info *info);
void enc1_se_dp_audio_enable(
struct stream_encoder *enc);
void enc1_se_dp_audio_disable(
struct stream_encoder *enc);
void enc1_se_hdmi_audio_setup(
struct stream_encoder *enc,
unsigned int az_inst,
struct audio_info *info,
struct audio_crtc_info *audio_crtc_info);
void enc1_se_hdmi_audio_disable(
struct stream_encoder *enc);
#endif /* __DC_STREAM_ENCODER_DCN10_H__ */
drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
View file @ c5011872
......@@ -191,6 +191,23 @@ enum controller_dp_test_pattern {
CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
};
enum dp_pixel_encoding_type {
DP_PIXEL_ENCODING_TYPE_RGB444 = 0x00000000,
DP_PIXEL_ENCODING_TYPE_YCBCR422 = 0x00000001,
DP_PIXEL_ENCODING_TYPE_YCBCR444 = 0x00000002,
DP_PIXEL_ENCODING_TYPE_RGB_WIDE_GAMUT = 0x00000003,
DP_PIXEL_ENCODING_TYPE_Y_ONLY = 0x00000004,
DP_PIXEL_ENCODING_TYPE_YCBCR420 = 0x00000005
};
enum dp_component_depth {
DP_COMPONENT_PIXEL_DEPTH_6BPC = 0x00000000,
DP_COMPONENT_PIXEL_DEPTH_8BPC = 0x00000001,
DP_COMPONENT_PIXEL_DEPTH_10BPC = 0x00000002,
DP_COMPONENT_PIXEL_DEPTH_12BPC = 0x00000003,
DP_COMPONENT_PIXEL_DEPTH_16BPC = 0x00000004
};
enum dc_lut_mode {
LUT_BYPASS,
LUT_RAM_A,
......
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