Commit c664876c authored by Alexander Graf's avatar Alexander Graf Committed by Avi Kivity

KVM: PPC: Implement mfsr emulation

We emulate the mfsrin instruction already, that passes the SR number
in a register value. But we lacked support for mfsr that encoded the
SR number in the opcode.

So let's implement it.
Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
parent a56cf347
...@@ -35,6 +35,7 @@ ...@@ -35,6 +35,7 @@
#define OP_31_XOP_SLBMTE 402 #define OP_31_XOP_SLBMTE 402
#define OP_31_XOP_SLBIE 434 #define OP_31_XOP_SLBIE 434
#define OP_31_XOP_SLBIA 498 #define OP_31_XOP_SLBIA 498
#define OP_31_XOP_MFSR 595
#define OP_31_XOP_MFSRIN 659 #define OP_31_XOP_MFSRIN 659
#define OP_31_XOP_SLBMFEV 851 #define OP_31_XOP_SLBMFEV 851
#define OP_31_XOP_EIOIO 854 #define OP_31_XOP_EIOIO 854
...@@ -90,6 +91,18 @@ int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu, ...@@ -90,6 +91,18 @@ int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
case OP_31_XOP_MTMSR: case OP_31_XOP_MTMSR:
kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, get_rs(inst))); kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, get_rs(inst)));
break; break;
case OP_31_XOP_MFSR:
{
int srnum;
srnum = kvmppc_get_field(inst, 12 + 32, 15 + 32);
if (vcpu->arch.mmu.mfsrin) {
u32 sr;
sr = vcpu->arch.mmu.mfsrin(vcpu, srnum);
kvmppc_set_gpr(vcpu, get_rt(inst), sr);
}
break;
}
case OP_31_XOP_MFSRIN: case OP_31_XOP_MFSRIN:
{ {
int srnum; int srnum;
......
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