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Commit c805eeb7 authored by Arend van Spriel's avatar Arend van Spriel Committed by John W. Linville
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brcmfmac: restructure brcmf_sdio_chip_recognition() 

Rework function to allow only bcm4329 in case of chip backplane
type being sonics sillicon backplane.
Reviewed-by: default avatarFranky Lin <frankyl@broadcom.com>
Reviewed-by: default avatarHante Meuleman <meuleman@broadcom.com>
Reviewed-by: default avatarPieter-Paul Giesberts <pieterpg@broadcom.com>
Reviewed-by: default avatarDaniel (Deognyoun) Kim <dekim@broadcom.com>
Signed-off-by: default avatarArend van Spriel <arend@broadcom.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 3355650c
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Showing with 167 additions and 167 deletions
drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c
View file @ c805eeb7
...@@ -462,26 +462,55 @@ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev, ...@@ -462,26 +462,55 @@ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev,
struct chip_info *ci) struct chip_info *ci)
{ {
u32 regdata; u32 regdata;
int ret; u32 socitype;
/* Get CC core rev /* Get CC core rev
* Chipid is assume to be at offset 0 from regs arg * Chipid is assume to be at offset 0 from SI_ENUM_BASE
* For different chiptypes or old sdio hosts w/o chipcommon, * For different chiptypes or old sdio hosts w/o chipcommon,
* other ways of recognition should be added here. * other ways of recognition should be added here.
*/ */
ci->c_inf[0].id = BCMA_CORE_CHIPCOMMON;
ci->c_inf[0].base = SI_ENUM_BASE;
regdata = brcmf_sdiod_regrl(sdiodev, regdata = brcmf_sdiod_regrl(sdiodev,
CORE_CC_REG(ci->c_inf[0].base, chipid), CORE_CC_REG(SI_ENUM_BASE, chipid),
NULL); NULL);
ci->chip = regdata & CID_ID_MASK; ci->chip = regdata & CID_ID_MASK;
ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT; ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 && if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 &&
ci->chiprev >= 2) ci->chiprev >= 2)
ci->chip = BCM4339_CHIP_ID; ci->chip = BCM4339_CHIP_ID;
ci->socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT; socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
brcmf_dbg(INFO, "found %s chip: id=0x%x, rev=%d\n",
socitype == SOCI_SB ? "SB" : "AXI", ci->chip, ci->chiprev);
if (socitype == SOCI_SB) {
if (ci->chip != BCM4329_CHIP_ID) {
brcmf_err("SB chip is not supported\n");
return -ENODEV;
}
ci->iscoreup = brcmf_sdio_sb_iscoreup;
ci->corerev = brcmf_sdio_sb_corerev;
ci->coredisable = brcmf_sdio_sb_coredisable;
ci->resetcore = brcmf_sdio_sb_resetcore;
ci->c_inf[0].id = BCMA_CORE_CHIPCOMMON;
ci->c_inf[0].base = SI_ENUM_BASE;
ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
ci->c_inf[1].base = BCM4329_CORE_BUS_BASE;
ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
ci->c_inf[2].base = BCM4329_CORE_SOCRAM_BASE;
ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
ci->c_inf[3].base = BCM4329_CORE_ARM_BASE;
ci->c_inf[4].id = BCMA_CORE_80211;
ci->c_inf[4].base = BCM43xx_CORE_D11_BASE;
ci->ramsize = BCM4329_RAMSIZE;
} else if (socitype == SOCI_AI) {
ci->iscoreup = brcmf_sdio_ai_iscoreup;
ci->corerev = brcmf_sdio_ai_corerev;
ci->coredisable = brcmf_sdio_ai_coredisable;
ci->resetcore = brcmf_sdio_ai_resetcore;
brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev); ci->c_inf[0].id = BCMA_CORE_CHIPCOMMON;
ci->c_inf[0].base = SI_ENUM_BASE;
/* Address of cores for new chips should be added here */ /* Address of cores for new chips should be added here */
switch (ci->chip) { switch (ci->chip) {
...@@ -525,17 +554,6 @@ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev, ...@@ -525,17 +554,6 @@ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev,
ci->c_inf[4].wrapbase = ci->c_inf[4].base + 0x00100000; ci->c_inf[4].wrapbase = ci->c_inf[4].base + 0x00100000;
ci->ramsize = 0x90000; ci->ramsize = 0x90000;
break; break;
case BCM4329_CHIP_ID:
ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
ci->c_inf[1].base = BCM4329_CORE_BUS_BASE;
ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
ci->c_inf[2].base = BCM4329_CORE_SOCRAM_BASE;
ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
ci->c_inf[3].base = BCM4329_CORE_ARM_BASE;
ci->c_inf[4].id = BCMA_CORE_80211;
ci->c_inf[4].base = BCM43xx_CORE_D11_BASE;
ci->ramsize = BCM4329_RAMSIZE;
break;
case BCM4330_CHIP_ID: case BCM4330_CHIP_ID:
ci->c_inf[0].wrapbase = 0x18100000; ci->c_inf[0].wrapbase = 0x18100000;
ci->c_inf[0].cib = 0x27004211; ci->c_inf[0].cib = 0x27004211;
...@@ -593,23 +611,6 @@ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev, ...@@ -593,23 +611,6 @@ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev,
ci->ramsize = 0xc0000; ci->ramsize = 0xc0000;
ci->rambase = 0x180000; ci->rambase = 0x180000;
break; break;
case BCM4339_CHIP_ID:
ci->c_inf[0].wrapbase = 0x18100000;
ci->c_inf[0].cib = 0x2e084411;
ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
ci->c_inf[1].base = 0x18005000;
ci->c_inf[1].wrapbase = 0x18105000;
ci->c_inf[1].cib = 0x15004211;
ci->c_inf[2].id = BCMA_CORE_ARM_CR4;
ci->c_inf[2].base = 0x18002000;
ci->c_inf[2].wrapbase = 0x18102000;
ci->c_inf[2].cib = 0x04084411;
ci->c_inf[3].id = BCMA_CORE_80211;
ci->c_inf[3].base = BCM43xx_CORE_D11_BASE;
ci->c_inf[3].wrapbase = ci->c_inf[3].base + 0x00100000;
ci->ramsize = 0xc0000;
ci->rambase = 0x180000;
break;
case BCM43362_CHIP_ID: case BCM43362_CHIP_ID:
ci->c_inf[0].wrapbase = 0x18100000; ci->c_inf[0].wrapbase = 0x18100000;
ci->c_inf[0].cib = 0x27004211; ci->c_inf[0].cib = 0x27004211;
...@@ -630,34 +631,34 @@ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev, ...@@ -630,34 +631,34 @@ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev,
ci->c_inf[4].wrapbase = ci->c_inf[4].base + 0x00100000; ci->c_inf[4].wrapbase = ci->c_inf[4].base + 0x00100000;
ci->ramsize = 0x3C000; ci->ramsize = 0x3C000;
break; break;
case BCM4339_CHIP_ID:
ci->c_inf[0].wrapbase = 0x18100000;
ci->c_inf[0].cib = 0x2e084411;
ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
ci->c_inf[1].base = 0x18005000;
ci->c_inf[1].wrapbase = 0x18105000;
ci->c_inf[1].cib = 0x15004211;
ci->c_inf[2].id = BCMA_CORE_ARM_CR4;
ci->c_inf[2].base = 0x18002000;
ci->c_inf[2].wrapbase = 0x18102000;
ci->c_inf[2].cib = 0x04084411;
ci->c_inf[3].id = BCMA_CORE_80211;
ci->c_inf[3].base = BCM43xx_CORE_D11_BASE;
ci->c_inf[3].wrapbase = ci->c_inf[3].base + 0x00100000;
ci->ramsize = 0xc0000;
ci->rambase = 0x180000;
break;
default: default:
brcmf_err("chipid 0x%x is not supported\n", ci->chip); brcmf_err("AXI chip is not supported\n");
return -ENODEV; return -ENODEV;
} }
} else {
ret = brcmf_sdio_chip_cichk(ci); brcmf_err("chip backplane type %u is not supported\n",
if (ret) socitype);
return ret;
switch (ci->socitype) {
case SOCI_SB:
ci->iscoreup = brcmf_sdio_sb_iscoreup;
ci->corerev = brcmf_sdio_sb_corerev;
ci->coredisable = brcmf_sdio_sb_coredisable;
ci->resetcore = brcmf_sdio_sb_resetcore;
break;
case SOCI_AI:
ci->iscoreup = brcmf_sdio_ai_iscoreup;
ci->corerev = brcmf_sdio_ai_corerev;
ci->coredisable = brcmf_sdio_ai_coredisable;
ci->resetcore = brcmf_sdio_ai_resetcore;
break;
default:
brcmf_err("socitype %u not supported\n", ci->socitype);
return -ENODEV; return -ENODEV;
} }
return 0; return brcmf_sdio_chip_cichk(ci);
} }
static int static int
......
drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.h
View file @ c805eeb7
...@@ -66,7 +66,6 @@ struct chip_core_info { ...@@ -66,7 +66,6 @@ struct chip_core_info {
struct chip_info { struct chip_info {
u32 chip; u32 chip;
u32 chiprev; u32 chiprev;
u32 socitype;
/* core info */ /* core info */
/* always put chipcommon core at 0, bus core at 1 */ /* always put chipcommon core at 0, bus core at 1 */
struct chip_core_info c_inf[BRCMF_MAX_CORENUM]; struct chip_core_info c_inf[BRCMF_MAX_CORENUM];
......
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