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Commit ca927387 authored by Tony Lindgren's avatar Tony Lindgren Committed by Russell King
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[ARM PATCH] 1780/1: Add TI OMAP support, include files 

Patch from Tony Lindgren

This patch adds the include files for Texas Instruments OMAP-1510 and 
1610 processors. 

OMAP is an embedded ARM processor with integrated DSP.

OMAP-1610 has hardware support for USB OTG, which might be of interest
to Linux developers. OMAP-1610 could be easily be used as development 
platform to add USB OTG support to Linux.

This patch is an updated version of patch 1768/1 with Russell King's
comments fixed. This patch requires patch 1777/1 applied.

This patch is brought to you by various linux-omap developers.
parent 58486ae8
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include/asm-arm/arch-omap/bus.h 0 → 100644
View file @ ca927387
/*
* linux/include/asm-arm/arch-omap/bus.h
*
* Virtual bus for OMAP. Allows better power management, such as managing
* shared clocks, and mapping of bus addresses to Local Bus addresses.
*
* See drivers/usb/host/ohci-omap.c or drivers/video/omap/omapfb.c for
* examples on how to register drivers to this bus.
*
* Copyright (C) 2003 - 2004 Nokia Corporation
* Written by Tony Lindgren <tony@atomide.com>
* Portions of code based on sa1111.c.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARM_ARCH_OMAP_BUS_H
#define __ASM_ARM_ARCH_OMAP_BUS_H
extern struct bus_type omap_bus_types[];
/*
* Description for physical device
*/
struct omap_dev {
struct device dev; /* Standard device description */
char *name;
unsigned int devid; /* OMAP device id */
unsigned int busid; /* OMAP virtual busid */
struct resource res; /* Standard resource description */
void *mapbase; /* OMAP physical address */
unsigned int irq[6]; /* OMAP interrupts */
u64 *dma_mask; /* Used by USB OHCI only */
};
#define OMAP_DEV(_d) container_of((_d), struct omap_dev, dev)
#define omap_get_drvdata(d) dev_get_drvdata(&(d)->dev)
#define omap_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
/*
* Description for device driver
*/
struct omap_driver {
struct device_driver drv; /* Standard driver description */
unsigned int devid; /* OMAP device id for bus */
unsigned int busid; /* OMAP virtual busid */
unsigned int clocks; /* OMAP shared clocks */
int (*probe)(struct omap_dev *);
int (*remove)(struct omap_dev *);
int (*suspend)(struct omap_dev *, u32);
int (*resume)(struct omap_dev *);
};
#define OMAP_DRV(_d) container_of((_d), struct omap_driver, drv)
#define OMAP_DRIVER_NAME(_omapdev) ((_omapdev)->dev.driver->name)
/*
* Device ID numbers for bus types
*/
#define OMAP_OCP_DEVID_USB 0
#define OMAP_TIPB_DEVID_LCD 1
#define OMAP_TIPB_DEVID_MMC 2
/*
* Virtual bus definitions for OMAP
*/
#define OMAP_NR_BUSES 2
#define OMAP_BUS_NAME_TIPB "tipb"
#define OMAP_BUS_NAME_LBUS "lbus"
enum {
OMAP_BUS_TIPB = 0,
OMAP_BUS_LBUS,
};
/* See arch/arm/mach-omap/bus.c for the rest of the bus definitions. */
extern int omap_driver_register(struct omap_driver *driver);
extern void omap_driver_unregister(struct omap_driver *driver);
extern int omap_device_register(struct omap_dev *odev);
extern void omap_device_unregister(struct omap_dev *odev);
#endif
include/asm-arm/arch-omap/clocks.h 0 → 100644
View file @ ca927387
/*
* OMAP clock interface
*
* Copyright (C) 2001 RidgeRun, Inc
* Written by Gordon McNutt <gmcnutt@ridgerun.com>
* Updated 2004 for Linux 2.6 by Tony Lindgren <tony@atomide.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARM_CLOCKS_H
#define __ASM_ARM_CLOCKS_H
#include <linux/config.h>
/* ARM_CKCTL bit shifts */
#define PERDIV 0
#define LCDDIV 2
#define ARMDIV 4
#define DSPDIV 6
#define TCDIV 8
#define DSPMMUDIV 10
#define ARM_TIMXO 12
#define EN_DSPCK 13
#define ARM_INTHCK_SEL 14 /* REVISIT: Where is this used? */
/* ARM_IDLECT1 bit shifts */
#define IDLWDT_ARM 0
#define IDLXORP_ARM 1
#define IDLPER_ARM 2
#define IDLLCD_ARM 3
#define IDLLB_ARM 4
#define IDLHSAB_ARM 5
#define IDLIF_ARM 6
#define IDLDPLL_ARM 7
#define IDLAPI_ARM 8
#define IDLTIM_ARM 9
#define SETARM_IDLE 11
/* ARM_IDLECT2 bit shifts */
#define EN_WDTCK 0
#define EN_XORPCK 1
#define EN_PERCK 2
#define EN_LCDCK 3
#define EN_LBCK 4
#define EN_HSABCK 5
#define EN_APICK 6
#define EN_TIMCK 7
#define DMACK_REQ 8
#define EN_GPIOCK 9
#define EN_LBFREECK 10
/*
* OMAP clocks
*/
typedef enum {
/* Fixed system clock */
OMAP_CLKIN = 0,
/* DPLL1 */
OMAP_CK_GEN1, OMAP_CK_GEN2, OMAP_CK_GEN3,
/* TC usually needs to be checked before anything else */
OMAP_TC_CK,
/* CLKM1 */
OMAP_ARM_CK, OMAP_MPUPER_CK, OMAP_ARM_GPIO_CK, OMAP_MPUXOR_CK,
OMAP_MPUTIM_CK, OMAP_MPUWD_CK,
/* CLKM2 */
OMAP_DSP_CK, OMAP_DSPMMU_CK,
#if 0
/* Accessible only from the dsp */
OMAP_DSPPER_CK, OMAP_GPIO_CK, OMAP_DSPXOR_CK, OMAP_DSPTIM_CK,
OMAP_DSPWD_CK, OMAP_UART_CK,
#endif
/* CLKM3 */
OMAP_DMA_CK, OMAP_API_CK, OMAP_HSAB_CK, OMAP_LBFREE_CK,
OMAP_LB_CK, OMAP_LCD_CK
} ck_t;
typedef enum {
/* Reset the MPU */
OMAP_ARM_RST,
/* Reset the DSP */
OMAP_DSP_RST,
/* Reset priority registers, EMIF config, and MPUI control logic */
OMAP_API_RST,
/* Reset DSP, MPU, and Peripherals */
OMAP_SW_RST,
} reset_t;
#define OMAP_CK_MIN OMAP_CLKIN
#define OMAP_CK_MAX OMAP_LCD_CK
#if defined(CONFIG_OMAP_ARM_30MHZ)
#define OMAP_CK_MAX_RATE 30
#elif defined(CONFIG_OMAP_ARM_60MHZ)
#define OMAP_CK_MAX_RATE 60
#elif defined(CONFIG_OMAP_ARM_96MHZ)
#define OMAP_CK_MAX_RATE 96
#elif defined(CONFIG_OMAP_ARM_120MHZ)
#define OMAP_CK_MAX_RATE 120
#elif defined(CONFIG_OMAP_ARM_168MHZ)
#define OMAP_CK_MAX_RATE 168
#elif defined(CONFIG_OMAP_ARM_182MHZ)
#define OMAP_CK_MAX_RATE 182
#elif defined(CONFIG_OMAP_ARM_192MHZ)
#define OMAP_CK_MAX_RATE 192
#elif defined(CONFIG_OMAP_ARM_195MHZ)
#define OMAP_CK_MAX_RATE 195
#endif
#define CK_DPLL_MASK 0x0fe0
/* Shared by CK and DSPC */
#define MPUI_STROBE_MAX_1509 24
#define MPUI_STROBE_MAX_1510 30
/*
* ----------------------------------------------------------------------------
* Clock interface functions
* ----------------------------------------------------------------------------
*/
/* Clock initialization. */
int init_ck(void);
/*
* For some clocks you have a choice of which "parent" clocks they are derived
* from. Use this to select a "parent". See the platform documentation for
* valid combinations.
*/
int ck_can_set_input(ck_t);
int ck_set_input(ck_t ck, ck_t input);
int ck_get_input(ck_t ck, ck_t *input);
/*
* Use this to set a clock rate. If other clocks are derived from this one,
* their rates will all change too. If this is a derived clock and I can't
* change it to match your request unless I also change the parent clock, then
* tough luck -- I won't change the parent automatically. I'll return an error
* if I can't get the clock within 10% of what you want. Otherwise I'll return
* the value I actually set it to. If I have to switch parents to get the rate
* then I will do this automatically (since it only affects this clock and its
* descendants).
*/
int ck_can_set_rate(ck_t);
int ck_set_rate(ck_t ck, int val_in_mhz);
int ck_get_rate(ck_t ck);
/*
* Use this to get a bitmap of available rates for the clock. Caller allocates
* the buffer and passes in the length. Clock module fills up to len bytes of
* the buffer & passes back actual bytes used.
*/
int ck_get_rates(ck_t ck, void *buf, int len);
int ck_valid_rate(int rate);
/*
* Idle a clock. What happens next depends on the clock ;). For example, if
* you idle the ARM_CK you might well end up in sleep mode on some platforms.
* If you try to idle a clock that doesn't support it I'll return an error.
* Note that idling a clock does not always take affect until certain h/w
* conditions are met. Consult the platform specs to learn more.
*/
int ck_can_idle(ck_t);
int ck_idle(ck_t);
int ck_activate(ck_t);
int ck_is_idle(ck_t);
/*
* Enable/disable a clock. I'll return an error if the h/w doesn't support it.
* If you disable a clock being used by an active device then you probably
* just screwed it. YOU are responsible for making sure this doesn't happen.
*/
int ck_can_disable(ck_t);
int ck_enable(ck_t);
int ck_disable(ck_t);
int ck_is_enabled(ck_t);
/* Enable/reset ARM peripherals (remove/set reset signal) */
void ck_enable_peripherals(void);
void ck_reset_peripherals(void);
/* Generate/clear a MPU or DSP reset */
void ck_generate_reset(reset_t reset);
void ck_release_from_reset(reset_t reset);
/* This gets a string representation of the clock's name. Useful for proc. */
char *ck_get_name(ck_t);
extern void start_mputimer1(unsigned long);
#endif
include/asm-arm/arch-omap/dma.h 0 → 100644
View file @ ca927387
/*
* linux/include/asm-arm/arch-omap/dma.h
*
* Copyright (C) 2003 Nokia Corporation
* Author: Juha Yrjl <juha.yrjola@nokia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
#define MAX_DMA_ADDRESS 0xffffffff
#define OMAP_LOGICAL_DMA_CH_COUNT 17
#define OMAP_DMA_NO_DEVICE 0
#define OMAP_DMA_MCSI1_TX 1
#define OMAP_DMA_MCSI1_RX 2
#define OMAP_DMA_I2C_RX 3
#define OMAP_DMA_I2C_TX 4
#define OMAP_DMA_EXT_NDMA_REQ 5
#define OMAP_DMA_EXT_NDMA_REQ2 6
#define OMAP_DMA_UWIRE_TX 7
#define OMAP_DMA_MCBSP1_DMA_TX 8
#define OMAP_DMA_MCBSP1_DMA_RX 9
#define OMAP_DMA_MCBSP3_DMA_TX 10
#define OMAP_DMA_MCBSP3_DMA_RX 11
#define OMAP_DMA_UART1_TX 12
#define OMAP_DMA_UART1_RX 13
#define OMAP_DMA_UART2_TX 14
#define OMAP_DMA_UART2_RX 15
#define OMAP_DMA_MCBSP2_TX 16
#define OMAP_DMA_MCBSP2_RX 17
#define OMAP_DMA_UART3_TX 18
#define OMAP_DMA_UART3_RX 19
#define OMAP_DMA_CAMERA_IF_RX 20
#define OMAP_DMA_MMC_TX 21
#define OMAP_DMA_MMC_RX 22
#define OMAP_DMA_NAND 23
#define OMAP_DMA_IRQ_LCD_LINE 24
#define OMAP_DMA_MEMORY_STICK 25
#define OMAP_DMA_USB_W2FC_RX0 26
#define OMAP_DMA_USB_W2FC_RX1 27
#define OMAP_DMA_USB_W2FC_RX2 28
#define OMAP_DMA_USB_W2FC_TX0 29
#define OMAP_DMA_USB_W2FC_TX1 30
#define OMAP_DMA_USB_W2FC_TX2 31
/* These are only for 1610 */
#define OMAP_DMA_CRYPTO_DES_IN 32
#define OMAP_DMA_SPI_TX 33
#define OMAP_DMA_SPI_RX 34
#define OMAP_DMA_CRYPTO_HASH 35
#define OMAP_DMA_CCP_ATTN 36
#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
#define OMAP_DMA_CMT_APE_TX_CHAN_0 38
#define OMAP_DMA_CMT_APE_RV_CHAN_0 39
#define OMAP_DMA_CMT_APE_TX_CHAN_1 40
#define OMAP_DMA_CMT_APE_RV_CHAN_1 41
#define OMAP_DMA_CMT_APE_TX_CHAN_2 42
#define OMAP_DMA_CMT_APE_RV_CHAN_2 43
#define OMAP_DMA_CMT_APE_TX_CHAN_3 44
#define OMAP_DMA_CMT_APE_RV_CHAN_3 45
#define OMAP_DMA_CMT_APE_TX_CHAN_4 46
#define OMAP_DMA_CMT_APE_RV_CHAN_4 47
#define OMAP_DMA_CMT_APE_TX_CHAN_5 48
#define OMAP_DMA_CMT_APE_RV_CHAN_5 49
#define OMAP_DMA_CMT_APE_TX_CHAN_6 50
#define OMAP_DMA_CMT_APE_RV_CHAN_6 51
#define OMAP_DMA_CMT_APE_TX_CHAN_7 52
#define OMAP_DMA_CMT_APE_RV_CHAN_7 53
#define OMAP_DMA_MMC2_TX 54
#define OMAP_DMA_MMC2_RX 55
#define OMAP_DMA_CRYPTO_DES_OUT 56
#define OMAP_DMA_BASE 0xfffed800
#define OMAP_DMA_GCR_REG (OMAP_DMA_BASE + 0x400)
#define OMAP_DMA_GSCR_REG (OMAP_DMA_BASE + 0x404)
#define OMAP_DMA_GRST_REG (OMAP_DMA_BASE + 0x408)
#define OMAP_DMA_HW_ID_REG (OMAP_DMA_BASE + 0x442)
#define OMAP_DMA_PCH2_ID_REG (OMAP_DMA_BASE + 0x444)
#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446)
#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448)
#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a)
#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c)
#define OMAP_DMA_CAPS_0_U_REG (OMAP_DMA_BASE + 0x44e)
#define OMAP_DMA_CAPS_0_L_REG (OMAP_DMA_BASE + 0x450)
#define OMAP_DMA_CAPS_1_U_REG (OMAP_DMA_BASE + 0x452)
#define OMAP_DMA_CAPS_1_L_REG (OMAP_DMA_BASE + 0x454)
#define OMAP_DMA_CAPS_2_REG (OMAP_DMA_BASE + 0x456)
#define OMAP_DMA_CAPS_3_REG (OMAP_DMA_BASE + 0x458)
#define OMAP_DMA_CAPS_4_REG (OMAP_DMA_BASE + 0x45a)
#define OMAP_DMA_PCH2_SR_REG (OMAP_DMA_BASE + 0x460)
#define OMAP_DMA_PCH0_SR_REG (OMAP_DMA_BASE + 0x480)
#define OMAP_DMA_PCH1_SR_REG (OMAP_DMA_BASE + 0x482)
#define OMAP_DMA_PCHD_SR_REG (OMAP_DMA_BASE + 0x4c0)
#define OMAP1510_DMA_LCD_CTRL 0xfffedb00
#define OMAP1510_DMA_LCD_TOP_F1_L 0xfffedb02
#define OMAP1510_DMA_LCD_TOP_F1_U 0xfffedb04
#define OMAP1510_DMA_LCD_BOT_F1_L 0xfffedb06
#define OMAP1510_DMA_LCD_BOT_F1_U 0xfffedb08
#define OMAP1610_DMA_LCD_CSDP 0xfffee3c0
#define OMAP1610_DMA_LCD_CCR 0xfffee3c2
#define OMAP1610_DMA_LCD_CTRL 0xfffee3c4
#define OMAP1610_DMA_LCD_TOP_B1_L 0xfffee3c8
#define OMAP1610_DMA_LCD_TOP_B1_U 0xfffee3ca
#define OMAP1610_DMA_LCD_BOT_B1_L 0xfffee3cc
#define OMAP1610_DMA_LCD_BOT_B1_U 0xfffee3ce
#define OMAP1610_DMA_LCD_TOP_B2_L 0xfffee3d0
#define OMAP1610_DMA_LCD_TOP_B2_U 0xfffee3d2
#define OMAP1610_DMA_LCD_BOT_B2_L 0xfffee3d4
#define OMAP1610_DMA_LCD_BOT_B2_U 0xfffee3d6
#define OMAP1610_DMA_LCD_SRC_EI_B1 0xfffee3d8
#define OMAP1610_DMA_LCD_SRC_FI_B1_L 0xfffee3da
#define OMAP1610_DMA_LCD_SRC_EN_B1 0xfffee3e0
#define OMAP1610_DMA_LCD_SRC_FN_B1 0xfffee3e4
#define OMAP1610_DMA_LCD_LCH_CTRL 0xfffee3ea
#define OMAP1610_DMA_LCD_SRC_FI_B1_U 0xfffee3f4
/* Every LCh has its own set of the registers below */
#define OMAP_DMA_CSDP_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x00)
#define OMAP_DMA_CCR_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x02)
#define OMAP_DMA_CICR_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x04)
#define OMAP_DMA_CSR_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x06)
#define OMAP_DMA_CSSA_L_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x08)
#define OMAP_DMA_CSSA_U_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
#define OMAP_DMA_CDSA_L_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
#define OMAP_DMA_CDSA_U_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
#define OMAP_DMA_CEN_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x10)
#define OMAP_DMA_CFN_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x12)
#define OMAP_DMA_CSFI_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x14)
#define OMAP_DMA_CSEI_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x16)
#define OMAP_DMA_CSAC_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x18)
#define OMAP_DMA_CDAC_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
#define OMAP_DMA_CDEI_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
#define OMAP_DMA_CDFI_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
#define OMAP_DMA_COLOR_L_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x20)
#define OMAP_DMA_COLOR_U_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x22)
#define OMAP_DMA_CCR2_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x24)
#define OMAP_DMA_CLNK_CTRL_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x28)
#define OMAP_DMA_LCH_CTRL_REG(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
#define OMAP_DMA_TOUT_IRQ (1 << 0)
#define OMAP_DMA_DROP_IRQ (1 << 1)
#define OMAP_DMA_HALF_IRQ (1 << 2)
#define OMAP_DMA_FRAME_IRQ (1 << 3)
#define OMAP_DMA_LAST_IRQ (1 << 4)
#define OMAP_DMA_BLOCK_IRQ (1 << 5)
#define OMAP_DMA_SYNC_IRQ (1 << 6)
#define OMAP_DMA_DATA_TYPE_S8 0x00
#define OMAP_DMA_DATA_TYPE_S16 0x01
#define OMAP_DMA_DATA_TYPE_S32 0x02
#define OMAP_DMA_SYNC_ELEMENT 0x00
#define OMAP_DMA_SYNC_FRAME 0x01
#define OMAP_DMA_SYNC_BLOCK 0x02
#define OMAP_DMA_PORT_EMIFF 0x00
#define OMAP_DMA_PORT_EMIFS 0x01
#define OMAP_DMA_PORT_OCP_T1 0x02
#define OMAP_DMA_PORT_TIPB 0x03
#define OMAP_DMA_PORT_OCP_T2 0x04
#define OMAP_DMA_PORT_MPUI 0x05
#define OMAP_DMA_AMODE_CONSTANT 0x00
#define OMAP_DMA_AMODE_POST_INC 0x01
#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
/* LCD DMA block numbers */
enum {
OMAP_LCD_DMA_B1_TOP,
OMAP_LCD_DMA_B1_BOTTOM,
OMAP_LCD_DMA_B2_TOP,
OMAP_LCD_DMA_B2_BOTTOM
};
extern int omap_request_dma(int dev_id, const char *dev_name,
void (* callback)(int lch, u16 ch_status, void *data),
void *data, int *dma_ch);
extern void omap_enable_dma_irq(int ch, u16 irq_bits);
extern void omap_disable_dma_irq(int ch, u16 irq_bits);
extern void omap_free_dma(int ch);
extern void omap_start_dma(int lch);
extern void omap_stop_dma(int lch);
extern void omap_set_dma_transfer_params(int lch, int data_type,
int elem_count, int frame_count,
int sync_mode);
extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
unsigned long src_start);
extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
unsigned long dest_start);
/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
extern int omap_dma_in_1510_mode(void);
/* LCD DMA functions */
extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
void *data);
extern void omap_free_lcd_dma(void);
extern void omap_start_lcd_dma(void);
extern void omap_stop_lcd_dma(void);
extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
int data_type);
extern void omap_set_lcd_dma_b1_rotation(int rotate);
#endif /* __ASM_ARCH_DMA_H */
include/asm-arm/arch-omap/fpga.h 0 → 100644
View file @ ca927387
/*
* linux/include/asm-arm/arch-omap/fpga.h
*
* Interrupt handler for OMAP-1510 FPGA
*
* Copyright (C) 2001 RidgeRun, Inc.
* Author: Greg Lonnon <glonnon@ridgerun.com>
*
* Copyright (C) 2002 MontaVista Software, Inc.
*
* Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
* Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_OMAP_FPGA_H
#define __ASM_ARCH_OMAP_FPGA_H
extern void fpga_init_irq(void);
extern unsigned char fpga_read(int reg);
extern void fpga_write(unsigned char val, int reg);
#endif
include/asm-arm/arch-omap/gpio.h 0 → 100644
View file @ ca927387
/*
* linux/include/asm-arm/arch-omap/gpio.h
*
* OMAP GPIO handling defines and functions
*
* Copyright (C) 2003 Nokia Corporation
*
* Written by Juha Yrjl <juha.yrjola@nokia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __ASM_ARCH_OMAP_GPIO_H
#define __ASM_ARCH_OMAP_GPIO_H
#include <asm/arch/hardware.h>
#include <asm/arch/irqs.h>
#include <asm/io.h>
#define OMAP_MPUIO_BASE 0xfffb5000
#define OMAP_MPUIO_INPUT_LATCH 0x00
#define OMAP_MPUIO_OUTPUT_REG 0x04
#define OMAP_MPUIO_IO_CNTL 0x08
#define OMAP_MPUIO_KBR_LATCH 0x10
#define OMAP_MPUIO_KBC_REG 0x14
#define OMAP_MPUIO_GPIO_EVENT_MODE_REG 0x18
#define OMAP_MPUIO_GPIO_INT_EDGE_REG 0x1c
#define OMAP_MPUIO_KBD_INT 0x20
#define OMAP_MPUIO_GPIO_INT 0x24
#define OMAP_MPUIO_KBD_MASKIT 0x28
#define OMAP_MPUIO_GPIO_MASKIT 0x2c
#define OMAP_MPUIO_GPIO_DEBOUNCING_REG 0x30
#define OMAP_MPUIO_LATCH_REG 0x34
#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
#define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ? \
IH_MPUIO_BASE + ((nr) & 0x0f) : \
IH_GPIO_BASE + ((nr) & 0x3f))
/* For EDGECTRL */
#define OMAP_GPIO_NO_EDGE 0x00
#define OMAP_GPIO_FALLING_EDGE 0x01
#define OMAP_GPIO_RISING_EDGE 0x02
#define OMAP_GPIO_BOTH_EDGES 0x03
extern int omap_request_gpio(int gpio);
extern void omap_free_gpio(int gpio);
extern void omap_set_gpio_direction(int gpio, int is_input);
extern void omap_set_gpio_dataout(int gpio, int enable);
extern int omap_get_gpio_datain(int gpio);
extern void omap_set_gpio_edge_ctrl(int gpio, int edge);
#endif
include/asm-arm/arch-omap/hardware.h 0 → 100644
View file @ ca927387
/*
* linux/include/asm-arm/arch-omap/hardware.h
*
* Hardware definitions for TI OMAP processors and boards
*
* NOTE: Please put device driver specific defines into a separate header
* file for each driver.
*
* Copyright (C) 2001 RidgeRun, Inc.
* Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
*
* Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_OMAP_HARDWARE_H
#define __ASM_ARCH_OMAP_HARDWARE_H
#include <asm/sizes.h>
#include <linux/config.h>
#ifndef __ASSEMBLER__
#include <asm/types.h>
#endif
#include <asm/mach-types.h>
/*
* ----------------------------------------------------------------------------
* I/O mapping
* ----------------------------------------------------------------------------
*/
#define IO_BASE 0xFFFB0000 /* Virtual */
#define IO_SIZE 0x40000
#define IO_START 0xFFFB0000 /* Physical */
#define PCIO_BASE 0
#define IO_ADDRESS(x) ((x))
/*
* ---------------------------------------------------------------------------
* Processor differentiation
* ---------------------------------------------------------------------------
*/
#ifdef CONFIG_ARCH_OMAP730
#include "omap730.h"
#define cpu_is_omap730() (1)
#else
#define cpu_is_omap730() (0)
#endif
#ifdef CONFIG_ARCH_OMAP1510
#include "omap1510.h"
#define cpu_is_omap1510() (1)
#else
#define cpu_is_omap1510() (0)
#endif
#ifdef CONFIG_ARCH_OMAP1610
#include "omap1610.h"
#define cpu_is_omap1610() (1)
#else
#define cpu_is_omap1610() (0)
#endif
/*
* ---------------------------------------------------------------------------
* Board differentiation
* ---------------------------------------------------------------------------
*/
#ifdef CONFIG_OMAP_INNOVATOR
#include "omap-innovator.h"
#define omap_is_innovator() (1)
#else
#define omap_is_innovator() (0)
#endif
#ifdef CONFIG_MACH_OMAP_H2
#include "omap-h2.h"
#define omap_is_h2() (1)
#else
#define omap_is_h2() (0)
#endif
#ifdef CONFIG_MACH_OMAP_PERSEUS2
#include "omap-perseus2.h"
#define omap_is_perseus2() (1)
#else
#define omap_is_perseus2() (0)
#endif
/*
* ---------------------------------------------------------------------------
* Common definitions for all OMAP processors
* NOTE: Put all processor or board specific parts to the special header
* files.
* ---------------------------------------------------------------------------
*/
/*
* ----------------------------------------------------------------------------
* Base addresses
* ----------------------------------------------------------------------------
*/
/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
#define OMAP_DSP_BASE 0xE0000000
#define OMAP_DSP_SIZE 0x50000
#define OMAP_DSP_START 0xE0000000
#define OMAP_DSPREG_BASE 0xE1000000
#define OMAP_DSPREG_SIZE SZ_128K
#define OMAP_DSPREG_START 0xE1000000
/*
* ----------------------------------------------------------------------------
* Clocks
* ----------------------------------------------------------------------------
*/
#define CLKGEN_RESET_BASE (0xfffece00)
#define ARM_CKCTL (volatile __u16 *)(CLKGEN_RESET_BASE + 0x0)
#define ARM_IDLECT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x4)
#define ARM_IDLECT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x8)
#define ARM_EWUPCT (volatile __u16 *)(CLKGEN_RESET_BASE + 0xC)
#define ARM_RSTCT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x10)
#define ARM_RSTCT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x14)
#define ARM_SYSST (volatile __u16 *)(CLKGEN_RESET_BASE + 0x18)
#define CK_RATEF 1
#define CK_IDLEF 2
#define CK_ENABLEF 4
#define CK_SELECTF 8
#define SETARM_IDLE_SHIFT
/* DPLL control registers */
#define DPLL_CTL_REG (volatile __u16 *)(0xfffecf00)
#define CK_DPLL1 (volatile __u16 *)(0xfffecf00)
/* ULPD */
#define ULPD_REG_BASE (0xfffe0800)
#define ULPD_IT_STATUS_REG (volatile __u16 *)(ULPD_REG_BASE + 0x14)
#define ULPD_CLOCK_CTRL_REG (volatile __u16 *)(ULPD_REG_BASE + 0x30)
#define ULPD_SOFT_REQ_REG (volatile __u16 *)(ULPD_REG_BASE + 0x34)
#define ULPD_DPLL_CTRL_REG (volatile __u16 *)(ULPD_REG_BASE + 0x3c)
#define ULPD_STATUS_REQ_REG (volatile __u16 *)(ULPD_REG_BASE + 0x40)
#define ULPD_APLL_CTRL_REG (volatile __u16 *)(ULPD_REG_BASE + 0x4c)
#define ULPD_POWER_CTRL_REG (volatile __u16 *)(ULPD_REG_BASE + 0x50)
#define ULPD_CAM_CLK_CTRL_REG (volatile __u16 *)(ULPD_REG_BASE + 0x7c)
/*
* ---------------------------------------------------------------------------
* Timers
* ---------------------------------------------------------------------------
*/
#define OMAP_32kHz_TIMER_BASE 0xfffb9000
/* 32k Timer Registers */
#define TIMER32k_CR 0x08
#define TIMER32k_TVR 0x00
#define TIMER32k_TCR 0x04
/* 32k Timer Control Register definition */
#define TIMER32k_TSS (1<<0)
#define TIMER32k_TRB (1<<1)
#define TIMER32k_INT (1<<2)
#define TIMER32k_ARL (1<<3)
/* MPU Timer base addresses */
#define OMAP_MPUTIMER_BASE 0xfffec500
#define OMAP_MPUTIMER_OFF 0x00000100
#define OMAP_TIMER1_BASE 0xfffec500
#define OMAP_TIMER2_BASE 0xfffec600
#define OMAP_TIMER3_BASE 0xfffec700
#define OMAP_WATCHDOG_BASE 0xfffec800
/* MPU Timer Registers */
#define CNTL_TIMER 0
#define LOAD_TIM 4
#define READ_TIM 8
/* CNTL_TIMER register bits */
#define MPUTIM_FREE (1<<6)
#define MPUTIM_CLOCK_ENABLE (1<<5)
#define MPUTIM_PTV_MASK (0x7<<PTV_BIT)
#define MPUTIM_PTV_BIT 2
#define MPUTIM_AR (1<<1)
#define MPUTIM_ST (1<<0)
/*
* ---------------------------------------------------------------------------
* Interrupts
* ---------------------------------------------------------------------------
*/
#define OMAP_IH1_BASE 0xfffecb00
#define OMAP_IH2_BASE 0xfffe0000
#define OMAP_ITR 0x0
#define OMAP_MASK 0x4
#define IRQ_ITR 0x00
#define IRQ_MIR 0x04
#define IRQ_SIR_IRQ 0x10
#define IRQ_SIR_FIQ 0x14
#define IRQ_CONTROL_REG 0x18
#define IRQ_ISR 0x9c
#define IRQ_ILR0 0x1c
/* OMAP-1610 specific interrupt handler registers */
#define OMAP_IH2_SECT1 (OMAP_IH2_BASE)
#define OMAP_IH2_SECT2 (OMAP_IH2_BASE + 0x100)
#define OMAP_IH2_SECT3 (OMAP_IH2_BASE + 0x200)
#define OMAP_IH2_SECT4 (OMAP_IH2_BASE + 0x300)
/*
* ---------------------------------------------------------------------------
* Traffic controller memory interface
* ---------------------------------------------------------------------------
*/
#define TCMIF_BASE 0xfffecc00
#define IMIF_PRIO (TCMIF_BASE + 0x00)
#define EMIFS_PRIO_REG (TCMIF_BASE + 0x04)
#define EMIFF_PRIO_REG (TCMIF_BASE + 0x08)
#define EMIFS_CONFIG_REG (TCMIF_BASE + 0x0c)
#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10)
#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14)
#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18)
#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c)
#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20)
#define EMIFF_MRS (TCMIF_BASE + 0x24)
#define TC_TIMEOUT1 (TCMIF_BASE + 0x28)
#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c)
#define TC_TIMEOUT3 (TCMIF_BASE + 0x30)
#define TC_ENDIANISM (TCMIF_BASE + 0x34)
#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c)
#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40)
/*
* ----------------------------------------------------------------------------
* System control registers
* ----------------------------------------------------------------------------
*/
#define MOD_CONF_CTRL_0 0xfffe1080
/*
* ----------------------------------------------------------------------------
* Pin multiplexing registers
* ----------------------------------------------------------------------------
*/
#define FUNC_MUX_CTRL_0 0xfffe1000
#define FUNC_MUX_CTRL_1 0xfffe1004
#define FUNC_MUX_CTRL_2 0xfffe1008
#define COMP_MODE_CTRL_0 0xfffe100c
#define FUNC_MUX_CTRL_3 0xfffe1010
#define FUNC_MUX_CTRL_4 0xfffe1014
#define FUNC_MUX_CTRL_5 0xfffe1018
#define FUNC_MUX_CTRL_6 0xfffe101C
#define FUNC_MUX_CTRL_7 0xfffe1020
#define FUNC_MUX_CTRL_8 0xfffe1024
#define FUNC_MUX_CTRL_9 0xfffe1028
#define FUNC_MUX_CTRL_A 0xfffe102C
#define FUNC_MUX_CTRL_B 0xfffe1030
#define FUNC_MUX_CTRL_C 0xfffe1034
#define FUNC_MUX_CTRL_D 0xfffe1038
#define PULL_DWN_CTRL_0 0xfffe1040
#define PULL_DWN_CTRL_1 0xfffe1044
#define PULL_DWN_CTRL_2 0xfffe1048
#define PULL_DWN_CTRL_3 0xfffe104c
/* OMAP-1610 specific multiplexing registers */
#define FUNC_MUX_CTRL_E 0xfffe1090
#define FUNC_MUX_CTRL_F 0xfffe1094
#define FUNC_MUX_CTRL_10 0xfffe1098
#define FUNC_MUX_CTRL_11 0xfffe109c
#define FUNC_MUX_CTRL_12 0xfffe10a0
#define PU_PD_SEL_0 0xfffe10b4
#define PU_PD_SEL_1 0xfffe10b8
#define PU_PD_SEL_2 0xfffe10bc
#define PU_PD_SEL_3 0xfffe10c0
#define PU_PD_SEL_4 0xfffe10c4
/*
* ---------------------------------------------------------------------------
* TIPB bus interface
* ---------------------------------------------------------------------------
*/
#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
#define MPU_PUBLIC_TIPB_CNTL_REG (TIPB_PUBLIC_CNTL_BASE + 0x8)
#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
#define MPU_PRIVATE_TIPB_CNTL_REG (TIPB_PRIVATE_CNTL_BASE + 0x8)
/*
* ----------------------------------------------------------------------------
* DSP control registers
* ----------------------------------------------------------------------------
*/
/* MPUI Interface Registers */
#define MPUI_CTRL_REG (volatile __u32 *)(0xfffec900)
#define MPUI_DEBUG_ADDR (volatile __u32 *)(0xfffec904)
#define MPUI_DEBUG_DATA (volatile __u32 *)(0xfffec908)
#define MPUI_DEBUG_FLAG (volatile __u16 *)(0xfffec90c)
#define MPUI_STATUS_REG (volatile __u16 *)(0xfffec910)
#define MPUI_DSP_STATUS_REG (volatile __u16 *)(0xfffec914)
#define MPUI_DSP_BOOT_CONFIG (volatile __u16 *)(0xfffec918)
#define MPUI_DSP_API_CONFIG (volatile __u16 *)(0xfffec91c)
#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
include/asm-arm/arch-omap/io.h 0 → 100644
View file @ ca927387
/*
* linux/include/asm-arm/arch-omap/io.h
*
* Copied from linux/include/asm-arm/arch-sa1100/io.h
* Copyright (C) 1997-1999 Russell King
*
* Modifications:
* 06-12-1997 RMK Created.
* 07-04-1999 RMK Major cleanup
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
/*
* We don't actually have real ISA nor PCI buses, but there is so many
* drivers out there that might just work if we fake them...
*/
#define __io(a) (PCIO_BASE + (a))
#define __mem_pci(a) ((unsigned long)(a))
#define __mem_isa(a) ((unsigned long)(a))
#endif
include/asm-arm/arch-omap/irqs.h 0 → 100644
View file @ ca927387
/*
* linux/include/asm-arm/arch-omap/irqs.h
*
* Copyright (C) Greg Lonnon 2001
* Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
* are different.
*/
#ifndef __ASM_ARCH_OMAP1510_IRQS_H
#define __ASM_ARCH_OMAP1510_IRQS_H
/*
* IRQ numbers for interrupt handler 1
*
* NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
*
*/
#define INT_IH2_IRQ 0
#define INT_CAMERA 1
#define INT_FIQ 3
#define INT_RTDX 6
#define INT_DSP_MMU_ABORT 7
#define INT_HOST 8
#define INT_ABORT 9
#define INT_DSP_MAILBOX1 10
#define INT_DSP_MAILBOX2 11
#define INT_BRIDGE_PRIV 13
#define INT_GPIO_BANK1 14
#define INT_UART3 15
#define INT_TIMER3 16
#define INT_DMA_CH0_6 19
#define INT_DMA_CH1_7 20
#define INT_DMA_CH2_8 21
#define INT_DMA_CH3 22
#define INT_DMA_CH4 23
#define INT_DMA_CH5 24
#define INT_DMA_LCD 25
#define INT_TIMER1 26
#define INT_WD_TIMER 27
#define INT_BRIDGE_PUB 28
#define INT_TIMER2 30
#define INT_LCD_CTRL 31
/*
* OMAP-1510 specific IRQ numbers for interrupt handler 1
*/
#define INT_1510_RES2 2
#define INT_1510_SPI_TX 4
#define INT_1510_SPI_RX 5
#define INT_1510_RES12 12
#define INT_1510_LB_MMU 17
#define INT_1510_RES18 18
#define INT_1510_LOCAL_BUS 29
/*
* OMAP-1610 specific IRQ numbers for interrupt handler 1
*/
#define INT_1610_IH2_FIQ 2
#define INT_1610_McBSP2_TX 4
#define INT_1610_McBSP2_RX 5
#define INT_1610_LCD_LINE 12
#define INT_1610_GPTIMER1 17
#define INT_1610_GPTIMER2 18
#define INT_1610_SSR_FIFO_0 29
/*
* OMAP-730 specific IRQ numbers for interrupt handler 1
*/
#define INT_730_IH2_FIQ 0
#define INT_730_IH2_IRQ 1
#define INT_730_USB_NON_ISO 2
#define INT_730_USB_ISO 3
#define INT_730_ICR 4
#define INT_730_EAC 5
#define INT_730_GPIO_BANK1 6
#define INT_730_GPIO_BANK2 7
#define INT_730_GPIO_BANK3 8
#define INT_730_McBSP2TX 10
#define INT_730_McBSP2RX 11
#define INT_730_McBSP2RX_OVF 12
#define INT_730_LCD_LINE 14
#define INT_730_GSM_PROTECT 15
#define INT_730_TIMER3 16
#define INT_730_GPIO_BANK5 17
#define INT_730_GPIO_BANK6 18
#define INT_730_SPGIO_WR 29
/*
* IRQ numbers for interrupt handler 2
*
* NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
*/
#define IH2_BASE 32
#define INT_KEYBOARD (1 + IH2_BASE)
#define INT_uWireTX (2 + IH2_BASE)
#define INT_uWireRX (3 + IH2_BASE)
#define INT_I2C (4 + IH2_BASE)
#define INT_MPUIO (5 + IH2_BASE)
#define INT_USB_HHC_1 (6 + IH2_BASE)
#define INT_McBSP3TX (10 + IH2_BASE)
#define INT_McBSP3RX (11 + IH2_BASE)
#define INT_McBSP1TX (12 + IH2_BASE)
#define INT_McBSP1RX (13 + IH2_BASE)
#define INT_UART1 (14 + IH2_BASE)
#define INT_UART2 (15 + IH2_BASE)
#define INT_BT_MCSI1TX (16 + IH2_BASE)
#define INT_BT_MCSI1RX (17 + IH2_BASE)
#define INT_USB_W2FC (20 + IH2_BASE)
#define INT_1WIRE (21 + IH2_BASE)
#define INT_OS_TIMER (22 + IH2_BASE)
#define INT_MMC (23 + IH2_BASE)
#define INT_GAUGE_32K (24 + IH2_BASE)
#define INT_RTC_TIMER (25 + IH2_BASE)
#define INT_RTC_ALARM (26 + IH2_BASE)
#define INT_MEM_STICK (27 + IH2_BASE)
#define INT_DSP_MMU (28 + IH2_BASE)
/*
* OMAP-1510 specific IRQ numbers for interrupt handler 2
*/
#define INT_1510_OS_32kHz_TIMER (22 + IH2_BASE)
#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
/*
* OMAP-1610 specific IRQ numbers for interrupt handler 2
*/
#define INT_1610_FAC (0 + IH2_BASE)
#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
#define INT_1610_USB_OTG (8 + IH2_BASE)
#define INT_1610_SoSSI (9 + IH2_BASE)
#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
#define INT_1610_MMC2 (42 + IH2_BASE)
#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
#define INT_1610_SPI (49 + IH2_BASE)
#define INT_1610_DMA_CH6 (53 + IH2_BASE)
#define INT_1610_DMA_CH7 (54 + IH2_BASE)
#define INT_1610_DMA_CH8 (55 + IH2_BASE)
#define INT_1610_DMA_CH9 (56 + IH2_BASE)
#define INT_1610_DMA_CH10 (57 + IH2_BASE)
#define INT_1610_DMA_CH11 (58 + IH2_BASE)
#define INT_1610_DMA_CH12 (59 + IH2_BASE)
#define INT_1610_DMA_CH13 (60 + IH2_BASE)
#define INT_1610_DMA_CH14 (61 + IH2_BASE)
#define INT_1610_DMA_CH15 (62 + IH2_BASE)
#define INT_1610_NAND (63 + IH2_BASE)
/*
* OMAP-730 specific IRQ numbers for interrupt handler 2
*/
#define INT_730_HW_ERRORS (0 + IH2_BASE)
#define INT_730_NFIQ_PWR_FAIL (1 + IH2_BASE)
#define INT_730_CFCD (2 + IH2_BASE)
#define INT_730_CFIREQ (3 + IH2_BASE)
#define INT_730_I2C (4 + IH2_BASE)
#define INT_730_PCC (5 + IH2_BASE)
#define INT_730_MPU_EXT_NIRQ (6 + IH2_BASE)
#define INT_730_SPI_100K_1 (7 + IH2_BASE)
#define INT_730_SYREN_SPI (8 + IH2_BASE)
#define INT_730_VLYNQ (9 + IH2_BASE)
#define INT_730_GPIO_BANK4 (10 + IH2_BASE)
#define INT_730_McBSP1TX (11 + IH2_BASE)
#define INT_730_McBSP1RX (12 + IH2_BASE)
#define INT_730_McBSP1RX_OF (13 + IH2_BASE)
#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE)
#define INT_730_UART_MODEM_1 (15 + IH2_BASE)
#define INT_730_MCSI (16 + IH2_BASE)
#define INT_730_uWireTX (17 + IH2_BASE)
#define INT_730_uWireRX (18 + IH2_BASE)
#define INT_730_SMC_CD (19 + IH2_BASE)
#define INT_730_SMC_IREQ (20 + IH2_BASE)
#define INT_730_HDQ_1WIRE (21 + IH2_BASE)
#define INT_730_TIMER32K (22 + IH2_BASE)
#define INT_730_MMC_SDIO (23 + IH2_BASE)
#define INT_730_UPLD (24 + IH2_BASE)
#define INT_730_RTC_TIMER (25 + IH2_BASE)
#define INT_730_RTC_ALARM (26 + IH2_BASE)
#define INT_730_USB_HHC_1 (27 + IH2_BASE)
#define INT_730_USB_HHC_2 (28 + IH2_BASE)
#define INT_730_USB_GENI (29 + IH2_BASE)
#define INT_730_USB_OTG (30 + IH2_BASE)
#define INT_730_CAMERA_IF (31 + IH2_BASE)
#define INT_730_RNG (32 + IH2_BASE)
#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE)
#define INT_730_DBB_RF_EN (34 + IH2_BASE)
#define INT_730_MPUIO_KEYPAD (35 + IH2_BASE)
#define INT_730_SHA1_MD5 (36 + IH2_BASE)
#define INT_730_SPI_100K_2 (37 + IH2_BASE)
#define INT_730_RNG_IDLE (38 + IH2_BASE)
#define INT_730_MPUIO (39 + IH2_BASE)
#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE)
#define INT_730_LLPC_OE_RISING (42 + IH2_BASE)
#define INT_730_LLPC_VSYNC (43 + IH2_BASE)
#define INT_730_WAKE_UP_REQ (46 + IH2_BASE)
#define INT_730_DMA_CH6 (53 + IH2_BASE)
#define INT_730_DMA_CH7 (54 + IH2_BASE)
#define INT_730_DMA_CH8 (55 + IH2_BASE)
#define INT_730_DMA_CH9 (56 + IH2_BASE)
#define INT_730_DMA_CH10 (57 + IH2_BASE)
#define INT_730_DMA_CH11 (58 + IH2_BASE)
#define INT_730_DMA_CH12 (59 + IH2_BASE)
#define INT_730_DMA_CH13 (60 + IH2_BASE)
#define INT_730_DMA_CH14 (61 + IH2_BASE)
#define INT_730_DMA_CH15 (62 + IH2_BASE)
#define INT_730_NAND (63 + IH2_BASE)
/* OMAP-730 differences */
#ifdef CONFIG_ARCH_OMAP730
#undef INT_IH2_IRQ
#define INT_IH2_IRQ INT_730_IH2_IRQ
#undef INT_KEYBOARD
#define INT_KEYBOARD INT_730_MPUIO_KEYPAD
#undef INT_UART1
#define INT_UART1 INT_730_UART_MODEM_1
#undef INT_UART2
#define INT_UART2 INT_730_UART_MODEM_IRDA_2
#undef INT_MPUIO
#define INT_MPUIO INT_730_MPUIO
#undef INT_RTC_TIMER
#define INT_RTC_TIMER INT_730_RTC_TIMER
#undef INT_RTC_ALARM
#define INT_RTC_ALARM INT_730_RTC_ALARM
#endif
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
* 16 MPUIO lines */
#define OMAP_MAX_GPIO_LINES 192
#define IH_GPIO_BASE (128 + IH2_BASE)
#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
#define IH_BOARD_BASE (16 + IH_MPUIO_BASE)
#ifndef __ASSEMBLY__
extern void omap_init_irq(void);
#endif
/*
* The definition of NR_IRQS is in board-specific header file, which is
* included via hardware.h
*/
#include <asm/arch/hardware.h>
#endif
include/asm-arm/arch-omap/memory.h 0 → 100644
View file @ ca927387
/*
* linux/include/asm-arm/arch-omap/memory.h
*
* Memory map for OMAP-1510 and 1610
*
* Copyright (C) 2000 RidgeRun, Inc.
* Author: Greg Lonnon <glonnon@ridgerun.com>
*
* This file was derived from linux/include/asm-arm/arch-intergrator/memory.h
* Copyright (C) 1999 ARM Limited
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_MMU_H
#define __ASM_ARCH_MMU_H
/*
* Task size: 3GB
*/
#define TASK_SIZE (0xbf000000UL)
#define TASK_SIZE_26 (0x04000000UL)
/*
* This decides where the kernel will search for a free chunk of vm
* space during mmap's.
*/
#define TASK_UNMAPPED_BASE (0x40000000)
/*
* Page offset: 3GB
*/
#define PAGE_OFFSET (0xC0000000UL)
#define PHYS_OFFSET (0x10000000UL)
/*
* OMAP-1510 Local Bus address offset
*/
#define OMAP1510_LB_OFFSET (0x30000000UL)
/*
* The DRAM is contiguous.
*/
#define __virt_to_phys__is_a_macro
#define __virt_to_phys(vpage) ((vpage) - PAGE_OFFSET + PHYS_OFFSET)
#define __phys_to_virt__is_a_macro
#define __phys_to_virt(ppage) ((ppage) + PAGE_OFFSET - PHYS_OFFSET)
/*
* Conversion between SDRAM and fake PCI bus, used by USB
* NOTE: Physical address must be converted to Local Bus address
* on OMAP-1510 only
*/
#define __virt_to_bus__is_a_macro
#define __bus_to_virt__is_a_macro
/*
* Bus address is physical address, except for OMAP-1510 Local Bus.
*/
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
/*
* OMAP-1510 bus address is translated into a Local Bus address if the
* OMAP bus type is lbus. See dmadev_uses_omap_lbus().
*/
#ifdef CONFIG_ARCH_OMAP1510
#define bus_to_lbus(x) ((x) + (OMAP1510_LB_OFFSET - PHYS_OFFSET))
#define lbus_to_bus(x) ((x) - (OMAP1510_LB_OFFSET - PHYS_OFFSET))
#endif
#define PHYS_TO_NID(addr) (0)
#endif
include/asm-arm/arch-omap/mux.h 0 → 100644
View file @ ca927387
/*
* linux/include/asm-arm/arch-omap/mux.h
*
* Table of the Omap register configurations for the FUNC_MUX and
* PULL_DWN combinations.
*
* Copyright (C) 2003 Nokia Corporation
*
* Written by Tony Lindgren <tony.lindgren@nokia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* NOTE: Please use the following naming style for new pin entries.
* For example, W8_1610_MMC2_DAT0, where:
* - W8 = ball
* - 1610 = 1510 or 1610, none if common for both 1510 and 1610
* - MMC2_DAT0 = function
*
* Change log:
* Added entry for the I2C interface. (02Feb 2004)
* Copyright (C) 2004 Texas Instruments
*
* Added entry for the keypad and uwire CS1. (09Mar 2004)
* Copyright (C) 2004 Texas Instruments
*
*/
#ifndef __ASM_ARCH_MUX_H
#define __ASM_ARCH_MUX_H
#define PU_PD_SEL_NA 0 /* No pu_pd reg availabe */
#define DEBUG_MUX
#ifdef DEBUG_MUX
#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
.mux_reg = FUNC_MUX_CTRL_##reg, \
.mask_offset = mode_offset, \
.mask = mode,
#define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
.pull_reg = PULL_DWN_CTRL_##reg, \
.pull_bit = bit, \
.pull_val = status,
#define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
.pu_pd_reg = PU_PD_SEL_##reg, \
.pu_pd_val = status,
#else
#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
.mask_offset = mode_offset, \
.mask = mode,
#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
.pull_bit = bit, \
.pull_val = status,
#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
.pu_pd_val = status,
#endif // DEBUG_MUX
#define MUX_CFG(desc, mux_reg, mode_offset, mode, \
pull_reg, pull_bit, pull_status, \
pu_pd_reg, pu_pd_status, debug_status) \
{ \
.name = desc, \
.debug = debug_status, \
MUX_REG(mux_reg, mode_offset, mode) \
PULL_REG(pull_reg, pull_bit, pull_status) \
PU_PD_REG(pu_pd_reg, pu_pd_status) \
},
#define PULL_DISABLED 0
#define PULL_ENABLED 1
#define PULL_DOWN 0
#define PULL_UP 1
typedef struct {
char *name;
unsigned char busy;
unsigned char debug;
const char *mux_reg_name;
const unsigned int mux_reg;
const unsigned char mask_offset;
const unsigned char mask;
const char *pull_name;
const unsigned int pull_reg;
const unsigned char pull_val;
const unsigned char pull_bit;
const char *pu_pd_name;
const unsigned int pu_pd_reg;
const unsigned char pu_pd_val;
} reg_cfg_set;
/*
* Lookup table for FUNC_MUX and PULL_DWN register combinations for each
* device. See also reg_cfg_table below for the register values.
*/
typedef enum {
/* UART1 (BT_UART_GATING)*/
UART1_TX = 0,
UART1_RTS,
/* UART2 (COM_UART_GATING)*/
UART2_TX,
UART2_RX,
UART2_CTS,
UART2_RTS,
/* UART3 (GIGA_UART_GATING) */
UART3_TX,
UART3_RX,
UART3_CTS,
UART3_RTS,
UART3_CLKREQ,
UART3_BCLK, /* 12MHz clock out */
/* USB master generic */
R18_USB_VBUS,
R18_1510_USB_GPIO0,
W4_USB_PUEN,
W4_USB_CLKO,
/* USB1 master */
USB1_SUSP,
USB1_SEO,
USB1_TXEN,
USB1_TXD,
USB1_VP,
USB1_VM,
USB1_RCV,
USB1_SPEED,
/* USB2 master */
USB2_SUSP,
USB2_VP,
USB2_TXEN,
USB2_VM,
USB2_RCV,
USB2_SEO,
USB2_TXD,
/* OMAP-1510 GPIO */
R18_1510_GPIO0,
R19_1510_GPIO1,
M14_1510_GPIO2,
/* MPUIO */
MPUIO2,
MPUIO4,
MPUIO5,
T20_1610_MPUIO5,
W11_1610_MPUIO6,
V10_1610_MPUIO7,
W11_1610_MPUIO9,
V10_1610_MPUIO10,
W10_1610_MPUIO11,
E20_1610_MPUIO13,
U20_1610_MPUIO14,
E19_1610_MPUIO15,
/* MCBSP2 */
MCBSP2_CLKR,
MCBSP2_CLKX,
MCBSP2_DR,
MCBSP2_DX,
MCBSP2_FSR,
MCBSP2_FSX,
/* MCBSP3 */
MCBSP3_CLKX,
/* Misc ballouts */
BALLOUT_V8_ARMIO3,
/* OMAP-1610 MMC2 */
W8_1610_MMC2_DAT0,
V8_1610_MMC2_DAT1,
W15_1610_MMC2_DAT2,
R10_1610_MMC2_DAT3,
Y10_1610_MMC2_CLK,
Y8_1610_MMC2_CMD,
V9_1610_MMC2_CMDDIR,
V5_1610_MMC2_DATDIR0,
W19_1610_MMC2_DATDIR1,
R18_1610_MMC2_CLKIN,
/* OMAP-1610 External Trace Interface */
M19_1610_ETM_PSTAT0,
L15_1610_ETM_PSTAT1,
L18_1610_ETM_PSTAT2,
L19_1610_ETM_D0,
J19_1610_ETM_D6,
J18_1610_ETM_D7,
/* OMAP-1610 GPIO */
P20_1610_GPIO4,
V9_1610_GPIO7,
N19_1610_GPIO13,
P10_1610_GPIO22,
V5_1610_GPIO24,
AA20_1610_GPIO_41,
/* OMAP-1610 uWire */
V19_1610_UWIRE_SCLK,
U18_1610_UWIRE_SDI,
W21_1610_UWIRE_SDO,
N14_1610_UWIRE_CS0,
P15_1610_UWIRE_CS0,
N15_1610_UWIRE_CS1,
/* First MMC */
MMC_CMD,
MMC_DAT1,
MMC_DAT2,
MMC_DAT0,
MMC_CLK,
MMC_DAT3,
/* OMAP-1610 USB0 alternate pin configuration */
W9_USB0_TXEN,
AA9_USB0_VP,
Y5_USB0_RCV,
R9_USB0_VM,
V6_USB0_TXD,
W5_USB0_SE0,
V9_USB0_SPEED,
V9_USB0_SUSP,
/* USB2 */
W9_USB2_TXEN,
AA9_USB2_VP,
Y5_USB2_RCV,
R9_USB2_VM,
V6_USB2_TXD,
W5_USB2_SE0,
/* UART1 1610 */
R13_1610_UART1_TX,
V14_1610_UART1_RX,
R14_1610_UART1_CTS,
AA15_1610_UART1_RTS,
/* I2C OMAP-1610 */
I2C_SCL,
I2C_SDA,
/* Keypad */
F18_1610_KBC0,
D20_1610_KBC1,
D19_1610_KBC2,
E18_1610_KBC3,
C21_1610_KBC4,
G18_1610_KBR0,
F19_1610_KBR1,
H14_1610_KBR2,
E20_1610_KBR3,
E19_1610_KBR4,
N19_1610_KBR5,
} reg_cfg_t;
#ifdef __MUX_C__
/*
* Table of various FUNC_MUX and PULL_DWN combinations for each device.
* See also reg_cfg_t above for the lookup table.
*/
static reg_cfg_set reg_cfg_table[] = {
/*
* description mux mode mux pull pull pull pu_pd pu dbg
* reg offset mode reg bit ena reg
*/
MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
/* UART2 (COM_UART_GATING), conflicts with USB2 */
MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
/* UART3 (GIGA_UART_GATING) */
MUX_CFG("UART3_TX", 6, 0, 1, 0, 30, 0, NA, 0, 0)
MUX_CFG("UART3_RX", 6, 3, 0, 0, 31, 1, NA, 0, 0)
MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)
MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0)
MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)
MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0)
/* USB internal master generic */
MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1)
MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1)
MUX_CFG("W4_USB_PUEN", D, 3, 0, 3, 5, 1, NA, 0, 1)
MUX_CFG("W4_USB_CLKO", D, 3, 1, 3, 5, 0, NA, 0, 1)
/* USB1 master */
MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1)
MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA, 0, 1)
MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA, 0, 1)
MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1)
MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1)
MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1)
MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1)
MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1)
/* USB2 master */
MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1)
MUX_CFG("USB2_VP", B, 6, 1, 2, 18, 0, NA, 0, 1)
MUX_CFG("USB2_TXEN", B, 9, 1, 2, 19, 0, NA, 0, 1)
MUX_CFG("USB2_VM", C, 18, 1, 3, 0, 0, NA, 0, 1)
MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1)
MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1)
MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1)
/* OMAP-1510 GPIO */
MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1)
MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1)
MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1)
/* MPUIO */
MUX_CFG("MPUIO2", 7, 18, 0, 1, 1, 1, NA, 0, 1)
MUX_CFG("MPUIO4", 7, 15, 0, 1, 13, 1, NA, 0, 1)
MUX_CFG("MPUIO5", 7, 12, 0, 1, 12, 1, NA, 0, 1)
MUX_CFG("T20_1610_MPUIO5", 7, 12, 0, 1, 12, 0, 3, 0, 1)
MUX_CFG("W11_1610_MPUIO6", 10, 15, 2, 3, 8, 0, 3, 0, 1)
MUX_CFG("V10_1610_MPUIO7", A, 24, 2, 2, 14, 0, 2, 0, 1)
MUX_CFG("W11_1610_MPUIO9", 10, 15, 1, 3, 8, 0, 3, 0, 1)
MUX_CFG("V10_1610_MPUIO10", A, 24, 1, 2, 14, 0, 2, 0, 1)
MUX_CFG("W10_1610_MPUIO11", A, 18, 2, 2, 11, 0, 2, 0, 1)
MUX_CFG("E20_1610_MPUIO13", 3, 21, 1, 0, 7, 0, 0, 0, 1)
MUX_CFG("U20_1610_MPUIO14", 9, 6, 6, 0, 30, 0, 0, 0, 1)
MUX_CFG("E19_1610_MPUIO15", 3, 18, 1, 0, 6, 0, 0, 0, 1)
/* MCBSP2 */
MUX_CFG("MCBSP2_CLKR", C, 6, 0, 2, 27, 1, NA, 0, 1)
MUX_CFG("MCBSP2_CLKX", C, 9, 0, 2, 29, 1, NA, 0, 1)
MUX_CFG("MCBSP2_DR", C, 0, 0, 2, 26, 1, NA, 0, 1)
MUX_CFG("MCBSP2_DX", C, 15, 0, 2, 31, 1, NA, 0, 1)
MUX_CFG("MCBSP2_FSR", C, 12, 0, 2, 30, 1, NA, 0, 1)
MUX_CFG("MCBSP2_FSX", C, 3, 0, 2, 27, 1, NA, 0, 1)
/* MCBSP3 NOTE: Mode must 1 for clock */
MUX_CFG("MCBSP3_CLKX", 9, 3, 1, 1, 29, 0, NA, 0, 1)
/* Misc ballouts */
MUX_CFG("BALLOUT_V8_ARMIO3", B, 18, 0, 2, 25, 1, NA, 0, 1)
/* OMAP-1610 MMC2 */
MUX_CFG("W8_1610_MMC2_DAT0", B, 21, 6, 2, 23, 1, 2, 1, 1)
MUX_CFG("V8_1610_MMC2_DAT1", B, 27, 6, 2, 25, 1, 2, 1, 1)
MUX_CFG("W15_1610_MMC2_DAT2", 9, 12, 6, 2, 5, 1, 2, 1, 1)
MUX_CFG("R10_1610_MMC2_DAT3", B, 18, 6, 2, 22, 1, 2, 1, 1)
MUX_CFG("Y10_1610_MMC2_CLK", B, 3, 6, 2, 17, 0, 2, 0, 1)
MUX_CFG("Y8_1610_MMC2_CMD", B, 24, 6, 2, 24, 1, 2, 1, 1)
MUX_CFG("V9_1610_MMC2_CMDDIR", B, 12, 6, 2, 20, 0, 2, 1, 1)
MUX_CFG("V5_1610_MMC2_DATDIR0", B, 15, 6, 2, 21, 0, 2, 1, 1)
MUX_CFG("W19_1610_MMC2_DATDIR1", 8, 15, 6, 1, 23, 0, 1, 1, 1)
MUX_CFG("R18_1610_MMC2_CLKIN", 7, 9, 6, 1, 11, 0, 1, 11, 1)
/* OMAP-1610 External Trace Interface */
MUX_CFG("M19_1610_ETM_PSTAT0", 5, 27, 1, 0, 29, 0, 0, 0, 1)
MUX_CFG("L15_1610_ETM_PSTAT1", 5, 24, 1, 0, 28, 0, 0, 0, 1)
MUX_CFG("L18_1610_ETM_PSTAT2", 5, 21, 1, 0, 27, 0, 0, 0, 1)
MUX_CFG("L19_1610_ETM_D0", 5, 18, 1, 0, 26, 0, 0, 0, 1)
MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1)
MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1)
/* OMAP-1610 GPIO */
MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1)
MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1)
MUX_CFG("N19_1610_GPIO13", 6, 12, 0, 1, 2, 0, 1, 1, 1)
MUX_CFG("P10_1610_GPIO22", C, 0, 7, 2, 26, 0, 2, 1, 1)
MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1)
MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1)
/* OMAP-1610 uWire */
MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1)
MUX_CFG("U18_1610_UWIRE_SDI", 8, 0, 0, 1, 18, 0, 1, 1, 1)
MUX_CFG("W21_1610_UWIRE_SDO", 8, 3, 0, 1, 19, 0, 1, 1, 1)
MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 0, 0, 0, 0, 0, 0)
/* First MMC interface, same on 1510 and 1610 */
MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1)
MUX_CFG("MMC_DAT1", A, 24, 0, 2, 14, 1, 2, 1, 1)
MUX_CFG("MMC_DAT2", A, 18, 0, 2, 12, 1, 2, 1, 1)
MUX_CFG("MMC_DAT0", B, 0, 0, 2, 16, 1, 2, 1, 1)
MUX_CFG("MMC_CLK", A, 21, 0, 0, 0, 0, 0, 0, 1)
MUX_CFG("MMC_DAT3", 10, 15, 0, 3, 8, 1, 3, 1, 1)
/* OMAP-1610 USB0 alternate configuration */
MUX_CFG("W9_USB0_TXEN", B, 9, 5, 2, 19, 0, 2, 0, 1)
MUX_CFG("AA9_USB0_VP", B, 6, 5, 2, 18, 0, 2, 0, 1)
MUX_CFG("Y5_USB0_RCV", C, 21, 5, 3, 1, 0, 1, 0, 1)
MUX_CFG("R9_USB0_VM", C, 18, 5, 3, 0, 0, 3, 0, 1)
MUX_CFG("V6_USB0_TXD", C, 27, 5, 3, 3, 0, 3, 0, 1)
MUX_CFG("W5_USB0_SE0", C, 24, 5, 3, 2, 0, 3, 0, 1)
MUX_CFG("V9_USB0_SPEED", B, 12, 5, 2, 20, 0, 2, 0, 1)
MUX_CFG("Y10_USB0_SUSP", B, 3, 5, 2, 17, 0, 2, 0, 1)
/* USB2 interface */
MUX_CFG("W9_USB2_TXEN", B, 9, 1, 0, 0, 0, NA, 0, 1)
MUX_CFG("AA9_USB2_VP", B, 6, 1, 0, 0, 0, NA, 0, 1)
MUX_CFG("Y5_USB2_RCV", C, 21, 1, 0, 0, 0, NA, 0, 1)
MUX_CFG("R8_USB2_VM", C, 18, 1, 0, 0, 0, NA, 0, 1)
MUX_CFG("V6_USB2_TXD", C, 27, 2, 0, 0, 0, NA, 0, 1)
MUX_CFG("W5_USB2_SE0", C, 24, 2, 0, 0, 0, NA, 0, 1)
/* UART1 */
MUX_CFG("R13_1610_UART1_TX", A, 12, 6, 2, 10, 0, 2, 10, 1)
MUX_CFG("V14_1610_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1)
MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1)
MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1)
/* I2C interface */
MUX_CFG("I2C_SCL", 7, 24, 0, 0, 0, 0, 0, 0, 0)
MUX_CFG("I2C_SDA", 7, 27, 0, 0, 0, 0, 0, 0, 0)
/* Keypad */
MUX_CFG("F18_1610_KBC0", 3, 15, 0, 0, 5, 1, 0, 0, 0)
MUX_CFG("D20_1610_KBC1", 3, 12, 0, 0, 4, 1, 0, 0, 0)
MUX_CFG("D19_1610_KBC2", 3, 9, 0, 0, 3, 1, 0, 0, 0)
MUX_CFG("E18_1610_KBC3", 3, 6, 0, 0, 2, 1, 0, 0, 0)
MUX_CFG("C21_1610_KBC4", 3, 3, 0, 0, 1, 1, 0, 0, 0)
MUX_CFG("G18_1610_KBR0", 4, 0, 0, 0, 10, 1, 0, 1, 0)
MUX_CFG("F19_1610_KBR1", 3, 27, 0, 0, 9, 1, 0, 1, 0)
MUX_CFG("H14_1610_KBR2", 3, 24, 0, 0, 8, 1, 0, 1, 0)
MUX_CFG("E20_1610_KBR3", 3, 21, 0, 0, 7, 1, 0, 1, 0)
MUX_CFG("E19_1610_KBR4", 3, 18, 0, 0, 6, 1, 0, 1, 0)
MUX_CFG("N19_1610_KBR5", 6, 12, 1, 1, 2, 1, 1, 1, 0)
};
#endif /* __MUX_C__ */
extern int omap_cfg_reg(reg_cfg_t reg_cfg);
#endif
include/asm-arm/arch-omap/omap-h2.h 0 → 100644
View file @ ca927387
/*
* linux/include/asm-arm/arch-omap/omap-h2.h
*
* Hardware definitions for TI OMAP1610 H2 board.
*
* Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_OMAP_H2_H
#define __ASM_ARCH_OMAP_H2_H
/* Placeholder for H2 specific defines */
#endif /* __ASM_ARCH_OMAP_H2_H */
include/asm-arm/arch-omap/omap-innovator.h 0 → 100644
View file @ ca927387
/*
* linux/include/asm-arm/arch-omap/omap-innovator.h
*
* Copyright (C) 2001 RidgeRun, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_OMAP_INNOVATOR_H
#define __ASM_ARCH_OMAP_INNOVATOR_H
#if defined (CONFIG_ARCH_OMAP1510)
/*
* ---------------------------------------------------------------------------
* OMAP-1510 FPGA
* ---------------------------------------------------------------------------
*/
#define OMAP1510P1_FPGA_BASE 0xE8000000 /* Virtual */
#define OMAP1510P1_FPGA_SIZE SZ_4K
#define OMAP1510P1_FPGA_START 0x08000000 /* Physical */
/* Revision */
#define OMAP1510P1_FPGA_REV_LOW (OMAP1510P1_FPGA_BASE + 0x0)
#define OMAP1510P1_FPGA_REV_HIGH (OMAP1510P1_FPGA_BASE + 0x1)
#define OMAP1510P1_FPGA_LCD_PANEL_CONTROL (OMAP1510P1_FPGA_BASE + 0x2)
#define OMAP1510P1_FPGA_LED_DIGIT (OMAP1510P1_FPGA_BASE + 0x3)
#define INNOVATOR_FPGA_HID_SPI (OMAP1510P1_FPGA_BASE + 0x4)
#define OMAP1510P1_FPGA_POWER (OMAP1510P1_FPGA_BASE + 0x5)
/* Interrupt status */
#define OMAP1510P1_FPGA_ISR_LO (OMAP1510P1_FPGA_BASE + 0x6)
#define OMAP1510P1_FPGA_ISR_HI (OMAP1510P1_FPGA_BASE + 0x7)
/* Interrupt mask */
#define OMAP1510P1_FPGA_IMR_LO (OMAP1510P1_FPGA_BASE + 0x8)
#define OMAP1510P1_FPGA_IMR_HI (OMAP1510P1_FPGA_BASE + 0x9)
/* Reset registers */
#define OMAP1510P1_FPGA_HOST_RESET (OMAP1510P1_FPGA_BASE + 0xa)
#define OMAP1510P1_FPGA_RST (OMAP1510P1_FPGA_BASE + 0xb)
#define OMAP1510P1_FPGA_AUDIO (OMAP1510P1_FPGA_BASE + 0xc)
#define OMAP1510P1_FPGA_DIP (OMAP1510P1_FPGA_BASE + 0xe)
#define OMAP1510P1_FPGA_FPGA_IO (OMAP1510P1_FPGA_BASE + 0xf)
#define OMAP1510P1_FPGA_UART1 (OMAP1510P1_FPGA_BASE + 0x14)
#define OMAP1510P1_FPGA_UART2 (OMAP1510P1_FPGA_BASE + 0x15)
#define OMAP1510P1_FPGA_OMAP1510_STATUS (OMAP1510P1_FPGA_BASE + 0x16)
#define OMAP1510P1_FPGA_BOARD_REV (OMAP1510P1_FPGA_BASE + 0x18)
#define OMAP1510P1_PPT_DATA (OMAP1510P1_FPGA_BASE + 0x100)
#define OMAP1510P1_PPT_STATUS (OMAP1510P1_FPGA_BASE + 0x101)
#define OMAP1510P1_PPT_CONTROL (OMAP1510P1_FPGA_BASE + 0x102)
#define OMAP1510P1_FPGA_TOUCHSCREEN (OMAP1510P1_FPGA_BASE + 0x204)
#define INNOVATOR_FPGA_INFO (OMAP1510P1_FPGA_BASE + 0x205)
#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510P1_FPGA_BASE + 0x206)
#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510P1_FPGA_BASE + 0x207)
#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510P1_FPGA_BASE + 0x208)
#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510P1_FPGA_BASE + 0x209)
#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510P1_FPGA_BASE + 0x20a)
#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510P1_FPGA_BASE + 0x20b)
#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510P1_FPGA_BASE + 0x20c)
#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510P1_FPGA_BASE + 0x20d)
#define INNOVATOR_FPGA_ISR2 (OMAP1510P1_FPGA_BASE + 0x20e)
#define INNOVATOR_FPGA_IMR2 (OMAP1510P1_FPGA_BASE + 0x210)
#define OMAP1510P1_FPGA_ETHR_START (OMAP1510P1_FPGA_START + 0x300)
#define OMAP1510P1_FPGA_ETHR_BASE (OMAP1510P1_FPGA_BASE + 0x300)
/*
* Power up Giga UART driver, turn on HID clock.
* Turn off BT power, since we're not using it and it
* draws power.
*/
#define OMAP1510P1_FPGA_RESET_VALUE 0x42
#define OMAP1510P1_FPGA_PCR_IF_PD0 (1 << 7)
#define OMAP1510P1_FPGA_PCR_COM2_EN (1 << 6)
#define OMAP1510P1_FPGA_PCR_COM1_EN (1 << 5)
#define OMAP1510P1_FPGA_PCR_EXP_PD0 (1 << 4)
#define OMAP1510P1_FPGA_PCR_EXP_PD1 (1 << 3)
#define OMAP1510P1_FPGA_PCR_48MHZ_CLK (1 << 2)
#define OMAP1510P1_FPGA_PCR_4MHZ_CLK (1 << 1)
#define OMAP1510P1_FPGA_PCR_RSRVD_BIT0 (1 << 0)
/*
* Innovator/OMAP1510 FPGA HID register bit definitions
*/
#define FPGA_HID_SCLK (1<<0) /* output */
#define FPGA_HID_MOSI (1<<1) /* output */
#define FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */
#define FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */
#define FPGA_HID_MISO (1<<4) /* input */
#define FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */
#define FPGA_HID_rsrvd (1<<6)
#define FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
#ifndef OMAP_SDRAM_DEVICE
#define OMAP_SDRAM_DEVICE D256M_1X16_4B
#endif
#define OMAP1510P1_IMIF_PRI_VALUE 0x00
#define OMAP1510P1_EMIFS_PRI_VALUE 0x00
#define OMAP1510P1_EMIFF_PRI_VALUE 0x00
/*
* These definitions define an area of FLASH set aside
* for the use of MTD/JFFS2. This is the area of flash
* that a JFFS2 filesystem will reside which is mounted
* at boot with the "root=/dev/mtdblock/0 rw"
* command line option. The flash address used here must
* fall within the legal range defined by rrload for storing
* the filesystem component. This address will be sufficiently
* deep into the overall flash range to avoid the other
* components also stored in flash such as the bootloader,
* the bootloader params, and the kernel.
* The SW2 settings for the map below are:
* 1 off, 2 off, 3 on, 4 off.
*/
/* Intel flash_0, partitioned as expected by rrload */
#define OMAP_FLASH_0_BASE 0xD8000000
#define OMAP_FLASH_0_START 0x00000000
#define OMAP_FLASH_0_SIZE SZ_16M
/* Intel flash_1, used for cramfs or other flash file systems */
#define OMAP_FLASH_1_BASE 0xD9000000
#define OMAP_FLASH_1_START 0x01000000
#define OMAP_FLASH_1_SIZE SZ_16M
/* The FPGA IRQ is cascaded through GPIO_13 */
#define INT_FPGA (IH_GPIO_BASE + 13)
/* IRQ Numbers for interrupts muxed through the FPGA */
#define IH_FPGA_BASE IH_BOARD_BASE
#define INT_FPGA_ATN (IH_FPGA_BASE + 0)
#define INT_FPGA_ACK (IH_FPGA_BASE + 1)
#define INT_FPGA2 (IH_FPGA_BASE + 2)
#define INT_FPGA3 (IH_FPGA_BASE + 3)
#define INT_FPGA4 (IH_FPGA_BASE + 4)
#define INT_FPGA5 (IH_FPGA_BASE + 5)
#define INT_FPGA6 (IH_FPGA_BASE + 6)
#define INT_FPGA7 (IH_FPGA_BASE + 7)
#define INT_FPGA8 (IH_FPGA_BASE + 8)
#define INT_FPGA9 (IH_FPGA_BASE + 9)
#define INT_FPGA10 (IH_FPGA_BASE + 10)
#define INT_FPGA11 (IH_FPGA_BASE + 11)
#define INT_FPGA12 (IH_FPGA_BASE + 12)
#define INT_ETHER (IH_FPGA_BASE + 13)
#define INT_FPGAUART1 (IH_FPGA_BASE + 14)
#define INT_FPGAUART2 (IH_FPGA_BASE + 15)
#define INT_FPGA_TS (IH_FPGA_BASE + 16)
#define INT_FPGA17 (IH_FPGA_BASE + 17)
#define INT_FPGA_CAM (IH_FPGA_BASE + 18)
#define INT_FPGA_RTC_A (IH_FPGA_BASE + 19)
#define INT_FPGA_RTC_B (IH_FPGA_BASE + 20)
#define INT_FPGA_CD (IH_FPGA_BASE + 21)
#define INT_FPGA22 (IH_FPGA_BASE + 22)
#define INT_FPGA23 (IH_FPGA_BASE + 23)
#define NR_FPGA_IRQS 24
#define MAXIRQNUM (IH_FPGA_BASE + NR_FPGA_IRQS - 1)
#define MAXFIQNUM MAXIRQNUM
#define MAXSWINUM MAXIRQNUM
#define NR_IRQS 256
#ifndef __ASSEMBLY__
void fpga_write(unsigned char val, int reg);
unsigned char fpga_read(int reg);
#endif
#elif defined (CONFIG_ARCH_OMAP1610)
/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
#define OMAP1610_ETHR_BASE 0xE8000000
#define OMAP1610_ETHR_SIZE SZ_4K
#define OMAP1610_ETHR_START 0x04000000
/* Intel STRATA NOR flash at CS3 */
#define OMAP1610_NOR_FLASH_BASE 0xD8000000
#define OMAP1610_NOR_FLASH_SIZE SZ_32M
#define OMAP1610_NOR_FLASH_START 0x0C000000
#define MAXIRQNUM (IH_BOARD_BASE)
#define MAXFIQNUM MAXIRQNUM
#define MAXSWINUM MAXIRQNUM
#define NR_IRQS (MAXIRQNUM + 1)
#else
#error "Only OMAP1510 and OMAP1610 Innovator supported!"
#endif
#endif
include/asm-arm/arch-omap/omap-perseus2.h 0 → 100644
View file @ ca927387
/*
* linux/include/asm-arm/arch-omap/omap-perseus2.h
*
* Copyright 2003 by Texas Instruments Incorporated
* OMAP730 / P2-sample additions
* Author: Jean Pihet
*
* Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
* Author: RidgeRun, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_OMAP_P2SAMPLE_H
#define __ASM_ARCH_OMAP_P2SAMPLE_H
#if defined(CONFIG_ARCH_OMAP730) && defined (CONFIG_MACH_OMAP_PERSEUS2)
/*
* NOTE: ALL DEFINITIONS IN THIS FILE NEED TO BE PREFIXED BY IDENTIFIER
* P2SAMPLE_ since they are specific to the EVM and not the chip.
*/
/* ---------------------------------------------------------------------------
* OMAP730 Debug Board FPGA
* ---------------------------------------------------------------------------
*
*/
/* maps in the FPGA registers and the ETHR registers */
#define OMAP730_FPGA_BASE 0xE8000000 /* VA */
#define OMAP730_FPGA_SIZE SZ_4K /* SIZE */
#define OMAP730_FPGA_START 0x04000000 /* PA */
#define OMAP730_FPGA_ETHR_START OMAP730_FPGA_START
#define OMAP730_FPGA_ETHR_BASE OMAP730_FPGA_BASE
#define OMAP730_FPGA_FPGA_REV (OMAP730_FPGA_BASE + 0x10) /* FPGA Revision */
#define OMAP730_FPGA_BOARD_REV (OMAP730_FPGA_BASE + 0x12) /* Board Revision */
#define OMAP730_FPGA_GPIO (OMAP730_FPGA_BASE + 0x14) /* GPIO outputs */
#define OMAP730_FPGA_LEDS (OMAP730_FPGA_BASE + 0x16) /* LEDs outputs */
#define OMAP730_FPGA_MISC_INPUTS (OMAP730_FPGA_BASE + 0x18) /* Misc inputs */
#define OMAP730_FPGA_LAN_STATUS (OMAP730_FPGA_BASE + 0x1A) /* LAN Status line */
#define OMAP730_FPGA_LAN_RESET (OMAP730_FPGA_BASE + 0x1C) /* LAN Reset line */
// LEDs definition on debug board (16 LEDs)
#define OMAP730_FPGA_LED_CLAIMRELEASE (1 << 15)
#define OMAP730_FPGA_LED_STARTSTOP (1 << 14)
#define OMAP730_FPGA_LED_HALTED (1 << 13)
#define OMAP730_FPGA_LED_IDLE (1 << 12)
#define OMAP730_FPGA_LED_TIMER (1 << 11)
// cpu0 load-meter LEDs
#define OMAP730_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ...
#define OMAP730_FPGA_LOAD_METER_SIZE 11
#define OMAP730_FPGA_LOAD_METER_MASK ((1 << OMAP730_FPGA_LOAD_METER_SIZE) - 1)
#ifndef OMAP_SDRAM_DEVICE
#define OMAP_SDRAM_DEVICE D256M_1X16_4B
#endif
/*
* These definitions define an area of FLASH set aside
* for the use of MTD/JFFS2. This is the area of flash
* that a JFFS2 filesystem will reside which is mounted
* at boot with the "root=/dev/mtdblock/0 rw"
* command line option.
*/
/* Intel flash_0, partitioned as expected by rrload */
#define OMAP_FLASH_0_BASE 0xD8000000 /* VA */
#define OMAP_FLASH_0_START 0x00000000 /* PA */
#define OMAP_FLASH_0_SIZE SZ_32M
/* 2.9.6 Traffic Controller Memory Interface Registers */
#define OMAP_FLASH_CFG_0 0xfffecc10
#define OMAP_FLASH_ACFG_0 0xfffecc50
#define OMAP_FLASH_CFG_1 0xfffecc14
#define OMAP_FLASH_ACFG_1 0xfffecc54
/*
* Configuration Registers
*/
#define PERSEUS2_CONFIG_BASE 0xfffe1000
#define PERSEUS2_IO_CONF_0 0xfffe1070
#define PERSEUS2_IO_CONF_1 0xfffe1074
#define PERSEUS2_IO_CONF_2 0xfffe1078
#define PERSEUS2_IO_CONF_3 0xfffe107c
#define PERSEUS2_IO_CONF_4 0xfffe1080
#define PERSEUS2_IO_CONF_5 0xfffe1084
#define PERSEUS2_IO_CONF_6 0xfffe1088
#define PERSEUS2_IO_CONF_7 0xfffe108c
#define PERSEUS2_IO_CONF_8 0xfffe1090
#define PERSEUS2_IO_CONF_9 0xfffe1094
#define PERSEUS2_IO_CONF_10 0xfffe1098
#define PERSEUS2_IO_CONF_11 0xfffe109c
#define PERSEUS2_IO_CONF_12 0xfffe10a0
#define PERSEUS2_IO_CONF_13 0xfffe10a4
#define PERSEUS2_MODE_1 0xfffe1010
#define PERSEUS2_MODE_2 0xfffe1014
/* CSMI specials: in terms of base + offset */
#define PERSEUS2_MODE2_OFFSET 0x14
/* DSP control: ICR registers */
#define ICR_BASE 0xfffbb800
/* M_CTL */
#define DSP_M_CTL ((volatile __u16 *)0xfffbb804)
/* DSP control: MMU registers */
#define DSP_MMU_BASE ((volatile __u16 *)0xfffed200)
/* The Ethernet Controller IRQ is cascaded to MPU_EXT_nIRQ througb the FPGA */
#define INT_ETHER INT_730_MPU_EXT_NIRQ
#define MAXIRQNUM IH_BOARD_BASE
#define MAXFIQNUM MAXIRQNUM
#define MAXSWINUM MAXIRQNUM
#define NR_IRQS (MAXIRQNUM + 1)
#ifndef __ASSEMBLY__
void fpga_write(unsigned char val, int reg);
unsigned char fpga_read(int reg);
#endif
/* PCC_UPLD control register: OMAP730 */
#define PCC_UPLD_CTRL_REG_BASE (0xfffe0900)
#define PCC_UPLD_CTRL_REG (volatile __u16 *)(PCC_UPLD_CTRL_REG_BASE + 0x00)
#else
#error "Only OMAP730 Perseus2 supported!"
#endif
#endif
include/asm-arm/arch-omap/omap1510.h 0 → 100644
View file @ ca927387
/* linux/include/asm-arm/arch-omap/omap1510.h
*
* Hardware definitions for TI OMAP1510 processor.
*
* Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_OMAP1510_H
#define __ASM_ARCH_OMAP1510_H
/*
* ----------------------------------------------------------------------------
* Base addresses
* ----------------------------------------------------------------------------
*/
/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
#define OMAP_SRAM_BASE 0xD0000000
#define OMAP_SRAM_SIZE (SZ_128K + SZ_64K)
#define OMAP_SRAM_START 0x20000000
#define OMAP_MCBSP1_BASE 0xE1011000
#define OMAP_MCBSP1_SIZE SZ_4K
#define OMAP_MCBSP1_START 0xE1011000
#define OMAP_MCBSP2_BASE 0xFFFB1000
#define OMAP_MCBSP3_BASE 0xE1017000
#define OMAP_MCBSP3_SIZE SZ_4K
#define OMAP_MCBSP3_START 0xE1017000
#endif /* __ASM_ARCH_OMAP1510_H */
include/asm-arm/arch-omap/omap1610.h 0 → 100644
View file @ ca927387
/* linux/include/asm-arm/arch-omap/omap1610.h
*
* Hardware definitions for TI OMAP1610 processor.
*
* Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_OMAP1610_H
#define __ASM_ARCH_OMAP1610_H
/*
* ----------------------------------------------------------------------------
* Base addresses
* ----------------------------------------------------------------------------
*/
/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
#define OMAP_SRAM_BASE 0xD0000000
#define OMAP_SRAM_SIZE (SZ_16K)
#define OMAP_SRAM_START 0x20000000
/*
* ----------------------------------------------------------------------------
* System control registers
* ----------------------------------------------------------------------------
*/
#define OMAP_RESET_CONTROL 0xfffe1140
#define ARM_IDLECT3 (CLKGEN_RESET_BASE + 0x24)
#define CONF_VOLTAGE_CTRL_0 0xfffe1060
#define CONF_VOLTAGE_VDDSHV6 (1 << 8)
#define CONF_VOLTAGE_VDDSHV7 (1 << 9)
#define CONF_VOLTAGE_VDDSHV8 (1 << 10)
#define CONF_VOLTAGE_VDDSHV9 (1 << 11)
#define SUBLVDS_CONF_VALID (1 << 13)
/*
* ---------------------------------------------------------------------------
* TIPB bus interface
* ---------------------------------------------------------------------------
*/
#define OMAP_TIPB_SWITCH 0xfffbc800
#define TIPB_BRIDGE_INT 0xfffeca00 /* Private TIPB_CNTL */
#define PRIVATE_MPU_TIPB_CNTL 0xfffeca08
#define TIPB_BRIDGE_EXT 0xfffed300 /* Public (Shared) TIPB_CNTL */
#define PUBLIC_MPU_TIPB_CNTL 0xfffed308
#define TIPB_SWITCH_CFG OMAP_TIPB_SWITCH
#define MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_CFG + 0x160)
#endif /* __ASM_ARCH_OMAP1610_H */
include/asm-arm/arch-omap/omap730.h 0 → 100644
View file @ ca927387
/* linux/include/asm-arm/arch-omap/omap730.h
*
* Hardware definitions for TI OMAP730 processor.
*
* Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_OMAP730_H
#define __ASM_ARCH_OMAP730_H
/*
* ----------------------------------------------------------------------------
* Base addresses
* ----------------------------------------------------------------------------
*/
/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
#define OMAP_SRAM_BASE 0xD0000000
#define OMAP_SRAM_SIZE (SZ_128K + SZ_64K + SZ_8K)
#define OMAP_SRAM_START 0x20000000
#define OMAP_MCBSP1_BASE 0xfffb1000
#define OMAP_MCBSP1_SIZE (SZ_1K * 2)
#define OMAP_MCBSP1_START 0xfffb1000
#define OMAP_MCBSP2_BASE 0xfffb1800
#endif /* __ASM_ARCH_OMAP730_H */
include/asm-arm/arch-omap/param.h 0 → 100644
View file @ ca927387
/*
* linux/include/asm-arm/arch-omap/param.h
*
* Initially based on linux/include/asm-arm/arch-integrator/param.h
* Copyright (C) 1999 ARM Limited
*
* BRIEF MODULE DESCRIPTION
* a place holder
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
include/asm-arm/arch-omap/pm.h 0 → 100644
View file @ ca927387
/*
* FILE NAME include/asm/arch-omap/pm.h
*
* BRIEF MODULE DESCRIPTION
*
* Author: MontaVista Software, Inc.
* support@mvista.com
*
* Copyright 2002 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* List of global OMAP registers to preserve. All registers are 16 bits
* and must be accessed with 16 read/writes.
* More ones like CP and general purpose register values are preserved
* with the stack pointer in sleep.S.
*/
#ifndef __ASM_ARCH_OMAP1510_PM_H
#define __ASM_ARCH_OMAP1510_PM_H
#define ARM_REG_BASE (0xfffece00)
#define ARM_ASM_IDLECT1 (ARM_REG_BASE + 0x4)
#define ARM_ASM_IDLECT2 (ARM_REG_BASE + 0x8)
#define ARM_ASM_RSTCT1 (ARM_REG_BASE + 0x10)
#define ARM_ASM_RSTCT2 (ARM_REG_BASE + 0x14)
#define ARM_ASM_SYSST (ARM_REG_BASE + 0x18)
/*
* Traffic Controller Memory Interface Registers
*/
#define TCMIF_BASE 0xfffecc00
#define EMIFS_ASM_CONFIG_REG (TCMIF_BASE + 0x0c)
#define EMIFF_ASM_SDRAM_CONFIG (TCMIF_BASE + 0x20)
#define IRQ_MIR1 (volatile unsigned int *)(OMAP_IH1_BASE + IRQ_MIR)
#define IRQ_MIR2 (volatile unsigned int *)(OMAP_IH2_BASE + IRQ_MIR)
#define IDLE_WAIT_CYCLES 0x000000ff
#define PERIPHERAL_ENABLE 0x2
#define BIG_SLEEP_REQUEST 0x0cc5
#define IDLE_LOOP_REQUEST 0x0c00
#define SELF_REFRESH_MODE 0x0c000001
#define IDLE_EMIFS_REQUEST 0xc
#define IDLE_CLOCK_DOMAINS 0x2
#define MODEM_32K_EN 0x1
#ifndef __ASSEMBLER__
extern void omap1510_pm_idle(void);
extern void omap_pm_suspend(void);
extern int omap1510_cpu_suspend(void);
extern int omap1510_idle_loop_suspend(void);
extern struct async_struct *omap_pm_sercons;
extern unsigned int serial_in(struct async_struct *, int);
extern unsigned int serial_out(struct async_struct *, int, int);
#define OMAP1510_SRAM_IDLE_SUSPEND 0xd002F000
#define OMAP1510_SRAM_API_SUSPEND 0xd002F200
#define CPU_SUSPEND_SIZE 200
#define ARM_REG_BASE (0xfffece00)
#define ARM_ASM_IDLECT1 (ARM_REG_BASE + 0x4)
#define ARM_ASM_IDLECT2 (ARM_REG_BASE + 0x8)
#define ARM_ASM_RSTCT1 (ARM_REG_BASE + 0x10)
#define ARM_ASM_RSTCT2 (ARM_REG_BASE + 0x14)
#define ARM_ASM_SYSST (ARM_REG_BASE + 0x18)
#define TCMIF_BASE 0xfffecc00
#define PM_EMIFS_CONFIG_REG (volatile unsigned int *)(TCMIF_BASE + 0x0c)
#define PM_EMIFF_SDRAM_CONFIG (volatile unsigned int *)(TCMIF_BASE + 0x20)
#define ULPD_LOW_POWER_REQ 0x3
#define DSP_IDLE_DELAY 10
#define DSP_IDLE 0x0040
#define DSP_ENABLE 0x0002
#define SUFFICIENT_DSP_RESET_TIME 1000
#define DEFAULT_MPUI_CONFIG 0x05cf
#define ENABLE_XORCLK 0x2
#define DSP_RESET 0x2000
#define TC_IDLE_REQUEST (0x0000000c)
#define EMIFF_CONFIG_REG EMIFF_SDRAM_CONFIG
#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = (unsigned short)*x
#define ARM_RESTORE(x) *x = (unsigned short)arm_sleep_save[ARM_SLEEP_SAVE_##x]
#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = (unsigned short)*x
#define ULPD_RESTORE(x) *x = (unsigned short)ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
#define MPUI_SAVE(x) mpui_sleep_save[MPUI_SLEEP_SAVE_##x] = (unsigned int)*x
#define MPUI_RESTORE(x) *x = (unsigned int)mpui_sleep_save[MPUI_SLEEP_SAVE_##x]
#define MPUI_SHOW(x) (unsigned int)mpui_sleep_save[MPUI_SLEEP_SAVE_##x]
enum arm_save_state {
ARM_SLEEP_SAVE_START = 0,
/*
* 9 MPU control registers, all 16 bits
*/
ARM_SLEEP_SAVE_ARM_CKCTL, ARM_SLEEP_SAVE_ARM_IDLECT1,
ARM_SLEEP_SAVE_ARM_IDLECT2, ARM_SLEEP_SAVE_ARM_EWUPCT,
ARM_SLEEP_SAVE_ARM_RSTCT1, ARM_SLEEP_SAVE_ARM_RSTCT2,
ARM_SLEEP_SAVE_ARM_SYSST,
ARM_SLEEP_SAVE_SIZE
};
enum ulpd_save_state {
ULDP_SLEEP_SAVE_START = 0,
ULPD_SLEEP_SAVE_ULPD_IT_STATUS_REG, ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL_REG,
ULPD_SLEEP_SAVE_ULPD_SOFT_REQ_REG, ULPD_SLEEP_SAVE_ULPD_STATUS_REQ_REG,
ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL_REG, ULPD_SLEEP_SAVE_ULPD_POWER_CTRL_REG,
ULPD_SLEEP_SAVE_SIZE
};
enum mpui_save_state {
/*
* MPUI registers 32 bits
*/
MPUI_SLEEP_SAVE_MPUI_CTRL_REG, MPUI_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
MPUI_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
MPUI_SLEEP_SAVE_MPUI_DSP_STATUS_REG,
MPUI_SLEEP_SAVE_PM_EMIFF_SDRAM_CONFIG,
MPUI_SLEEP_SAVE_PM_EMIFS_CONFIG_REG,
MPUI_SLEEP_SAVE_IRQ_MIR1, MPUI_SLEEP_SAVE_IRQ_MIR2,
MPUI_SLEEP_SAVE_SIZE
};
#endif /* ASSEMBLER */
#endif
include/asm-arm/arch-omap/serial.h 0 → 100644
View file @ ca927387
/*
* linux/include/asm-arm/arch-omap/serial.h
*
* BRIEF MODULE DESCRIPTION
* serial definitions
*
*/
#ifndef __ASM_ARCH_SERIAL_H
#define __ASM_ARCH_SERIAL_H
#define OMAP1510_UART1_BASE (unsigned char *)0xfffb0000
#define OMAP1510_UART2_BASE (unsigned char *)0xfffb0800
#define OMAP1510_UART3_BASE (unsigned char *)0xfffb9800
#define OMAP730_UART1_BASE (unsigned char *)0xfffb0000
#define OMAP730_UART2_BASE (unsigned char *)0xfffb0800
#if defined(CONFIG_ARCH_OMAP1510) || defined(CONFIG_ARCH_OMAP1610)
#define OMAP_SERIAL_REG_SHIFT 2
#else
#define OMAP_SERIAL_REG_SHIFT 0
#endif
#ifndef __ASSEMBLY__
#include <asm/arch/hardware.h>
#include <asm/irq.h>
/* UART3 Registers Maping through MPU bus */
#define OMAP_MPU_UART3_BASE 0xFFFB9800 /* UART3 through MPU bus */
#define UART3_RHR (OMAP_MPU_UART3_BASE + 0)
#define UART3_THR (OMAP_MPU_UART3_BASE + 0)
#define UART3_DLL (OMAP_MPU_UART3_BASE + 0)
#define UART3_IER (OMAP_MPU_UART3_BASE + 4)
#define UART3_DLH (OMAP_MPU_UART3_BASE + 4)
#define UART3_IIR (OMAP_MPU_UART3_BASE + 8)
#define UART3_FCR (OMAP_MPU_UART3_BASE + 8)
#define UART3_EFR (OMAP_MPU_UART3_BASE + 8)
#define UART3_LCR (OMAP_MPU_UART3_BASE + 0x0C)
#define UART3_MCR (OMAP_MPU_UART3_BASE + 0x10)
#define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10)
#define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14)
#define UART3_LSR (OMAP_MPU_UART3_BASE + 0x14)
#define UART3_TCR (OMAP_MPU_UART3_BASE + 0x18)
#define UART3_MSR (OMAP_MPU_UART3_BASE + 0x18)
#define UART3_XOFF1 (OMAP_MPU_UART3_BASE + 0x18)
#define UART3_XOFF2 (OMAP_MPU_UART3_BASE + 0x1C)
#define UART3_SPR (OMAP_MPU_UART3_BASE + 0x1C)
#define UART3_TLR (OMAP_MPU_UART3_BASE + 0x1C)
#define UART3_MDR1 (OMAP_MPU_UART3_BASE + 0x20)
#define UART3_MDR2 (OMAP_MPU_UART3_BASE + 0x24)
#define UART3_SFLSR (OMAP_MPU_UART3_BASE + 0x28)
#define UART3_TXFLL (OMAP_MPU_UART3_BASE + 0x28)
#define UART3_RESUME (OMAP_MPU_UART3_BASE + 0x2C)
#define UART3_TXFLH (OMAP_MPU_UART3_BASE + 0x2C)
#define UART3_SFREGL (OMAP_MPU_UART3_BASE + 0x30)
#define UART3_RXFLL (OMAP_MPU_UART3_BASE + 0x30)
#define UART3_SFREGH (OMAP_MPU_UART3_BASE + 0x34)
#define UART3_RXFLH (OMAP_MPU_UART3_BASE + 0x34)
#define UART3_BLR (OMAP_MPU_UART3_BASE + 0x38)
#define UART3_ACREG (OMAP_MPU_UART3_BASE + 0x3C)
#define UART3_DIV16 (OMAP_MPU_UART3_BASE + 0x3C)
#define UART3_SCR (OMAP_MPU_UART3_BASE + 0x40)
#define UART3_SSR (OMAP_MPU_UART3_BASE + 0x44)
#define UART3_EBLR (OMAP_MPU_UART3_BASE + 0x48)
#define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C)
#define UART3_MVR (OMAP_MPU_UART3_BASE + 0x50)
#ifdef CONFIG_ARCH_OMAP1510
#define BASE_BAUD (12000000/16)
#endif
#ifdef CONFIG_ARCH_OMAP1610
#define BASE_BAUD (48000000/16)
#endif
#ifdef CONFIG_ARCH_OMAP730
#define BASE_BAUD (48000000/16)
#define RS_TABLE_SIZE 2
#define STD_COM_FLAGS (ASYNC_SKIP_TEST)
#define STD_SERIAL_PORT_DEFNS \
{ \
.uart = PORT_OMAP, \
.baud_base = BASE_BAUD, \
.iomem_base = OMAP730_UART1_BASE, \
.iomem_reg_shift = 0, \
.io_type = SERIAL_IO_MEM, \
.irq = INT_UART1, \
.flags = STD_COM_FLAGS, \
}, { \
.uart = PORT_OMAP, \
.baud_base = BASE_BAUD, \
.iomem_base = OMAP730_UART2_BASE, \
.iomem_reg_shift = 0, \
.io_type = SERIAL_IO_MEM, \
.irq = INT_UART2, \
.flags = STD_COM_FLAGS, \
}
#else
#define RS_TABLE_SIZE 3
#define STD_COM_FLAGS (ASYNC_SKIP_TEST)
#define STD_SERIAL_PORT_DEFNS \
{ \
.uart = PORT_OMAP, \
.baud_base = BASE_BAUD, \
.iomem_base = OMAP1510_UART1_BASE, \
.iomem_reg_shift = 2, \
.io_type = SERIAL_IO_MEM, \
.irq = INT_UART1, \
.flags = STD_COM_FLAGS, \
}, { \
.uart = PORT_OMAP, \
.baud_base = BASE_BAUD, \
.iomem_base = OMAP1510_UART2_BASE, \
.iomem_reg_shift = 2, \
.io_type = SERIAL_IO_MEM, \
.irq = INT_UART2, \
.flags = STD_COM_FLAGS, \
}, { \
.uart = PORT_OMAP, \
.baud_base = BASE_BAUD, \
.iomem_base = OMAP1510_UART3_BASE, \
.iomem_reg_shift = 2, \
.io_type = SERIAL_IO_MEM, \
.irq = INT_UART3, \
.flags = STD_COM_FLAGS, \
}
#endif /* CONFIG_ARCH_OMAP730 */
#define EXTRA_SERIAL_PORT_DEFNS
/* OMAP FCR trigger redefinitions */
#define UART_FCR_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 8 */
#define UART_FCR_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 16 */
#define UART_FCR_R_TRIGGER_56 0x80 /* Mask for receive trigger set at 56 */
#define UART_FCR_R_TRIGGER_60 0xC0 /* Mask for receive trigger set at 60 */
/* There is an error in the description of the transmit trigger levels of
OMAP5910 TRM from January 2003. The transmit trigger level 56 is not
56 but 32, the transmit trigger level 60 is not 60 but 56!
Additionally, the descritption of these trigger levels is
a little bit unclear. The trigger level define the number of EMPTY
entries in the FIFO. Thus, if TRIGGER_8 is used, an interrupt is requested
if 8 FIFO entries are empty (and 56 entries are still filled [the FIFO
size is 64]). Or: If TRIGGER_56 is selected, everytime there are less than
8 characters in the FIFO, an interrrupt is spawned. In other words: The
trigger number is equal the number of characters which can be
written without FIFO overrun */
#define UART_FCR_T_TRIGGER_8 0x00 /* Mask for transmit trigger set at 8 */
#define UART_FCR_T_TRIGGER_16 0x10 /* Mask for transmit trigger set at 16 */
#define UART_FCR_T_TRIGGER_32 0x20 /* Mask for transmit trigger set at 32 */
#define UART_FCR_T_TRIGGER_56 0x30 /* Mask for transmit trigger set at 56 */
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_SERIAL_H */
include/asm-arm/arch-omap/system.h 0 → 100644
View file @ ca927387
/*
* Copied from linux/include/asm-arm/arch-sa1100/system.h
* Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <linux/config.h>
#include <asm/arch/hardware.h>
static inline void arch_idle(void)
{
cpu_do_idle();
}
static inline void arch_reset(char mode)
{
*(volatile u16 *)(ARM_RSTCT1) = 1;
}
#endif
include/asm-arm/arch-omap/time.h 0 → 100644
View file @ ca927387
/*
* linux/include/asm-arm/arch-omap/time.h
*
* 32kHz timer definition
*
* Copyright (C) 2000 RidgeRun, Inc.
* Author: Greg Lonnon <glonnon@ridgerun.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#if !defined(__ASM_ARCH_OMAP_TIME_H)
#define __ASM_ARCH_OMAP_TIME_H
#include <linux/config.h>
#include <linux/delay.h>
#include <asm/system.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/leds.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <asm/arch/clocks.h>
#ifndef __instrument
#define __instrument
#define __noinstrument __attribute__ ((no_instrument_function))
#endif
typedef struct {
u32 cntl; /* CNTL_TIMER, R/W */
u32 load_tim; /* LOAD_TIM, W */
u32 read_tim; /* READ_TIM, R */
} mputimer_regs_t;
#define mputimer_base(n) \
((volatile mputimer_regs_t*)(OMAP_MPUTIMER_BASE + \
(n)*OMAP_MPUTIMER_OFF))
static inline unsigned long timer32k_read(int reg) {
unsigned long val;
val = (inw(IO_ADDRESS((reg) + OMAP_32kHz_TIMER_BASE)));
return val;
}
static inline void timer32k_write(int reg,int val) {
outw( (val), (IO_ADDRESS( (reg) + OMAP_32kHz_TIMER_BASE)));
}
/*
* How long is the timer interval? 100 HZ, right...
* IRQ rate = (TVR + 1) / 32768 seconds
* TVR = 32768 * IRQ_RATE -1
* IRQ_RATE = 1/100
* TVR = 326
*/
#define TIMER32k_PERIOD 326
//#define TIMER32k_PERIOD 0x7ff
static inline void start_timer32k(void) {
timer32k_write(TIMER32k_CR,
TIMER32k_TSS | TIMER32k_TRB |
TIMER32k_INT | TIMER32k_ARL);
}
#ifdef CONFIG_MACH_OMAP_PERSEUS2
/*
* After programming PTV with 0 and setting the MPUTIM_CLOCK_ENABLE
* (external clock enable) bit, the timer count rate is 6.5 MHz (13
* MHZ input/2). !! The divider by 2 is undocumented !!
*/
#define MPUTICKS_PER_SEC (13000000/2)
#else
/*
* After programming PTV with 0, the timer count rate is 6 MHz.
* WARNING! this must be an even number, or machinecycles_to_usecs
* below will break.
*/
#define MPUTICKS_PER_SEC (12000000/2)
#endif
static int mputimer_started[3] = {0,0,0};
static inline void __noinstrument start_mputimer(int n,
unsigned long load_val)
{
volatile mputimer_regs_t* timer = mputimer_base(n);
mputimer_started[n] = 0;
timer->cntl = MPUTIM_CLOCK_ENABLE;
udelay(1);
timer->load_tim = load_val;
udelay(1);
timer->cntl = (MPUTIM_CLOCK_ENABLE | MPUTIM_AR | MPUTIM_ST);
mputimer_started[n] = 1;
}
static inline unsigned long __noinstrument
read_mputimer(int n)
{
volatile mputimer_regs_t* timer = mputimer_base(n);
return (mputimer_started[n] ? timer->read_tim : 0);
}
void __noinstrument start_mputimer1(unsigned long load_val)
{
start_mputimer(0, load_val);
}
void __noinstrument start_mputimer2(unsigned long load_val)
{
start_mputimer(1, load_val);
}
void __noinstrument start_mputimer3(unsigned long load_val)
{
start_mputimer(2, load_val);
}
unsigned long __noinstrument read_mputimer1(void)
{
return read_mputimer(0);
}
unsigned long __noinstrument read_mputimer2(void)
{
return read_mputimer(1);
}
unsigned long __noinstrument read_mputimer3(void)
{
return read_mputimer(2);
}
unsigned long __noinstrument do_getmachinecycles(void)
{
return 0 - read_mputimer(0);
}
unsigned long __noinstrument machinecycles_to_usecs(unsigned long mputicks)
{
/* Round up to nearest usec */
return ((mputicks * 1000) / (MPUTICKS_PER_SEC / 2 / 1000) + 1) >> 1;
}
/*
* This marks the time of the last system timer interrupt
* that was *processed by the ISR* (timer 2).
*/
static unsigned long systimer_mark;
static unsigned long omap1510_gettimeoffset(void)
{
/* Return elapsed usecs since last system timer ISR */
return machinecycles_to_usecs(do_getmachinecycles() - systimer_mark);
}
static irqreturn_t
omap1510_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
unsigned long now, ilatency;
/*
* Mark the time at which the timer interrupt ocurred using
* timer1. We need to remove interrupt latency, which we can
* retrieve from the current system timer2 counter. Both the
* offset timer1 and the system timer2 are counting at 6MHz,
* so we're ok.
*/
now = 0 - read_mputimer1();
ilatency = MPUTICKS_PER_SEC / 100 - read_mputimer2();
systimer_mark = now - ilatency;
do_leds();
do_timer(regs);
do_profile(regs);
return IRQ_HANDLED;
}
void __init time_init(void)
{
/* Since we don't call request_irq, we must init the structure */
gettimeoffset = omap1510_gettimeoffset;
timer_irq.handler = omap1510_timer_interrupt;
timer_irq.flags = SA_INTERRUPT;
#ifdef OMAP1510_USE_32KHZ_TIMER
timer32k_write(TIMER32k_CR, 0x0);
timer32k_write(TIMER32k_TVR,TIMER32k_PERIOD);
setup_irq(INT_OS_32kHz_TIMER, &timer_irq);
start_timer32k();
#else
setup_irq(INT_TIMER2, &timer_irq);
start_mputimer2(MPUTICKS_PER_SEC / 100 - 1);
#endif
}
#endif
include/asm-arm/arch-omap/timex.h 0 → 100644
View file @ ca927387
/*
* linux/include/asm-arm/arch-omap/timex.h
*
* Copyright (C) 2000 RidgeRun, Inc.
* Author: Greg Lonnon <glonnon@ridgerun.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#if !defined(__ASM_ARCH_OMAP_TIMEX_H)
#define __ASM_ARCH_OMAP_TIMEX_H
#include <asm/arch/clocks.h>
/* TC clock */
#define CLOCK_TICK_RATE ((OMAP_CK_MAX_RATE*1000000)/2)
#endif /* __ASM_ARCH_OMAP_TIMEX_H */
include/asm-arm/arch-omap/uncompress.h 0 → 100644
View file @ ca927387
/*
* linux/include/asm-arm/arch-omap/uncompress.h
*
* Serial port stubs for kernel decompress status messages
*
* Initially based on:
* linux-2.4.15-rmk1-dsplinux1.6/include/asm-arm/arch-omap1510/uncompress.h
* Copyright (C) 2000 RidgeRun, Inc.
* Author: Greg Lonnon <glonnon@ridgerun.com>
*
* Rewritten by:
* Author: <source@mvista.com>
* 2004 (c) MontaVista Software, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <linux/config.h>
#include <linux/types.h>
#include <linux/serial_reg.h>
#include <asm/mach-types.h>
#include <asm/hardware.h>
#include <asm/arch/serial.h>
#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
static void
puts(const char *s)
{
volatile u8 * uart = 0;
int shift = 0;
/* Determine which serial port to use */
do {
if (machine_is_innovator()) {
shift = 2;
uart = (volatile u8 *)(OMAP1510_UART1_BASE);
} else {
/* Assume nothing for unknown machines.
* Add an entry for your machine to select
* the default serial console here. If the
* serial port is enabled, we'll use it to
* display status messages. Else we'll be
* quiet.
*/
return;
}
if (check_port(uart, shift))
break;
/* Silent boot if no serial ports are enabled. */
return;
} while (0);
/*
* Now, xmit each character
*/
while (*s) {
while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
barrier();
uart[UART_TX << shift] = *s;
if (*s++ == '\n') {
while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
barrier();
uart[UART_TX << shift] = '\r';
}
}
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()
include/asm-arm/arch-omap/vmalloc.h 0 → 100644
View file @ ca927387
/*
* linux/include/asm-arm/arch-omap/vmalloc.h
*
* Copyright (C) 2000 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
#define MODULE_START (PAGE_OFFSET - 16*1048576)
#define MODULE_END (PAGE_OFFSET)
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