Commit ca94573b authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman

powerpc/mm/radix: Update pte update sequence for pte clear case

In the kernel we do follow the below sequence in different code paths.
pte = ptep_get_clear(ptep)
....
set_pte_at(ptep, pte)

We do that for mremap, autonuma protection update and softdirty clearing. This
implies our optimization to skip a tlb flush when clearing a pte update is
not valid, because for DD1 system that followup set_pte_at will be done witout
doing the required tlbflush. Fix that by always doing the dd1 style pte update
irrespective of new_pte value. In a later patch we will optimize the application
exit case.
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Tested-by: default avatarMichael Neuling <mikey@neuling.org>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 18061c17
...@@ -144,16 +144,10 @@ static inline unsigned long radix__pte_update(struct mm_struct *mm, ...@@ -144,16 +144,10 @@ static inline unsigned long radix__pte_update(struct mm_struct *mm,
* new value of pte * new value of pte
*/ */
new_pte = (old_pte | set) & ~clr; new_pte = (old_pte | set) & ~clr;
/*
* If we are trying to clear the pte, we can skip
* the below sequence and batch the tlb flush. The
* tlb flush batching is done by mmu gather code
*/
if (new_pte) {
asm volatile("ptesync" : : : "memory"); asm volatile("ptesync" : : : "memory");
radix__flush_tlb_pte_p9_dd1(old_pte, mm, addr); radix__flush_tlb_pte_p9_dd1(old_pte, mm, addr);
if (new_pte)
__radix_pte_update(ptep, 0, new_pte); __radix_pte_update(ptep, 0, new_pte);
}
} else } else
old_pte = __radix_pte_update(ptep, clr, set); old_pte = __radix_pte_update(ptep, clr, set);
asm volatile("ptesync" : : : "memory"); asm volatile("ptesync" : : : "memory");
......
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