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Commit cb1e06e0 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nvf0/gr: initial register/context setup 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 507cd5b5
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Inline Side-by-side
Showing with 1057 additions and 482 deletions
drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c
View file @ cb1e06e0
...@@ -2190,6 +2190,15 @@ nve0_grctx_generate_902d(struct nvc0_graph_priv *priv) ...@@ -2190,6 +2190,15 @@ nve0_grctx_generate_902d(struct nvc0_graph_priv *priv)
static void static void
nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv) nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv)
{ {
switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x404004, 0x00000000);
nv_wr32(priv, 0x404008, 0x00000000);
nv_wr32(priv, 0x40400c, 0x00000000);
break;
default:
break;
}
nv_wr32(priv, 0x404010, 0x0); nv_wr32(priv, 0x404010, 0x0);
nv_wr32(priv, 0x404014, 0x0); nv_wr32(priv, 0x404014, 0x0);
nv_wr32(priv, 0x404018, 0x0); nv_wr32(priv, 0x404018, 0x0);
...@@ -2197,6 +2206,19 @@ nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv) ...@@ -2197,6 +2206,19 @@ nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x404020, 0x0); nv_wr32(priv, 0x404020, 0x0);
nv_wr32(priv, 0x404024, 0xe000); nv_wr32(priv, 0x404024, 0xe000);
nv_wr32(priv, 0x404028, 0x0); nv_wr32(priv, 0x404028, 0x0);
switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x40402c, 0x00000000);
nv_wr32(priv, 0x404030, 0x00000000);
nv_wr32(priv, 0x404034, 0x00000000);
nv_wr32(priv, 0x404038, 0x00000000);
nv_wr32(priv, 0x40403c, 0x00000000);
nv_wr32(priv, 0x404040, 0x00000000);
nv_wr32(priv, 0x404044, 0x00000000);
break;
default:
break;
}
nv_wr32(priv, 0x4040a8, 0x0); nv_wr32(priv, 0x4040a8, 0x0);
nv_wr32(priv, 0x4040ac, 0x0); nv_wr32(priv, 0x4040ac, 0x0);
nv_wr32(priv, 0x4040b0, 0x0); nv_wr32(priv, 0x4040b0, 0x0);
...@@ -2214,6 +2236,22 @@ nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv) ...@@ -2214,6 +2236,22 @@ nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x4040e4, 0x0); nv_wr32(priv, 0x4040e4, 0x0);
nv_wr32(priv, 0x4040e8, 0x1000); nv_wr32(priv, 0x4040e8, 0x1000);
nv_wr32(priv, 0x4040f8, 0x0); nv_wr32(priv, 0x4040f8, 0x0);
switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x404100, 0x00000000);
nv_wr32(priv, 0x404104, 0x00000000);
nv_wr32(priv, 0x404108, 0x00000000);
nv_wr32(priv, 0x40410c, 0x00000000);
nv_wr32(priv, 0x404110, 0x00000000);
nv_wr32(priv, 0x404114, 0x00000000);
nv_wr32(priv, 0x404118, 0x00000000);
nv_wr32(priv, 0x40411c, 0x00000000);
nv_wr32(priv, 0x404120, 0x00000000);
nv_wr32(priv, 0x404124, 0x00000000);
break;
default:
break;
}
nv_wr32(priv, 0x404130, 0x0); nv_wr32(priv, 0x404130, 0x0);
nv_wr32(priv, 0x404134, 0x0); nv_wr32(priv, 0x404134, 0x0);
nv_wr32(priv, 0x404138, 0x20000040); nv_wr32(priv, 0x404138, 0x20000040);
...@@ -2221,14 +2259,32 @@ nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv) ...@@ -2221,14 +2259,32 @@ nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x404154, 0x400); nv_wr32(priv, 0x404154, 0x400);
nv_wr32(priv, 0x404158, 0x200); nv_wr32(priv, 0x404158, 0x200);
nv_wr32(priv, 0x404164, 0x55); nv_wr32(priv, 0x404164, 0x55);
switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x40417c, 0x00000000);
nv_wr32(priv, 0x404180, 0x00000000);
break;
default:
break;
}
nv_wr32(priv, 0x4041a0, 0x0); nv_wr32(priv, 0x4041a0, 0x0);
nv_wr32(priv, 0x4041a4, 0x0); nv_wr32(priv, 0x4041a4, 0x0);
nv_wr32(priv, 0x4041a8, 0x0); nv_wr32(priv, 0x4041a8, 0x0);
nv_wr32(priv, 0x4041ac, 0x0); nv_wr32(priv, 0x4041ac, 0x0);
nv_wr32(priv, 0x404200, 0x0); switch (nv_device(priv)->chipset) {
nv_wr32(priv, 0x404204, 0x0); case 0xf0:
nv_wr32(priv, 0x404208, 0x0); nv_wr32(priv, 0x404200, 0xa197);
nv_wr32(priv, 0x40420c, 0x0); nv_wr32(priv, 0x404204, 0xa1c0);
nv_wr32(priv, 0x404208, 0xa140);
nv_wr32(priv, 0x40420c, 0x902d);
break;
default:
nv_wr32(priv, 0x404200, 0x0);
nv_wr32(priv, 0x404204, 0x0);
nv_wr32(priv, 0x404208, 0x0);
nv_wr32(priv, 0x40420c, 0x0);
break;
}
} }
static void static void
...@@ -2246,7 +2302,13 @@ nve0_graph_generate_unk44xx(struct nvc0_graph_priv *priv) ...@@ -2246,7 +2302,13 @@ nve0_graph_generate_unk44xx(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x404428, 0x0); nv_wr32(priv, 0x404428, 0x0);
nv_wr32(priv, 0x40442c, 0x0); nv_wr32(priv, 0x40442c, 0x0);
nv_wr32(priv, 0x404430, 0x0); nv_wr32(priv, 0x404430, 0x0);
nv_wr32(priv, 0x404434, 0x0); switch (nv_device(priv)->chipset) {
case 0xf0:
break;
default:
nv_wr32(priv, 0x404434, 0x0);
break;
}
nv_wr32(priv, 0x404438, 0x0); nv_wr32(priv, 0x404438, 0x0);
nv_wr32(priv, 0x404460, 0x0); nv_wr32(priv, 0x404460, 0x0);
nv_wr32(priv, 0x404464, 0x0); nv_wr32(priv, 0x404464, 0x0);
...@@ -2339,12 +2401,26 @@ nve0_graph_generate_unk5bxx(struct nvc0_graph_priv *priv) ...@@ -2339,12 +2401,26 @@ nve0_graph_generate_unk5bxx(struct nvc0_graph_priv *priv)
{ {
nv_wr32(priv, 0x405b00, 0x0); nv_wr32(priv, 0x405b00, 0x0);
nv_wr32(priv, 0x405b10, 0x1000); nv_wr32(priv, 0x405b10, 0x1000);
switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x405b20, 0x04000000);
break;
default:
break;
}
} }
static void static void
nve0_graph_generate_unk60xx(struct nvc0_graph_priv *priv) nve0_graph_generate_unk60xx(struct nvc0_graph_priv *priv)
{ {
nv_wr32(priv, 0x406020, 0x4103c1); switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x406020, 0x34103c1);
break;
default:
nv_wr32(priv, 0x406020, 0x4103c1);
break;
}
nv_wr32(priv, 0x406028, 0x1); nv_wr32(priv, 0x406028, 0x1);
nv_wr32(priv, 0x40602c, 0x1); nv_wr32(priv, 0x40602c, 0x1);
nv_wr32(priv, 0x406030, 0x1); nv_wr32(priv, 0x406030, 0x1);
...@@ -2356,11 +2432,27 @@ nve0_graph_generate_unk64xx(struct nvc0_graph_priv *priv) ...@@ -2356,11 +2432,27 @@ nve0_graph_generate_unk64xx(struct nvc0_graph_priv *priv)
{ {
nv_wr32(priv, 0x4064a8, 0x0); nv_wr32(priv, 0x4064a8, 0x0);
nv_wr32(priv, 0x4064ac, 0x3fff); nv_wr32(priv, 0x4064ac, 0x3fff);
switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x4064b0, 0x0);
break;
default:
break;
}
nv_wr32(priv, 0x4064b4, 0x0); nv_wr32(priv, 0x4064b4, 0x0);
nv_wr32(priv, 0x4064b8, 0x0); nv_wr32(priv, 0x4064b8, 0x0);
nv_wr32(priv, 0x4064c0, 0x801a00f0); switch (nv_device(priv)->chipset) {
nv_wr32(priv, 0x4064c4, 0x192ffff); case 0xf0:
nv_wr32(priv, 0x4064c8, 0x1800600); nv_wr32(priv, 0x4064c0, 0x802000f0);
nv_wr32(priv, 0x4064c4, 0x192ffff);
nv_wr32(priv, 0x4064c8, 0x18007c0);
break;
default:
nv_wr32(priv, 0x4064c0, 0x801a00f0);
nv_wr32(priv, 0x4064c4, 0x192ffff);
nv_wr32(priv, 0x4064c8, 0x1800600);
break;
}
nv_wr32(priv, 0x4064cc, 0x0); nv_wr32(priv, 0x4064cc, 0x0);
nv_wr32(priv, 0x4064d0, 0x0); nv_wr32(priv, 0x4064d0, 0x0);
nv_wr32(priv, 0x4064d4, 0x0); nv_wr32(priv, 0x4064d4, 0x0);
...@@ -2376,7 +2468,13 @@ nve0_graph_generate_unk64xx(struct nvc0_graph_priv *priv) ...@@ -2376,7 +2468,13 @@ nve0_graph_generate_unk64xx(struct nvc0_graph_priv *priv)
static void static void
nve0_graph_generate_unk70xx(struct nvc0_graph_priv *priv) nve0_graph_generate_unk70xx(struct nvc0_graph_priv *priv)
{ {
nv_wr32(priv, 0x407040, 0x0); switch (nv_device(priv)->chipset) {
case 0xf0:
break;
default:
nv_wr32(priv, 0x407040, 0x0);
break;
}
} }
static void static void
...@@ -2408,9 +2506,23 @@ nve0_graph_generate_unk80xx(struct nvc0_graph_priv *priv) ...@@ -2408,9 +2506,23 @@ nve0_graph_generate_unk80xx(struct nvc0_graph_priv *priv)
static void static void
nve0_graph_generate_unk88xx(struct nvc0_graph_priv *priv) nve0_graph_generate_unk88xx(struct nvc0_graph_priv *priv)
{ {
nv_wr32(priv, 0x408800, 0x2802a3c); switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x408800, 0x12802a3c);
break;
default:
nv_wr32(priv, 0x408800, 0x2802a3c);
break;
}
nv_wr32(priv, 0x408804, 0x40); nv_wr32(priv, 0x408804, 0x40);
nv_wr32(priv, 0x408808, 0x1043e005); switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x408808, 0x1003e005);
break;
default:
nv_wr32(priv, 0x408808, 0x1043e005);
break;
}
nv_wr32(priv, 0x408840, 0xb); nv_wr32(priv, 0x408840, 0xb);
nv_wr32(priv, 0x408900, 0x3080b801); nv_wr32(priv, 0x408900, 0x3080b801);
nv_wr32(priv, 0x408904, 0x62000001); nv_wr32(priv, 0x408904, 0x62000001);
...@@ -2447,7 +2559,14 @@ nve0_graph_generate_gpc(struct nvc0_graph_priv *priv) ...@@ -2447,7 +2559,14 @@ nve0_graph_generate_gpc(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x418710, 0x0); nv_wr32(priv, 0x418710, 0x0);
nv_wr32(priv, 0x418800, 0x7006860a); nv_wr32(priv, 0x418800, 0x7006860a);
nv_wr32(priv, 0x418808, 0x0); nv_wr32(priv, 0x418808, 0x0);
nv_wr32(priv, 0x41880c, 0x0); switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x41880c, 0x30);
break;
default:
nv_wr32(priv, 0x41880c, 0x0);
break;
}
nv_wr32(priv, 0x418810, 0x0); nv_wr32(priv, 0x418810, 0x0);
nv_wr32(priv, 0x418828, 0x44); nv_wr32(priv, 0x418828, 0x44);
nv_wr32(priv, 0x418830, 0x10000001); nv_wr32(priv, 0x418830, 0x10000001);
...@@ -2493,6 +2612,13 @@ nve0_graph_generate_gpc(struct nvc0_graph_priv *priv) ...@@ -2493,6 +2612,13 @@ nve0_graph_generate_gpc(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x418c6c, 0x1); nv_wr32(priv, 0x418c6c, 0x1);
nv_wr32(priv, 0x418c80, 0x20200004); nv_wr32(priv, 0x418c80, 0x20200004);
nv_wr32(priv, 0x418c8c, 0x1); nv_wr32(priv, 0x418c8c, 0x1);
switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x418d24, 0x0);
break;
default:
break;
}
nv_wr32(priv, 0x419000, 0x780); nv_wr32(priv, 0x419000, 0x780);
nv_wr32(priv, 0x419004, 0x0); nv_wr32(priv, 0x419004, 0x0);
nv_wr32(priv, 0x419008, 0x0); nv_wr32(priv, 0x419008, 0x0);
...@@ -2512,31 +2638,71 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv) ...@@ -2512,31 +2638,71 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x419a10, 0x0); nv_wr32(priv, 0x419a10, 0x0);
nv_wr32(priv, 0x419a14, 0x200); nv_wr32(priv, 0x419a14, 0x200);
nv_wr32(priv, 0x419a1c, 0xc000); nv_wr32(priv, 0x419a1c, 0xc000);
nv_wr32(priv, 0x419a20, 0x800); switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x419a20, 0x20800);
break;
default:
nv_wr32(priv, 0x419a20, 0x800);
break;
}
nv_wr32(priv, 0x419a30, 0x1); nv_wr32(priv, 0x419a30, 0x1);
nv_wr32(priv, 0x419ac4, 0x37f440); nv_wr32(priv, 0x419ac4, 0x37f440);
nv_wr32(priv, 0x419c00, 0xa); switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x419c00, 0x1a);
break;
default:
nv_wr32(priv, 0x419c00, 0xa);
break;
}
nv_wr32(priv, 0x419c04, 0x80000006); nv_wr32(priv, 0x419c04, 0x80000006);
nv_wr32(priv, 0x419c08, 0x2); nv_wr32(priv, 0x419c08, 0x2);
nv_wr32(priv, 0x419c20, 0x0); nv_wr32(priv, 0x419c20, 0x0);
nv_wr32(priv, 0x419c24, 0x84210); nv_wr32(priv, 0x419c24, 0x84210);
nv_wr32(priv, 0x419c28, 0x3efbefbe); nv_wr32(priv, 0x419c28, 0x3efbefbe);
nv_wr32(priv, 0x419ce8, 0x0); nv_wr32(priv, 0x419ce8, 0x0);
nv_wr32(priv, 0x419cf4, 0x3203); switch (nv_device(priv)->chipset) {
nv_wr32(priv, 0x419e04, 0x0); case 0xf0:
nv_wr32(priv, 0x419e08, 0x0); nv_wr32(priv, 0x419cf4, 0x203);
nv_wr32(priv, 0x419e0c, 0x0); nv_wr32(priv, 0x419e04, 0x0);
nv_wr32(priv, 0x419e10, 0x402); nv_wr32(priv, 0x419e08, 0x1d);
nv_wr32(priv, 0x419e0c, 0x0);
nv_wr32(priv, 0x419e10, 0x1c02);
break;
default:
nv_wr32(priv, 0x419cf4, 0x3203);
nv_wr32(priv, 0x419e04, 0x0);
nv_wr32(priv, 0x419e08, 0x0);
nv_wr32(priv, 0x419e0c, 0x0);
nv_wr32(priv, 0x419e10, 0x402);
break;
}
nv_wr32(priv, 0x419e44, 0x13eff2); nv_wr32(priv, 0x419e44, 0x13eff2);
nv_wr32(priv, 0x419e48, 0x0); nv_wr32(priv, 0x419e48, 0x0);
nv_wr32(priv, 0x419e4c, 0x7f); nv_wr32(priv, 0x419e4c, 0x7f);
nv_wr32(priv, 0x419e50, 0x0); nv_wr32(priv, 0x419e50, 0x0);
nv_wr32(priv, 0x419e54, 0x0); nv_wr32(priv, 0x419e54, 0x0);
nv_wr32(priv, 0x419e58, 0x0); switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x419e58, 0x1);
break;
default:
nv_wr32(priv, 0x419e58, 0x0);
break;
}
nv_wr32(priv, 0x419e5c, 0x0); nv_wr32(priv, 0x419e5c, 0x0);
nv_wr32(priv, 0x419e60, 0x0); nv_wr32(priv, 0x419e60, 0x0);
nv_wr32(priv, 0x419e64, 0x0); nv_wr32(priv, 0x419e64, 0x0);
nv_wr32(priv, 0x419e68, 0x0); switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x419e68, 0x2);
break;
default:
nv_wr32(priv, 0x419e68, 0x0);
break;
}
nv_wr32(priv, 0x419e6c, 0x0); nv_wr32(priv, 0x419e6c, 0x0);
nv_wr32(priv, 0x419e70, 0x0); nv_wr32(priv, 0x419e70, 0x0);
nv_wr32(priv, 0x419e74, 0x0); nv_wr32(priv, 0x419e74, 0x0);
...@@ -2553,37 +2719,49 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv) ...@@ -2553,37 +2719,49 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv)
case 0xe7: case 0xe7:
case 0xe6: case 0xe6:
nv_wr32(priv, 0x419eac, 0x1f8f); nv_wr32(priv, 0x419eac, 0x1f8f);
nv_wr32(priv, 0x419eb0, 0xd3f);
break;
case 0xf0:
nv_wr32(priv, 0x419eac, 0x1fcf);
nv_wr32(priv, 0x419eb0, 0xdb00da0);
nv_wr32(priv, 0x419eb8, 0x0);
break; break;
default: default:
nv_wr32(priv, 0x419eac, 0x1fcf); nv_wr32(priv, 0x419eac, 0x1fcf);
nv_wr32(priv, 0x419eb0, 0xd3f);
break; break;
} }
nv_wr32(priv, 0x419eb0, 0xd3f);
nv_wr32(priv, 0x419ec8, 0x1304f); nv_wr32(priv, 0x419ec8, 0x1304f);
nv_wr32(priv, 0x419f30, 0x0); nv_wr32(priv, 0x419f30, 0x0);
nv_wr32(priv, 0x419f34, 0x0); nv_wr32(priv, 0x419f34, 0x0);
nv_wr32(priv, 0x419f38, 0x0); nv_wr32(priv, 0x419f38, 0x0);
nv_wr32(priv, 0x419f3c, 0x0); nv_wr32(priv, 0x419f3c, 0x0);
nv_wr32(priv, 0x419f40, 0x0);
nv_wr32(priv, 0x419f44, 0x0);
nv_wr32(priv, 0x419f48, 0x0);
nv_wr32(priv, 0x419f4c, 0x0);
nv_wr32(priv, 0x419f58, 0x0);
switch (nv_device(priv)->chipset) { switch (nv_device(priv)->chipset) {
case 0xe7: case 0xf0:
case 0xe6: nv_wr32(priv, 0x419f40, 0x18);
nv_wr32(priv, 0x419f70, 0x0);
break; break;
default: default:
nv_wr32(priv, 0x419f40, 0x0);
break; break;
} }
nv_wr32(priv, 0x419f78, 0xb); nv_wr32(priv, 0x419f44, 0x0);
nv_wr32(priv, 0x419f48, 0x0);
nv_wr32(priv, 0x419f4c, 0x0);
nv_wr32(priv, 0x419f58, 0x0);
switch (nv_device(priv)->chipset) { switch (nv_device(priv)->chipset) {
case 0xe7: case 0xe7:
case 0xe6: case 0xe6:
nv_wr32(priv, 0x419f70, 0x0);
nv_wr32(priv, 0x419f78, 0xb);
nv_wr32(priv, 0x419f7c, 0x27a); nv_wr32(priv, 0x419f7c, 0x27a);
break; break;
case 0xf0:
nv_wr32(priv, 0x419f70, 0x7300);
nv_wr32(priv, 0x419f78, 0xeb);
nv_wr32(priv, 0x419f7c, 0x404);
break;
default: default:
nv_wr32(priv, 0x419f78, 0xb);
break; break;
} }
} }
...@@ -2592,9 +2770,23 @@ static void ...@@ -2592,9 +2770,23 @@ static void
nve0_graph_generate_tpcunk(struct nvc0_graph_priv *priv) nve0_graph_generate_tpcunk(struct nvc0_graph_priv *priv)
{ {
nv_wr32(priv, 0x41be24, 0x6); nv_wr32(priv, 0x41be24, 0x6);
nv_wr32(priv, 0x41bec0, 0x12180000); switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x41bec0, 0x10000000);
break;
default:
nv_wr32(priv, 0x41bec0, 0x12180000);
break;
}
nv_wr32(priv, 0x41bec4, 0x37f7f); nv_wr32(priv, 0x41bec4, 0x37f7f);
nv_wr32(priv, 0x41bee4, 0x6480430); switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x41bee4, 0x0);
break;
default:
nv_wr32(priv, 0x41bee4, 0x6480430);
break;
}
nv_wr32(priv, 0x41bf00, 0xa418820); nv_wr32(priv, 0x41bf00, 0xa418820);
nv_wr32(priv, 0x41bf04, 0x62080e6); nv_wr32(priv, 0x41bf04, 0x62080e6);
nv_wr32(priv, 0x41bf08, 0x20398a4); nv_wr32(priv, 0x41bf08, 0x20398a4);
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
View file @ cb1e06e0
...@@ -62,6 +62,11 @@ chipsets: ...@@ -62,6 +62,11 @@ chipsets:
.b16 #nve4_gpc_mmio_tail .b16 #nve4_gpc_mmio_tail
.b16 #nve6_tpc_mmio_head .b16 #nve6_tpc_mmio_head
.b16 #nve6_tpc_mmio_tail .b16 #nve6_tpc_mmio_tail
.b8 0xf0 0 0 0
.b16 #nvf0_gpc_mmio_head
.b16 #nvf0_gpc_mmio_tail
.b16 #nvf0_tpc_mmio_head
.b16 #nvf0_tpc_mmio_tail
.b8 0 0 0 0 .b8 0 0 0 0
// GPC mmio lists // GPC mmio lists
...@@ -101,6 +106,37 @@ mmctx_data(0x0031d0, 1) ...@@ -101,6 +106,37 @@ mmctx_data(0x0031d0, 1)
mmctx_data(0x0031e0, 2) mmctx_data(0x0031e0, 2)
nve4_gpc_mmio_tail: nve4_gpc_mmio_tail:
nvf0_gpc_mmio_head:
mmctx_data(0x000380, 1)
mmctx_data(0x000400, 2)
mmctx_data(0x00040c, 3)
mmctx_data(0x000450, 9)
mmctx_data(0x000600, 1)
mmctx_data(0x000684, 1)
mmctx_data(0x000700, 5)
mmctx_data(0x000800, 1)
mmctx_data(0x000808, 3)
mmctx_data(0x000828, 1)
mmctx_data(0x000830, 1)
mmctx_data(0x0008d8, 1)
mmctx_data(0x0008e0, 1)
mmctx_data(0x0008e8, 6)
mmctx_data(0x00091c, 1)
mmctx_data(0x000924, 3)
mmctx_data(0x000b00, 1)
mmctx_data(0x000b08, 6)
mmctx_data(0x000bb8, 1)
mmctx_data(0x000c08, 1)
mmctx_data(0x000c10, 8)
mmctx_data(0x000c40, 1)
mmctx_data(0x000c6c, 1)
mmctx_data(0x000c80, 1)
mmctx_data(0x000c8c, 1)
mmctx_data(0x000d24, 1)
mmctx_data(0x001000, 3)
mmctx_data(0x001014, 1)
nvf0_gpc_mmio_tail:
// TPC mmio lists // TPC mmio lists
nve4_tpc_mmio_head: nve4_tpc_mmio_head:
mmctx_data(0x000048, 1) mmctx_data(0x000048, 1)
...@@ -145,6 +181,29 @@ mmctx_data(0x000770, 1) ...@@ -145,6 +181,29 @@ mmctx_data(0x000770, 1)
mmctx_data(0x000778, 2) mmctx_data(0x000778, 2)
nve6_tpc_mmio_tail: nve6_tpc_mmio_tail:
nvf0_tpc_mmio_head:
mmctx_data(0x000048, 1)
mmctx_data(0x000064, 1)
mmctx_data(0x000088, 1)
mmctx_data(0x000200, 6)
mmctx_data(0x00021c, 2)
mmctx_data(0x000230, 1)
mmctx_data(0x0002c4, 1)
mmctx_data(0x000400, 3)
mmctx_data(0x000420, 3)
mmctx_data(0x0004e8, 1)
mmctx_data(0x0004f4, 1)
mmctx_data(0x000604, 4)
mmctx_data(0x000644, 22)
mmctx_data(0x0006ac, 2)
mmctx_data(0x0006b8, 1)
mmctx_data(0x0006c8, 1)
mmctx_data(0x000730, 8)
mmctx_data(0x000758, 1)
mmctx_data(0x000770, 1)
mmctx_data(0x000778, 2)
nvf0_tpc_mmio_tail:
.section #nve0_grgpc_code .section #nve0_grgpc_code
bra #init bra #init
define(`include_code') define(`include_code')
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
View file @ cb1e06e0
...@@ -34,16 +34,19 @@ uint32_t nve0_grgpc_data[] = { ...@@ -34,16 +34,19 @@ uint32_t nve0_grgpc_data[] = {
0x00000000, 0x00000000,
/* 0x0064: chipsets */ /* 0x0064: chipsets */
0x000000e4, 0x000000e4,
0x0110008c, 0x011c0098,
0x01580110, 0x01d4018c,
0x000000e7, 0x000000e7,
0x0110008c, 0x011c0098,
0x01a40158, 0x022001d4,
0x000000e6, 0x000000e6,
0x0110008c, 0x011c0098,
0x01a40158, 0x022001d4,
0x000000f0,
0x018c011c,
0x02700220,
0x00000000, 0x00000000,
/* 0x008c: nve4_gpc_mmio_head */ /* 0x0098: nve4_gpc_mmio_head */
0x00000380, 0x00000380,
0x04000400, 0x04000400,
0x0800040c, 0x0800040c,
...@@ -77,8 +80,38 @@ uint32_t nve0_grgpc_data[] = { ...@@ -77,8 +80,38 @@ uint32_t nve0_grgpc_data[] = {
0x14003100, 0x14003100,
0x000031d0, 0x000031d0,
0x040031e0, 0x040031e0,
/* 0x0110: nve4_gpc_mmio_tail */ /* 0x011c: nve4_gpc_mmio_tail */
/* 0x0110: nve4_tpc_mmio_head */ /* 0x011c: nvf0_gpc_mmio_head */
0x00000380,
0x04000400,
0x0800040c,
0x20000450,
0x00000600,
0x00000684,
0x10000700,
0x00000800,
0x08000808,
0x00000828,
0x00000830,
0x000008d8,
0x000008e0,
0x140008e8,
0x0000091c,
0x08000924,
0x00000b00,
0x14000b08,
0x00000bb8,
0x00000c08,
0x1c000c10,
0x00000c40,
0x00000c6c,
0x00000c80,
0x00000c8c,
0x00000d24,
0x08001000,
0x00001014,
/* 0x018c: nvf0_gpc_mmio_tail */
/* 0x018c: nve4_tpc_mmio_head */
0x00000048, 0x00000048,
0x00000064, 0x00000064,
0x00000088, 0x00000088,
...@@ -97,8 +130,29 @@ uint32_t nve0_grgpc_data[] = { ...@@ -97,8 +130,29 @@ uint32_t nve0_grgpc_data[] = {
0x1c000730, 0x1c000730,
0x00000758, 0x00000758,
0x00000778, 0x00000778,
/* 0x0158: nve4_tpc_mmio_tail */ /* 0x01d4: nve4_tpc_mmio_tail */
/* 0x0158: nve6_tpc_mmio_head */ /* 0x01d4: nve6_tpc_mmio_head */
0x00000048,
0x00000064,
0x00000088,
0x14000200,
0x0400021c,
0x00000230,
0x000002c4,
0x08000400,
0x08000420,
0x000004e8,
0x000004f4,
0x0c000604,
0x54000644,
0x040006ac,
0x000006c8,
0x1c000730,
0x00000758,
0x00000770,
0x04000778,
/* 0x0220: nve6_tpc_mmio_tail */
/* 0x0220: nvf0_tpc_mmio_head */
0x00000048, 0x00000048,
0x00000064, 0x00000064,
0x00000088, 0x00000088,
...@@ -113,6 +167,7 @@ uint32_t nve0_grgpc_data[] = { ...@@ -113,6 +167,7 @@ uint32_t nve0_grgpc_data[] = {
0x0c000604, 0x0c000604,
0x54000644, 0x54000644,
0x040006ac, 0x040006ac,
0x000006b8,
0x000006c8, 0x000006c8,
0x1c000730, 0x1c000730,
0x00000758, 0x00000758,
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
View file @ cb1e06e0
...@@ -37,6 +37,15 @@ hub_mmio_list_tail: .b32 0 ...@@ -37,6 +37,15 @@ hub_mmio_list_tail: .b32 0
ctx_current: .b32 0 ctx_current: .b32 0
.align 256
chan_data:
chan_mmio_count: .b32 0
chan_mmio_address: .b32 0
.align 256
xfer_data: .b32 0
.align 256
chipsets: chipsets:
.b8 0xe4 0 0 0 .b8 0xe4 0 0 0
.b16 #nve4_hub_mmio_head .b16 #nve4_hub_mmio_head
...@@ -47,6 +56,9 @@ chipsets: ...@@ -47,6 +56,9 @@ chipsets:
.b8 0xe6 0 0 0 .b8 0xe6 0 0 0
.b16 #nve4_hub_mmio_head .b16 #nve4_hub_mmio_head
.b16 #nve4_hub_mmio_tail .b16 #nve4_hub_mmio_tail
.b8 0xf0 0 0 0
.b16 #nvf0_hub_mmio_head
.b16 #nvf0_hub_mmio_tail
.b8 0 0 0 0 .b8 0 0 0 0
nve4_hub_mmio_head: nve4_hub_mmio_head:
...@@ -103,13 +115,61 @@ mmctx_data(0x408900, 3) ...@@ -103,13 +115,61 @@ mmctx_data(0x408900, 3)
mmctx_data(0x408980, 1) mmctx_data(0x408980, 1)
nve4_hub_mmio_tail: nve4_hub_mmio_tail:
.align 256 nvf0_hub_mmio_head:
chan_data: mmctx_data(0x17e91c, 2)
chan_mmio_count: .b32 0 mmctx_data(0x400204, 2)
chan_mmio_address: .b32 0 mmctx_data(0x404004, 17)
mmctx_data(0x4040a8, 9)
.align 256 mmctx_data(0x4040d0, 7)
xfer_data: .b32 0 mmctx_data(0x4040f8, 1)
mmctx_data(0x404100, 10)
mmctx_data(0x404130, 3)
mmctx_data(0x404150, 3)
mmctx_data(0x404164, 1)
mmctx_data(0x40417c, 2)
mmctx_data(0x4041a0, 4)
mmctx_data(0x404200, 4)
mmctx_data(0x404404, 12)
mmctx_data(0x404438, 1)
mmctx_data(0x404460, 4)
mmctx_data(0x404480, 1)
mmctx_data(0x404498, 1)
mmctx_data(0x404604, 4)
mmctx_data(0x404618, 4)
mmctx_data(0x40462c, 2)
mmctx_data(0x404640, 1)
mmctx_data(0x404654, 1)
mmctx_data(0x404660, 1)
mmctx_data(0x404678, 19)
mmctx_data(0x4046c8, 3)
mmctx_data(0x404700, 3)
mmctx_data(0x404718, 10)
mmctx_data(0x404744, 2)
mmctx_data(0x404754, 1)
mmctx_data(0x405800, 1)
mmctx_data(0x405830, 3)
mmctx_data(0x405854, 1)
mmctx_data(0x405870, 4)
mmctx_data(0x405a00, 2)
mmctx_data(0x405a18, 1)
mmctx_data(0x405b00, 1)
mmctx_data(0x405b10, 1)
mmctx_data(0x405b20, 1)
mmctx_data(0x406020, 1)
mmctx_data(0x406028, 4)
mmctx_data(0x4064a8, 5)
mmctx_data(0x4064c0, 12)
mmctx_data(0x4064fc, 1)
mmctx_data(0x407804, 1)
mmctx_data(0x40780c, 6)
mmctx_data(0x4078bc, 1)
mmctx_data(0x408000, 7)
mmctx_data(0x408064, 1)
mmctx_data(0x408800, 3)
mmctx_data(0x408840, 1)
mmctx_data(0x408900, 3)
mmctx_data(0x408980, 1)
nvf0_hub_mmio_tail:
.section #nve0_grhub_code .section #nve0_grhub_code
bra #init bra #init
......
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
View file @ cb1e06e0
...@@ -28,67 +28,7 @@ uint32_t nve0_grhub_data[] = { ...@@ -28,67 +28,7 @@ uint32_t nve0_grhub_data[] = {
0x00000000, 0x00000000,
/* 0x0058: ctx_current */ /* 0x0058: ctx_current */
0x00000000, 0x00000000,
/* 0x005c: chipsets */
0x000000e4,
0x01440078,
0x000000e7,
0x01440078,
0x000000e6,
0x01440078,
0x00000000, 0x00000000,
/* 0x0078: nve4_hub_mmio_head */
0x0417e91c,
0x04400204,
0x18404010,
0x204040a8,
0x184040d0,
0x004040f8,
0x08404130,
0x08404150,
0x00404164,
0x0c4041a0,
0x0c404200,
0x34404404,
0x0c404460,
0x00404480,
0x00404498,
0x0c404604,
0x0c404618,
0x0440462c,
0x00404640,
0x00404654,
0x00404660,
0x48404678,
0x084046c8,
0x08404700,
0x24404718,
0x04404744,
0x00404754,
0x00405800,
0x08405830,
0x00405854,
0x0c405870,
0x04405a00,
0x00405a18,
0x00405b00,
0x00405b10,
0x00406020,
0x0c406028,
0x044064a8,
0x044064b4,
0x2c4064c0,
0x004064fc,
0x00407040,
0x00407804,
0x1440780c,
0x004078bc,
0x18408000,
0x00408064,
0x08408800,
0x00408840,
0x08408900,
0x00408980,
/* 0x0144: nve4_hub_mmio_tail */
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
...@@ -129,6 +69,26 @@ uint32_t nve0_grhub_data[] = { ...@@ -129,6 +69,26 @@ uint32_t nve0_grhub_data[] = {
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
/* 0x0100: chan_data */
/* 0x0100: chan_mmio_count */
0x00000000,
/* 0x0104: chan_mmio_address */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
...@@ -136,10 +96,7 @@ uint32_t nve0_grhub_data[] = { ...@@ -136,10 +96,7 @@ uint32_t nve0_grhub_data[] = {
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
/* 0x0200: chan_data */
/* 0x0200: chan_mmio_count */
0x00000000, 0x00000000,
/* 0x0204: chan_mmio_address */
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
...@@ -179,6 +136,7 @@ uint32_t nve0_grhub_data[] = { ...@@ -179,6 +136,7 @@ uint32_t nve0_grhub_data[] = {
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
/* 0x0200: xfer_data */
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
...@@ -203,8 +161,163 @@ uint32_t nve0_grhub_data[] = { ...@@ -203,8 +161,163 @@ uint32_t nve0_grhub_data[] = {
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
/* 0x0300: xfer_data */
0x00000000, 0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 0x0300: chipsets */
0x000000e4,
0x03f00324,
0x000000e7,
0x03f00324,
0x000000e6,
0x03f00324,
0x000000f0,
0x04c403f0,
0x00000000,
/* 0x0324: nve4_hub_mmio_head */
0x0417e91c,
0x04400204,
0x18404010,
0x204040a8,
0x184040d0,
0x004040f8,
0x08404130,
0x08404150,
0x00404164,
0x0c4041a0,
0x0c404200,
0x34404404,
0x0c404460,
0x00404480,
0x00404498,
0x0c404604,
0x0c404618,
0x0440462c,
0x00404640,
0x00404654,
0x00404660,
0x48404678,
0x084046c8,
0x08404700,
0x24404718,
0x04404744,
0x00404754,
0x00405800,
0x08405830,
0x00405854,
0x0c405870,
0x04405a00,
0x00405a18,
0x00405b00,
0x00405b10,
0x00406020,
0x0c406028,
0x044064a8,
0x044064b4,
0x2c4064c0,
0x004064fc,
0x00407040,
0x00407804,
0x1440780c,
0x004078bc,
0x18408000,
0x00408064,
0x08408800,
0x00408840,
0x08408900,
0x00408980,
/* 0x03f0: nve4_hub_mmio_tail */
/* 0x03f0: nvf0_hub_mmio_head */
0x0417e91c,
0x04400204,
0x40404004,
0x204040a8,
0x184040d0,
0x004040f8,
0x24404100,
0x08404130,
0x08404150,
0x00404164,
0x0440417c,
0x0c4041a0,
0x0c404200,
0x2c404404,
0x00404438,
0x0c404460,
0x00404480,
0x00404498,
0x0c404604,
0x0c404618,
0x0440462c,
0x00404640,
0x00404654,
0x00404660,
0x48404678,
0x084046c8,
0x08404700,
0x24404718,
0x04404744,
0x00404754,
0x00405800,
0x08405830,
0x00405854,
0x0c405870,
0x04405a00,
0x00405a18,
0x00405b00,
0x00405b10,
0x00405b20,
0x00406020,
0x0c406028,
0x104064a8,
0x2c4064c0,
0x004064fc,
0x00407804,
0x1440780c,
0x004078bc,
0x18408000,
0x00408064,
0x08408800,
0x00408840,
0x08408900,
0x00408980,
}; };
uint32_t nve0_grhub_code[] = { uint32_t nve0_grhub_code[] = {
...@@ -440,7 +553,7 @@ uint32_t nve0_grhub_code[] = { ...@@ -440,7 +553,7 @@ uint32_t nve0_grhub_code[] = {
0x0017f100, 0x0017f100,
0x0227f012, 0x0227f012,
0xf10012d0, 0xf10012d0,
0xfe05b917, 0xfe05ba17,
0x17f10010, 0x17f10010,
0x10d00400, 0x10d00400,
0x0437f1c0, 0x0437f1c0,
...@@ -474,385 +587,385 @@ uint32_t nve0_grhub_code[] = { ...@@ -474,385 +587,385 @@ uint32_t nve0_grhub_code[] = {
0x4021d000, 0x4021d000,
0x080027f1, 0x080027f1,
0xcf0624b6, 0xcf0624b6,
0xf7f00022, 0xf7f10022,
/* 0x03a9: init_find_chipset */ /* 0x03aa: init_find_chipset */
0x08f0b654, 0xf0b602f8,
0xb800f398, 0x00f39808,
0x0bf40432, 0xf40432b8,
0x0034b00b, 0x34b00b0b,
0xf8f11bf4, 0xf11bf400,
/* 0x03bd: init_context */ /* 0x03be: init_context */
0x0017f100, 0x17f100f8,
0x02fe5801, 0xfe580100,
0xf003ff58, 0x03ff5802,
0x0e8000e3, 0x8000e3f0,
0x150f8014, 0x0f80140e,
0x013d21f5, 0x3d21f515,
0x070037f1, 0x0037f101,
0x950634b6, 0x0634b607,
0x34d00814, 0xd0081495,
0x4034d000, 0x34d00034,
0x130030b7, 0x0030b740,
0xb6001fbb, 0x001fbb13,
0x3fd002f5, 0xd002f5b6,
0x0815b600, 0x15b6003f,
0xb60110b6, 0x0110b608,
0x1fb90814, 0xb90814b6,
0x6321f502, 0x21f5021f,
0x001fbb02, 0x1fbb0263,
0xf1000398, 0x00039800,
0xf0200047, 0x200047f1,
/* 0x040e: init_gpc */ /* 0x040f: init_gpc */
0x4ea05043, 0xa05043f0,
0x1fb90804, 0xb908044e,
0x8d21f402, 0x21f4021f,
0x08004ea0, 0x004ea08d,
0xf4022fb9, 0x022fb908,
0x4ea08d21,
0xf4bd010c,
0xa08d21f4, 0xa08d21f4,
0xf401044e, 0xbd010c4e,
0x4ea08d21, 0x8d21f4f4,
0xf7f00100, 0x01044ea0,
0x8d21f402, 0xa08d21f4,
0x08004ea0, 0xf001004e,
/* 0x0440: init_gpc_wait */ 0x21f402f7,
0xc86821f4, 0x004ea08d,
0x0bf41fff, /* 0x0441: init_gpc_wait */
0x044ea0fa,
0x6821f408, 0x6821f408,
0xb7001fbb, 0xf41fffc8,
0xb6800040, 0x4ea0fa0b,
0x1bf40132, 0x21f40804,
0x0027f1b4, 0x001fbb68,
0x0624b608, 0x800040b7,
0xb74021d0, 0xf40132b6,
0xbd080020, 0x27f1b41b,
0x1f19f014, 0x24b60800,
/* 0x0473: main */ 0x4021d006,
0xf40021d0, 0x080020b7,
0x28f40031, 0x19f014bd,
0x08d7f000, 0x0021d01f,
0xf43921f4, /* 0x0474: main */
0xe4b1f401, 0xf40031f4,
0x1bf54001, 0xd7f00028,
0x87f100d1, 0x3921f408,
0x84b6083c, 0xb1f401f4,
0xf094bd06, 0xf54001e4,
0x89d00499, 0xf100d11b,
0x0017f100,
0x0614b60b,
0xcf4012cf,
0x13c80011,
0x7e0bf41f,
0xf41f23c8,
0x20f95a0b,
0xf10212b9,
0xb6083c87, 0xb6083c87,
0x94bd0684, 0x94bd0684,
0xd00799f0, 0xd00499f0,
0x32f40089, 0x17f10089,
0x0231f401, 0x14b60b00,
0x07fb21f5, 0x4012cf06,
0x085c87f1, 0xc80011cf,
0x0bf41f13,
0x1f23c87e,
0xf95a0bf4,
0x0212b920,
0x083c87f1,
0xbd0684b6, 0xbd0684b6,
0x0799f094, 0x0799f094,
0xfc0089d0, 0xf40089d0,
0x3c87f120, 0x31f40132,
0xfc21f502,
0x5c87f107,
0x0684b608, 0x0684b608,
0x99f094bd, 0x99f094bd,
0x0089d006, 0x0089d007,
0xf50131f4, 0x87f120fc,
0xf107fb21, 0x84b6083c,
0xb6085c87, 0xf094bd06,
0x94bd0684, 0x89d00699,
0xd00699f0, 0x0131f400,
0x0ef40089, 0x07fc21f5,
/* 0x0509: chsw_prev_no_next */
0xb920f931,
0x32f40212,
0x0232f401,
0x07fb21f5,
0x17f120fc,
0x14b60b00,
0x0012d006,
/* 0x0527: chsw_no_prev */
0xc8130ef4,
0x0bf41f23,
0x0131f40d,
0xf50232f4,
/* 0x0537: chsw_done */
0xf107fb21,
0xb60b0c17,
0x27f00614,
0x0012d001,
0x085c87f1, 0x085c87f1,
0xbd0684b6, 0xbd0684b6,
0x0499f094, 0x0699f094,
0xf50089d0, 0xf40089d0,
/* 0x0557: main_not_ctx_switch */ /* 0x050a: chsw_prev_no_next */
0xb0ff200e, 0x20f9310e,
0x1bf401e4, 0xf40212b9,
0x02f2b90d, 0x32f40132,
0x078f21f5, 0xfc21f502,
/* 0x0567: main_not_ctx_chan */ 0xf120fc07,
0xb0420ef4, 0xb60b0017,
0x1bf402e4, 0x12d00614,
0x3c87f12e, 0x130ef400,
/* 0x0528: chsw_no_prev */
0xf41f23c8,
0x31f40d0b,
0x0232f401,
0x07fc21f5,
/* 0x0538: chsw_done */
0x0b0c17f1,
0xf00614b6,
0x12d00127,
0x5c87f100,
0x0684b608, 0x0684b608,
0x99f094bd, 0x99f094bd,
0x0089d007, 0x0089d004,
0xf40132f4, 0xff200ef5,
0x21f50232, /* 0x0558: main_not_ctx_switch */
0x87f107fb, 0xf401e4b0,
0x84b6085c, 0xf2b90d1b,
0x9021f502,
0x420ef407,
/* 0x0568: main_not_ctx_chan */
0xf402e4b0,
0x87f12e1b,
0x84b6083c,
0xf094bd06, 0xf094bd06,
0x89d00799, 0x89d00799,
0x110ef400, 0x0132f400,
/* 0x0598: main_not_ctx_save */ 0xf50232f4,
0xf010ef94, 0xf107fc21,
0x21f501f5, 0xb6085c87,
0x0ef502ec, 0x94bd0684,
/* 0x05a6: main_done */ 0xd00799f0,
0x17f1fed1, 0x0ef40089,
0x14b60820, /* 0x0599: main_not_ctx_save */
0xf024bd06, 0x10ef9411,
0x12d01f29, 0xf501f5f0,
0xbe0ef500, 0xf502ec21,
/* 0x05b9: ih */ /* 0x05a7: main_done */
0xfe80f9fe, 0xf1fed10e,
0x80f90188, 0xb6082017,
0xa0f990f9, 0x24bd0614,
0xd0f9b0f9, 0xd01f29f0,
0xf0f9e0f9, 0x0ef50012,
0xc4800acf, /* 0x05ba: ih */
0x0bf404ab, 0x80f9febe,
0x00b7f11d, 0xf90188fe,
0x08d7f019, 0xf990f980,
0xcf40becf, 0xf9b0f9a0,
0x21f400bf, 0xf9e0f9d0,
0x00b0b704, 0x800acff0,
0x01e7f004, 0xf404abc4,
/* 0x05ef: ih_no_fifo */ 0xb7f11d0b,
0xe400bed0, 0xd7f01900,
0xf40100ab, 0x40becf08,
0xd7f00d0b, 0xf400bfcf,
0x01e7f108, 0xb0b70421,
0x0421f440, 0xe7f00400,
/* 0x0600: ih_no_ctxsw */ 0x00bed001,
0x0104b7f1, /* 0x05f0: ih_no_fifo */
0xabffb0bd, 0x0100abe4,
0x0d0bf4b4, 0xf00d0bf4,
0x0c1ca7f1, 0xe7f108d7,
0xd006a4b6, 0x21f44001,
/* 0x0616: ih_no_other */ /* 0x0601: ih_no_ctxsw */
0x0ad000ab, 0x04b7f104,
0xfcf0fc40, 0xffb0bd01,
0xfcd0fce0, 0x0bf4b4ab,
0xfca0fcb0, 0x1ca7f10d,
0xfe80fc90, 0x06a4b60c,
0x80fc0088, /* 0x0617: ih_no_other */
0xf80032f4, 0xd000abd0,
/* 0x0631: ctx_4170s */ 0xf0fc400a,
0x70e7f101, 0xd0fce0fc,
0xa0fcb0fc,
0x80fc90fc,
0xfc0088fe,
0x0032f480,
/* 0x0632: ctx_4170s */
0xe7f101f8,
0xe3f04170,
0x10f5f040,
0xf88d21f4,
/* 0x0641: ctx_4170w */
0x70e7f100,
0x40e3f041, 0x40e3f041,
0xf410f5f0, 0xf06821f4,
0x00f88d21, 0x1bf410f4,
/* 0x0640: ctx_4170w */ /* 0x0653: ctx_redswitch */
0x4170e7f1, 0xf100f8f3,
0xf440e3f0, 0xb60614e7,
0xf4f06821, 0xf7f106e4,
0xf31bf410, 0xefd00270,
/* 0x0652: ctx_redswitch */ 0x08f7f000,
0xe7f100f8, /* 0x0664: ctx_redswitch_delay */
0xe4b60614, 0xf401f2b6,
0x70f7f106, 0xf7f1fd1b,
0x00efd002, 0xefd00770,
/* 0x0663: ctx_redswitch_delay */ /* 0x0673: ctx_86c */
0xb608f7f0, 0xf100f800,
0x1bf401f2, 0xb6086ce7,
0x70f7f1fd, 0xefd006e4,
0x00efd007, 0x14e7f100,
/* 0x0672: ctx_86c */ 0x40e3f08a,
0xe7f100f8, 0xf18d21f4,
0xe4b6086c, 0xf0a86ce7,
0x00efd006, 0x21f441e3,
0x8a14e7f1, /* 0x0693: ctx_load */
0xf440e3f0, 0xf100f88d,
0xe7f18d21,
0xe3f0a86c,
0x8d21f441,
/* 0x0692: ctx_load */
0x87f100f8,
0x84b6083c,
0xf094bd06,
0x89d00599,
0x0ca7f000,
0xf1c921f4,
0xb60a2417,
0x10d00614,
0x0037f100,
0x0634b60b,
0xf14032d0,
0xb60a0c17,
0x47f00614,
0x0012d007,
/* 0x06cb: ctx_chan_wait_0 */
0xcf4014d0,
0x44f04014,
0xfa1bf41f,
0xfe0032d0,
0x2af0000b,
0x0424b61f,
0xf10220b6,
0xb6083c87, 0xb6083c87,
0x94bd0684, 0x94bd0684,
0xd00899f0, 0xd00599f0,
0x17f10089, 0xa7f00089,
0x14b60a04, 0xc921f40c,
0x0012d006, 0x0a2417f1,
0x0a2017f1, 0xd00614b6,
0x37f10010,
0x34b60b00,
0x4032d006,
0x0a0c17f1,
0xf00614b6, 0xf00614b6,
0x23f10227, 0x12d00747,
0x12d08000, 0x4014d000,
0x1017f000, /* 0x06cc: ctx_chan_wait_0 */
0x030027f1, 0xf04014cf,
0xfa0223f0, 0x1bf41f44,
0x03f80512, 0x0032d0fa,
0x085c87f1, 0xf0000bfe,
0x24b61f2a,
0x0220b604,
0x083c87f1,
0xbd0684b6, 0xbd0684b6,
0x0899f094, 0x0899f094,
0x980089d0, 0xf10089d0,
0x14b6c101, 0xb60a0417,
0xc0029818, 0x12d00614,
0xfd0825b6, 0x2017f100,
0x01800512, 0x0614b60a,
0x3c87f116, 0xf10227f0,
0xd0800023,
0x17f00012,
0x0027f110,
0x0223f002,
0xf80512fa,
0x5c87f103,
0x0684b608, 0x0684b608,
0x99f094bd, 0x99f094bd,
0x0089d009, 0x0089d008,
0x0a0427f1, 0xb6810198,
0xd00624b6, 0x02981814,
0x27f00021, 0x0825b680,
0x2017f101, 0x800512fd,
0x0614b60a, 0x87f11601,
0xf10012d0, 0x84b6083c,
0xf0020017, 0xf094bd06,
0x01fa0613, 0x89d00999,
0xf103f805, 0x0427f100,
0x0624b60a,
0xf00021d0,
0x17f10127,
0x14b60a20,
0x0012d006,
0x010017f1,
0xfa0613f0,
0x03f80501,
0x085c87f1,
0xbd0684b6,
0x0999f094,
0xf10089d0,
0xb6085c87, 0xb6085c87,
0x94bd0684, 0x94bd0684,
0xd00999f0, 0xd00599f0,
0x87f10089, 0x00f80089,
0x84b6085c, /* 0x0790: ctx_chan */
0xf094bd06, 0x069321f5,
0x89d00599, 0xf40ca7f0,
/* 0x078f: ctx_chan */ 0x17f1c921,
0xf500f800, 0x14b60a10,
0xf0069221, 0x0527f006,
0x21f40ca7, /* 0x07a7: ctx_chan_wait */
0x1017f1c9, 0xcf0012d0,
0x0614b60a, 0x22fd0012,
0xd00527f0, 0xfa1bf405,
/* 0x07a6: ctx_chan_wait */ /* 0x07b2: ctx_mmio_exec */
0x12cf0012, 0x039800f8,
0x0522fd00, 0x0427f141,
0xf8fa1bf4, 0x0624b60a,
/* 0x07b1: ctx_mmio_exec */ 0xbd0023d0,
0x81039800, /* 0x07c1: ctx_mmio_loop */
0x0a0427f1, 0xff34c434,
0xd00624b6, 0xf10f1bf4,
0x34bd0023, 0xf0020057,
/* 0x07c0: ctx_mmio_loop */ 0x35fa0653,
0xf4ff34c4, /* 0x07d3: ctx_mmio_pull */
0x57f10f1b, 0x9803f805,
0x53f00300, 0x4f98804e,
0x0535fa06, 0x8d21f481,
/* 0x07d2: ctx_mmio_pull */ 0xb60830b6,
0x4e9803f8, 0x1bf40112,
0xc14f98c0, /* 0x07e5: ctx_mmio_done */
0xb68d21f4, 0x160398df,
0x12b60830, 0x800023d0,
0xdf1bf401, 0x17f14000,
/* 0x07e4: ctx_mmio_done */ 0x13f00100,
0xd0160398, 0x0601fa06,
0x00800023, 0x00f803f8,
0x0017f180, /* 0x07fc: ctx_xfer */
0x0613f002, 0x0c00f7f1,
0xf80601fa, 0xf006f4b6,
/* 0x07fb: ctx_xfer */ 0xfed004e7,
0xf100f803, /* 0x0809: ctx_xfer_idle */
0xb60c00f7, 0x00fecf80,
0xe7f006f4, 0x2000e4f1,
0x80fed004, 0xf4f91bf4,
/* 0x0808: ctx_xfer_idle */ 0x02f40611,
0xf100fecf, /* 0x0819: ctx_xfer_pre */
0xf42000e4, 0x10f7f00d,
0x11f4f91b, 0x067321f5,
0x0d02f406, /* 0x0823: ctx_xfer_pre_load */
/* 0x0818: ctx_xfer_pre */ 0xf01c11f4,
0xf510f7f0, 0x21f502f7,
0xf4067221, 0x21f50632,
/* 0x0822: ctx_xfer_pre_load */ 0x21f50641,
0xf7f01c11, 0xf4bd0653,
0x3121f502, 0x063221f5,
0x4021f506, 0x069321f5,
0x5221f506, /* 0x083c: ctx_xfer_exec */
0xf5f4bd06, 0xf1160198,
0xf5063121, 0xb6041427,
/* 0x083b: ctx_xfer_exec */ 0x20d00624,
0x98069221, 0x00e7f100,
0x27f11601, 0x41e3f0a5,
0x24b60414, 0xf4021fb9,
0x0020d006, 0xe0b68d21,
0xa500e7f1, 0x01fcf004,
0xb941e3f0, 0xb6022cf0,
0x21f4021f, 0xf2fd0124,
0x04e0b68d, 0x8d21f405,
0xf001fcf0, 0x4afc17f1,
0x24b6022c, 0xf00213f0,
0x05f2fd01, 0x12d00c27,
0xf18d21f4, 0x0721f500,
0xf04afc17, 0xfc27f102,
0x27f00213, 0x0223f047,
0x0012d00c, 0xf00020d0,
0x020721f5, 0x20b6012c,
0x47fc27f1, 0x0012d003,
0xd00223f0, 0xf001acf0,
0x2cf00020, 0xb7f006a5,
0x0320b601, 0x140c9800,
0xf00012d0, 0xf0150d98,
0xa5f001ac, 0x21f500e7,
0x00b7f006, 0xa7f0015c,
0x98140c98, 0x0321f508,
0xe7f0150d, 0x0721f501,
0x5c21f500, 0x2201f402,
0x08a7f001, 0xf40ca7f0,
0x010321f5, 0x17f1c921,
0x020721f5, 0x14b60a10,
0xf02201f4, 0x0527f006,
0x21f40ca7, /* 0x08c3: ctx_xfer_post_save_wait */
0x1017f1c9, 0xcf0012d0,
0x0614b60a, 0x22fd0012,
0xd00527f0, 0xfa1bf405,
/* 0x08c2: ctx_xfer_post_save_wait */ /* 0x08cf: ctx_xfer_post */
0x12cf0012, 0xf02e02f4,
0x0522fd00, 0x21f502f7,
0xf4fa1bf4, 0xf4bd0632,
/* 0x08ce: ctx_xfer_post */ 0x067321f5,
0xf7f02e02, 0x022621f5,
0x3121f502, 0x064121f5,
0xf5f4bd06, 0x21f5f4bd,
0xf5067221, 0x11f40632,
0xf5022621, 0x40019810,
0xbd064021, 0xf40511fd,
0x3121f5f4, 0x21f5070b,
0x1011f406, /* 0x08fa: ctx_xfer_no_post_mmio */
0xfd800198, /* 0x08fa: ctx_xfer_done */
0x0bf40511, 0x00f807b2,
0xb121f507,
/* 0x08f9: ctx_xfer_no_post_mmio */
/* 0x08f9: ctx_xfer_done */
0x0000f807,
0x00000000, 0x00000000,
}; };
drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
View file @ cb1e06e0
...@@ -517,6 +517,13 @@ nve0_graph_init_unk40xx(struct nvc0_graph_priv *priv) ...@@ -517,6 +517,13 @@ nve0_graph_init_unk40xx(struct nvc0_graph_priv *priv)
{ {
nv_wr32(priv, 0x40415c, 0x00000000); nv_wr32(priv, 0x40415c, 0x00000000);
nv_wr32(priv, 0x404170, 0x00000000); nv_wr32(priv, 0x404170, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x4041b4, 0x00000000);
break;
default:
break;
}
} }
static void static void
...@@ -551,7 +558,14 @@ nve0_graph_init_unk58xx(struct nvc0_graph_priv *priv) ...@@ -551,7 +558,14 @@ nve0_graph_init_unk58xx(struct nvc0_graph_priv *priv)
{ {
nv_wr32(priv, 0x405844, 0x00ffffff); nv_wr32(priv, 0x405844, 0x00ffffff);
nv_wr32(priv, 0x405850, 0x00000000); nv_wr32(priv, 0x405850, 0x00000000);
nv_wr32(priv, 0x405900, 0x0000ff34); switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x405900, 0x0000ff00);
break;
default:
nv_wr32(priv, 0x405900, 0x0000ff34);
break;
}
nv_wr32(priv, 0x405908, 0x00000000); nv_wr32(priv, 0x405908, 0x00000000);
nv_wr32(priv, 0x405928, 0x00000000); nv_wr32(priv, 0x405928, 0x00000000);
nv_wr32(priv, 0x40592c, 0x00000000); nv_wr32(priv, 0x40592c, 0x00000000);
...@@ -567,11 +581,26 @@ static void ...@@ -567,11 +581,26 @@ static void
nve0_graph_init_unk70xx(struct nvc0_graph_priv *priv) nve0_graph_init_unk70xx(struct nvc0_graph_priv *priv)
{ {
nv_wr32(priv, 0x407010, 0x00000000); nv_wr32(priv, 0x407010, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x407040, 0x80440424);
nv_wr32(priv, 0x407048, 0x0000000a);
break;
default:
break;
}
} }
static void static void
nve0_graph_init_unk5bxx(struct nvc0_graph_priv *priv) nve0_graph_init_unk5bxx(struct nvc0_graph_priv *priv)
{ {
switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x505b44, 0x00000000);
break;
default:
break;
}
nv_wr32(priv, 0x405b50, 0x00000000); nv_wr32(priv, 0x405b50, 0x00000000);
} }
...@@ -610,11 +639,25 @@ nve0_graph_init_gpc(struct nvc0_graph_priv *priv) ...@@ -610,11 +639,25 @@ nve0_graph_init_gpc(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x418d00, 0x00000000); nv_wr32(priv, 0x418d00, 0x00000000);
nv_wr32(priv, 0x418d28, 0x00000000); nv_wr32(priv, 0x418d28, 0x00000000);
nv_wr32(priv, 0x418d2c, 0x00000000); nv_wr32(priv, 0x418d2c, 0x00000000);
nv_wr32(priv, 0x418f00, 0x00000000); switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x418f00, 0x00000400);
break;
default:
nv_wr32(priv, 0x418f00, 0x00000000);
break;
}
nv_wr32(priv, 0x418f08, 0x00000000); nv_wr32(priv, 0x418f08, 0x00000000);
nv_wr32(priv, 0x418f20, 0x00000000); nv_wr32(priv, 0x418f20, 0x00000000);
nv_wr32(priv, 0x418f24, 0x00000000); nv_wr32(priv, 0x418f24, 0x00000000);
nv_wr32(priv, 0x418e00, 0x00000060); switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x418e00, 0x00000000);
break;
default:
nv_wr32(priv, 0x418e00, 0x00000060);
break;
}
nv_wr32(priv, 0x418e08, 0x00000000); nv_wr32(priv, 0x418e08, 0x00000000);
nv_wr32(priv, 0x418e1c, 0x00000000); nv_wr32(priv, 0x418e1c, 0x00000000);
nv_wr32(priv, 0x418e20, 0x00000000); nv_wr32(priv, 0x418e20, 0x00000000);
...@@ -630,9 +673,24 @@ nve0_graph_init_tpc(struct nvc0_graph_priv *priv) ...@@ -630,9 +673,24 @@ nve0_graph_init_tpc(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x419ab0, 0x00000000); nv_wr32(priv, 0x419ab0, 0x00000000);
nv_wr32(priv, 0x419ac8, 0x00000000); nv_wr32(priv, 0x419ac8, 0x00000000);
nv_wr32(priv, 0x419ab8, 0x000000e7); nv_wr32(priv, 0x419ab8, 0x000000e7);
switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x419aec, 0x00000000);
break;
default:
break;
}
nv_wr32(priv, 0x419abc, 0x00000000); nv_wr32(priv, 0x419abc, 0x00000000);
nv_wr32(priv, 0x419ac0, 0x00000000); nv_wr32(priv, 0x419ac0, 0x00000000);
nv_wr32(priv, 0x419ab4, 0x00000000); nv_wr32(priv, 0x419ab4, 0x00000000);
switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x419aa8, 0x00000000);
nv_wr32(priv, 0x419aac, 0x00000000);
break;
default:
break;
}
nv_wr32(priv, 0x41980c, 0x00000010); nv_wr32(priv, 0x41980c, 0x00000010);
nv_wr32(priv, 0x419844, 0x00000000); nv_wr32(priv, 0x419844, 0x00000000);
nv_wr32(priv, 0x419850, 0x00000004); nv_wr32(priv, 0x419850, 0x00000004);
...@@ -644,23 +702,59 @@ nve0_graph_init_tpc(struct nvc0_graph_priv *priv) ...@@ -644,23 +702,59 @@ nve0_graph_init_tpc(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x419cb4, 0x00000000); nv_wr32(priv, 0x419cb4, 0x00000000);
nv_wr32(priv, 0x419cb8, 0x00b08bea); nv_wr32(priv, 0x419cb8, 0x00b08bea);
nv_wr32(priv, 0x419c84, 0x00010384); nv_wr32(priv, 0x419c84, 0x00010384);
nv_wr32(priv, 0x419cbc, 0x28137646); switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x419cbc, 0x281b3646);
break;
default:
nv_wr32(priv, 0x419cbc, 0x28137646);
break;
}
nv_wr32(priv, 0x419cc0, 0x00000000); nv_wr32(priv, 0x419cc0, 0x00000000);
nv_wr32(priv, 0x419cc4, 0x00000000); nv_wr32(priv, 0x419cc4, 0x00000000);
nv_wr32(priv, 0x419c80, 0x00020232); switch (nv_device(priv)->chipset) {
nv_wr32(priv, 0x419c0c, 0x00000000); case 0xf0:
nv_wr32(priv, 0x419e00, 0x00000000); nv_wr32(priv, 0x419c80, 0x00020230);
nv_wr32(priv, 0x419ccc, 0x00000000);
nv_wr32(priv, 0x419cd0, 0x00000000);
nv_wr32(priv, 0x419c0c, 0x00000000);
nv_wr32(priv, 0x419e00, 0x00000080);
break;
default:
nv_wr32(priv, 0x419c80, 0x00020232);
nv_wr32(priv, 0x419c0c, 0x00000000);
nv_wr32(priv, 0x419e00, 0x00000000);
break;
}
nv_wr32(priv, 0x419ea0, 0x00000000); nv_wr32(priv, 0x419ea0, 0x00000000);
nv_wr32(priv, 0x419ee4, 0x00000000); nv_wr32(priv, 0x419ee4, 0x00000000);
nv_wr32(priv, 0x419ea4, 0x00000100); nv_wr32(priv, 0x419ea4, 0x00000100);
nv_wr32(priv, 0x419ea8, 0x00000000); nv_wr32(priv, 0x419ea8, 0x00000000);
nv_wr32(priv, 0x419eb4, 0x00000000); nv_wr32(priv, 0x419eb4, 0x00000000);
nv_wr32(priv, 0x419eb8, 0x00000000); switch (nv_device(priv)->chipset) {
case 0xf0:
break;
default:
nv_wr32(priv, 0x419eb8, 0x00000000);
break;
}
nv_wr32(priv, 0x419ebc, 0x00000000); nv_wr32(priv, 0x419ebc, 0x00000000);
nv_wr32(priv, 0x419ec0, 0x00000000); nv_wr32(priv, 0x419ec0, 0x00000000);
nv_wr32(priv, 0x419edc, 0x00000000); nv_wr32(priv, 0x419edc, 0x00000000);
nv_wr32(priv, 0x419f00, 0x00000000); nv_wr32(priv, 0x419f00, 0x00000000);
nv_wr32(priv, 0x419f74, 0x00000555); switch (nv_device(priv)->chipset) {
case 0xf0:
nv_wr32(priv, 0x419ed0, 0x00003234);
nv_wr32(priv, 0x419f74, 0x00015555);
nv_wr32(priv, 0x419f80, 0x00000000);
nv_wr32(priv, 0x419f84, 0x00000000);
nv_wr32(priv, 0x419f88, 0x00000000);
nv_wr32(priv, 0x419f8c, 0x00000000);
break;
default:
nv_wr32(priv, 0x419f74, 0x00000555);
break;
}
} }
static void static void
...@@ -726,6 +820,7 @@ nve0_graph_init_units(struct nvc0_graph_priv *priv) ...@@ -726,6 +820,7 @@ nve0_graph_init_units(struct nvc0_graph_priv *priv)
switch (nv_device(priv)->chipset) { switch (nv_device(priv)->chipset) {
case 0xe7: case 0xe7:
case 0xe6: case 0xe6:
case 0xf0:
nv_wr32(priv, 0x407020, 0x40000000); nv_wr32(priv, 0x407020, 0x40000000);
break; break;
default: default:
...@@ -971,6 +1066,7 @@ nve0_graph_init(struct nouveau_object *object) ...@@ -971,6 +1066,7 @@ nve0_graph_init(struct nouveau_object *object)
switch (nv_device(priv)->chipset) { switch (nv_device(priv)->chipset) {
case 0xe7: case 0xe7:
case 0xe6: case 0xe6:
case 0xf0:
nve0_graph_init_unk40xx(priv); nve0_graph_init_unk40xx(priv);
nve0_graph_init_unk44xx(priv); nve0_graph_init_unk44xx(priv);
nve0_graph_init_unk78xx(priv); nve0_graph_init_unk78xx(priv);
......
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