Commit cb6d08a2 authored by Ryo Kataoka's avatar Ryo Kataoka Committed by Simon Horman

ARM: shmobile: r8a7791: Remove MSIOF address from device tree

MSIOF Base Address H'E6xx can be accessed by CPU and DMAC.
MSIOF Base Address H'E7xx for DMAC was removed from H/W manual.
Signed-off-by: default avatarRyo Kataoka <ryo.kataoka.wt@renesas.com>
Signed-off-by: default avatarYoshihiro Kaneko <ykaneko0929@gmail.com>
Acked-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent c7d1f08a
...@@ -60,7 +60,7 @@ Example: ...@@ -60,7 +60,7 @@ Example:
msiof0: spi@e6e20000 { msiof0: spi@e6e20000 {
compatible = "renesas,msiof-r8a7791"; compatible = "renesas,msiof-r8a7791";
reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>; reg = <0 0xe6e20000 0 0x0064>;
interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
dmas = <&dmac0 0x51>, <&dmac0 0x52>; dmas = <&dmac0 0x51>, <&dmac0 0x52>;
......
...@@ -1288,7 +1288,7 @@ qspi: spi@e6b10000 { ...@@ -1288,7 +1288,7 @@ qspi: spi@e6b10000 {
msiof0: spi@e6e20000 { msiof0: spi@e6e20000 {
compatible = "renesas,msiof-r8a7791"; compatible = "renesas,msiof-r8a7791";
reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>; reg = <0 0xe6e20000 0 0x0064>;
interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
dmas = <&dmac0 0x51>, <&dmac0 0x52>; dmas = <&dmac0 0x51>, <&dmac0 0x52>;
...@@ -1300,7 +1300,7 @@ msiof0: spi@e6e20000 { ...@@ -1300,7 +1300,7 @@ msiof0: spi@e6e20000 {
msiof1: spi@e6e10000 { msiof1: spi@e6e10000 {
compatible = "renesas,msiof-r8a7791"; compatible = "renesas,msiof-r8a7791";
reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>; reg = <0 0xe6e10000 0 0x0064>;
interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
dmas = <&dmac0 0x55>, <&dmac0 0x56>; dmas = <&dmac0 0x55>, <&dmac0 0x56>;
...@@ -1312,7 +1312,7 @@ msiof1: spi@e6e10000 { ...@@ -1312,7 +1312,7 @@ msiof1: spi@e6e10000 {
msiof2: spi@e6e00000 { msiof2: spi@e6e00000 {
compatible = "renesas,msiof-r8a7791"; compatible = "renesas,msiof-r8a7791";
reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>; reg = <0 0xe6e00000 0 0x0064>;
interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
dmas = <&dmac0 0x41>, <&dmac0 0x42>; dmas = <&dmac0 0x41>, <&dmac0 0x42>;
......
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