Commit cc6c9848 authored by Palmer Dabbelt's avatar Palmer Dabbelt Committed by Thomas Gleixner

RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler

The existing mechanism for handling IRQs on RISC-V is pretty ugly: the irq
entry code selects the handler via Kconfig dependencies.

Use the new generic IRQ handling infastructure, which allows boot time
registration of the low level entry handler.

This does add an additional load to the interrupt latency, but there's a
lot of tuning left to be done there on RISC-V so it's OK for now.
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarChristoph Hellwig <hch@lst.de>
Acked-by: default avatarStafford Horne <shorne@gmail.com>
Cc: jonas@southpole.se
Cc: catalin.marinas@arm.com
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux@armlinux.org.uk
Cc: stefan.kristiansson@saunalahti.fi
Cc: openrisc@lists.librecores.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lkml.kernel.org/r/20180307235731.22627-3-palmer@sifive.com
parent caacdbf4
...@@ -33,6 +33,7 @@ config RISCV ...@@ -33,6 +33,7 @@ config RISCV
select MODULES_USE_ELF_RELA if MODULES select MODULES_USE_ELF_RELA if MODULES
select THREAD_INFO_IN_TASK select THREAD_INFO_IN_TASK
select RISCV_TIMER select RISCV_TIMER
select GENERIC_IRQ_MULTI_HANDLER
config MMU config MMU
def_bool y def_bool y
......
...@@ -15,6 +15,7 @@ generic-y += fcntl.h ...@@ -15,6 +15,7 @@ generic-y += fcntl.h
generic-y += futex.h generic-y += futex.h
generic-y += hardirq.h generic-y += hardirq.h
generic-y += hash.h generic-y += hash.h
generic-y += handle_irq.h
generic-y += hw_irq.h generic-y += hw_irq.h
generic-y += ioctl.h generic-y += ioctl.h
generic-y += ioctls.h generic-y += ioctls.h
......
...@@ -167,10 +167,9 @@ ENTRY(handle_exception) ...@@ -167,10 +167,9 @@ ENTRY(handle_exception)
bge s4, zero, 1f bge s4, zero, 1f
/* Handle interrupts */ /* Handle interrupts */
slli a0, s4, 1 move a0, sp /* pt_regs */
srli a0, a0, 1 REG_L a1, handle_arch_irq
move a1, sp /* pt_regs */ jr a1
tail do_IRQ
1: 1:
/* Exceptions run with interrupts enabled */ /* Exceptions run with interrupts enabled */
csrs sstatus, SR_SIE csrs sstatus, SR_SIE
......
...@@ -24,16 +24,3 @@ void __init init_IRQ(void) ...@@ -24,16 +24,3 @@ void __init init_IRQ(void)
{ {
irqchip_init(); irqchip_init();
} }
asmlinkage void __irq_entry do_IRQ(unsigned int cause, struct pt_regs *regs)
{
#ifdef CONFIG_RISCV_INTC
/*
* FIXME: We don't want a direct call to riscv_intc_irq here. The plan
* is to put an IRQ domain here and let the interrupt controller
* register with that, but I poked around the arm64 code a bit and
* there might be a better way to do it (ie, something fully generic).
*/
riscv_intc_irq(cause, regs);
#endif
}
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