Commit d1b5ef00 authored by Fabien Parent's avatar Fabien Parent Committed by Joerg Roedel

iommu/mediatek: Add flag for legacy ivrp paddr

Add a new flag in order to select which IVRP_PADDR format is used
by an SoC.
Signed-off-by: default avatarFabien Parent <fparent@baylibre.com>
Reviewed-by: default avatarYong Wu <yong.wu@mediatek.com>
Reviewed-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
Link: https://lore.kernel.org/r/20200907101649.1573134-2-fparent@baylibre.comSigned-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent f7f842cc
...@@ -118,6 +118,7 @@ ...@@ -118,6 +118,7 @@
#define OUT_ORDER_WR_EN BIT(4) #define OUT_ORDER_WR_EN BIT(4)
#define HAS_SUB_COMM BIT(5) #define HAS_SUB_COMM BIT(5)
#define WR_THROT_EN BIT(6) #define WR_THROT_EN BIT(6)
#define HAS_LEGACY_IVRP_PADDR BIT(7)
#define MTK_IOMMU_HAS_FLAG(pdata, _x) \ #define MTK_IOMMU_HAS_FLAG(pdata, _x) \
((((pdata)->flags) & (_x)) == (_x)) ((((pdata)->flags) & (_x)) == (_x))
...@@ -584,7 +585,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) ...@@ -584,7 +585,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
F_INT_PRETETCH_TRANSATION_FIFO_FAULT; F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL); writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
if (data->plat_data->m4u_plat == M4U_MT8173) if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
regval = (data->protect_base >> 1) | (data->enable_4GB << 31); regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
else else
regval = lower_32_bits(data->protect_base) | regval = lower_32_bits(data->protect_base) |
...@@ -841,7 +842,8 @@ static const struct mtk_iommu_plat_data mt6779_data = { ...@@ -841,7 +842,8 @@ static const struct mtk_iommu_plat_data mt6779_data = {
static const struct mtk_iommu_plat_data mt8173_data = { static const struct mtk_iommu_plat_data mt8173_data = {
.m4u_plat = M4U_MT8173, .m4u_plat = M4U_MT8173,
.flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI, .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
HAS_LEGACY_IVRP_PADDR,
.inv_sel_reg = REG_MMU_INV_SEL_GEN1, .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
}; };
......
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