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Commit d278dae8 authored by Linus Walleij's avatar Linus Walleij
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Merge tag 'sh-pfc-for-v4.10-tag2' of... 

Merge tag 'sh-pfc-for-v4.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.10 (take two)

  - DU and EtherAVB pin groups for R-Car M3-W,
  - Bias handling cleanups and bug fixes,
  - Drive-strength for non-GPIO pins for R-Car H3,
  - EtherAVB MDIO & MII, and QSPI pin groups for R-Car H3.
parents 688daf23 1fa1522f
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drivers/pinctrl/sh-pfc/core.c
View file @ d278dae8
......@@ -389,6 +389,21 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
return 0;
}
const struct sh_pfc_bias_info *
sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
unsigned int num, unsigned int pin)
{
unsigned int i;
for (i = 0; i < num; i++)
if (info[i].pin == pin)
return &info[i];
WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
return NULL;
}
static int sh_pfc_init_ranges(struct sh_pfc *pfc)
{
struct sh_pfc_pin_range *range;
......
drivers/pinctrl/sh-pfc/core.h
View file @ d278dae8
......@@ -33,4 +33,8 @@ void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width,
int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
const struct sh_pfc_bias_info *
sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
unsigned int num, unsigned int pin);
#endif /* __SH_PFC_CORE_H__ */
drivers/pinctrl/sh-pfc/pfc-r8a7778.c
View file @ d278dae8
......@@ -24,6 +24,7 @@
#include <linux/kernel.h>
#include <linux/pinctrl/pinconf-generic.h>
#include "core.h"
#include "sh_pfc.h"
#define PORT_GP_PUP_1(bank, pin, fn, sfx) \
......@@ -2918,183 +2919,182 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define PUPR4 0x110
#define PUPR5 0x114
static const struct {
u16 reg : 11;
u16 bit : 5;
} pullups[] = {
[RCAR_GP_PIN(0, 6)] = { PUPR0, 0 }, /* A0 */
[RCAR_GP_PIN(0, 7)] = { PUPR0, 1 }, /* A1 */
[RCAR_GP_PIN(0, 8)] = { PUPR0, 2 }, /* A2 */
[RCAR_GP_PIN(0, 9)] = { PUPR0, 3 }, /* A3 */
[RCAR_GP_PIN(0, 10)] = { PUPR0, 4 }, /* A4 */
[RCAR_GP_PIN(0, 11)] = { PUPR0, 5 }, /* A5 */
[RCAR_GP_PIN(0, 12)] = { PUPR0, 6 }, /* A6 */
[RCAR_GP_PIN(0, 13)] = { PUPR0, 7 }, /* A7 */
[RCAR_GP_PIN(0, 14)] = { PUPR0, 8 }, /* A8 */
[RCAR_GP_PIN(0, 15)] = { PUPR0, 9 }, /* A9 */
[RCAR_GP_PIN(0, 16)] = { PUPR0, 10 }, /* A10 */
[RCAR_GP_PIN(0, 17)] = { PUPR0, 11 }, /* A11 */
[RCAR_GP_PIN(0, 18)] = { PUPR0, 12 }, /* A12 */
[RCAR_GP_PIN(0, 19)] = { PUPR0, 13 }, /* A13 */
[RCAR_GP_PIN(0, 20)] = { PUPR0, 14 }, /* A14 */
[RCAR_GP_PIN(0, 21)] = { PUPR0, 15 }, /* A15 */
[RCAR_GP_PIN(0, 22)] = { PUPR0, 16 }, /* A16 */
[RCAR_GP_PIN(0, 23)] = { PUPR0, 17 }, /* A17 */
[RCAR_GP_PIN(0, 24)] = { PUPR0, 18 }, /* A18 */
[RCAR_GP_PIN(0, 25)] = { PUPR0, 19 }, /* A19 */
[RCAR_GP_PIN(0, 26)] = { PUPR0, 20 }, /* A20 */
[RCAR_GP_PIN(0, 27)] = { PUPR0, 21 }, /* A21 */
[RCAR_GP_PIN(0, 28)] = { PUPR0, 22 }, /* A22 */
[RCAR_GP_PIN(0, 29)] = { PUPR0, 23 }, /* A23 */
[RCAR_GP_PIN(0, 30)] = { PUPR0, 24 }, /* A24 */
[RCAR_GP_PIN(0, 31)] = { PUPR0, 25 }, /* A25 */
[RCAR_GP_PIN(1, 3)] = { PUPR0, 26 }, /* /EX_CS0 */
[RCAR_GP_PIN(1, 4)] = { PUPR0, 27 }, /* /EX_CS1 */
[RCAR_GP_PIN(1, 5)] = { PUPR0, 28 }, /* /EX_CS2 */
[RCAR_GP_PIN(1, 6)] = { PUPR0, 29 }, /* /EX_CS3 */
[RCAR_GP_PIN(1, 7)] = { PUPR0, 30 }, /* /EX_CS4 */
[RCAR_GP_PIN(1, 8)] = { PUPR0, 31 }, /* /EX_CS5 */
[RCAR_GP_PIN(0, 0)] = { PUPR1, 0 }, /* /PRESETOUT */
[RCAR_GP_PIN(0, 5)] = { PUPR1, 1 }, /* /BS */
[RCAR_GP_PIN(1, 0)] = { PUPR1, 2 }, /* RD//WR */
[RCAR_GP_PIN(1, 1)] = { PUPR1, 3 }, /* /WE0 */
[RCAR_GP_PIN(1, 2)] = { PUPR1, 4 }, /* /WE1 */
[RCAR_GP_PIN(1, 11)] = { PUPR1, 5 }, /* EX_WAIT0 */
[RCAR_GP_PIN(1, 9)] = { PUPR1, 6 }, /* DREQ0 */
[RCAR_GP_PIN(1, 10)] = { PUPR1, 7 }, /* DACK0 */
[RCAR_GP_PIN(1, 12)] = { PUPR1, 8 }, /* IRQ0 */
[RCAR_GP_PIN(1, 13)] = { PUPR1, 9 }, /* IRQ1 */
[RCAR_GP_PIN(1, 22)] = { PUPR2, 0 }, /* DU0_DR0 */
[RCAR_GP_PIN(1, 23)] = { PUPR2, 1 }, /* DU0_DR1 */
[RCAR_GP_PIN(1, 24)] = { PUPR2, 2 }, /* DU0_DR2 */
[RCAR_GP_PIN(1, 25)] = { PUPR2, 3 }, /* DU0_DR3 */
[RCAR_GP_PIN(1, 26)] = { PUPR2, 4 }, /* DU0_DR4 */
[RCAR_GP_PIN(1, 27)] = { PUPR2, 5 }, /* DU0_DR5 */
[RCAR_GP_PIN(1, 28)] = { PUPR2, 6 }, /* DU0_DR6 */
[RCAR_GP_PIN(1, 29)] = { PUPR2, 7 }, /* DU0_DR7 */
[RCAR_GP_PIN(1, 30)] = { PUPR2, 8 }, /* DU0_DG0 */
[RCAR_GP_PIN(1, 31)] = { PUPR2, 9 }, /* DU0_DG1 */
[RCAR_GP_PIN(2, 0)] = { PUPR2, 10 }, /* DU0_DG2 */
[RCAR_GP_PIN(2, 1)] = { PUPR2, 11 }, /* DU0_DG3 */
[RCAR_GP_PIN(2, 2)] = { PUPR2, 12 }, /* DU0_DG4 */
[RCAR_GP_PIN(2, 3)] = { PUPR2, 13 }, /* DU0_DG5 */
[RCAR_GP_PIN(2, 4)] = { PUPR2, 14 }, /* DU0_DG6 */
[RCAR_GP_PIN(2, 5)] = { PUPR2, 15 }, /* DU0_DG7 */
[RCAR_GP_PIN(2, 6)] = { PUPR2, 16 }, /* DU0_DB0 */
[RCAR_GP_PIN(2, 7)] = { PUPR2, 17 }, /* DU0_DB1 */
[RCAR_GP_PIN(2, 8)] = { PUPR2, 18 }, /* DU0_DB2 */
[RCAR_GP_PIN(2, 9)] = { PUPR2, 19 }, /* DU0_DB3 */
[RCAR_GP_PIN(2, 10)] = { PUPR2, 20 }, /* DU0_DB4 */
[RCAR_GP_PIN(2, 11)] = { PUPR2, 21 }, /* DU0_DB5 */
[RCAR_GP_PIN(2, 12)] = { PUPR2, 22 }, /* DU0_DB6 */
[RCAR_GP_PIN(2, 13)] = { PUPR2, 23 }, /* DU0_DB7 */
[RCAR_GP_PIN(2, 14)] = { PUPR2, 24 }, /* DU0_DOTCLKIN */
[RCAR_GP_PIN(2, 15)] = { PUPR2, 25 }, /* DU0_DOTCLKOUT0 */
[RCAR_GP_PIN(2, 17)] = { PUPR2, 26 }, /* DU0_HSYNC */
[RCAR_GP_PIN(2, 18)] = { PUPR2, 27 }, /* DU0_VSYNC */
[RCAR_GP_PIN(2, 19)] = { PUPR2, 28 }, /* DU0_EXODDF */
[RCAR_GP_PIN(2, 20)] = { PUPR2, 29 }, /* DU0_DISP */
[RCAR_GP_PIN(2, 21)] = { PUPR2, 30 }, /* DU0_CDE */
[RCAR_GP_PIN(2, 16)] = { PUPR2, 31 }, /* DU0_DOTCLKOUT1 */
[RCAR_GP_PIN(3, 24)] = { PUPR3, 0 }, /* VI0_CLK */
[RCAR_GP_PIN(3, 25)] = { PUPR3, 1 }, /* VI0_CLKENB */
[RCAR_GP_PIN(3, 26)] = { PUPR3, 2 }, /* VI0_FIELD */
[RCAR_GP_PIN(3, 27)] = { PUPR3, 3 }, /* /VI0_HSYNC */
[RCAR_GP_PIN(3, 28)] = { PUPR3, 4 }, /* /VI0_VSYNC */
[RCAR_GP_PIN(3, 29)] = { PUPR3, 5 }, /* VI0_DATA0 */
[RCAR_GP_PIN(3, 30)] = { PUPR3, 6 }, /* VI0_DATA1 */
[RCAR_GP_PIN(3, 31)] = { PUPR3, 7 }, /* VI0_DATA2 */
[RCAR_GP_PIN(4, 0)] = { PUPR3, 8 }, /* VI0_DATA3 */
[RCAR_GP_PIN(4, 1)] = { PUPR3, 9 }, /* VI0_DATA4 */
[RCAR_GP_PIN(4, 2)] = { PUPR3, 10 }, /* VI0_DATA5 */
[RCAR_GP_PIN(4, 3)] = { PUPR3, 11 }, /* VI0_DATA6 */
[RCAR_GP_PIN(4, 4)] = { PUPR3, 12 }, /* VI0_DATA7 */
[RCAR_GP_PIN(4, 5)] = { PUPR3, 13 }, /* VI0_G2 */
[RCAR_GP_PIN(4, 6)] = { PUPR3, 14 }, /* VI0_G3 */
[RCAR_GP_PIN(4, 7)] = { PUPR3, 15 }, /* VI0_G4 */
[RCAR_GP_PIN(4, 8)] = { PUPR3, 16 }, /* VI0_G5 */
[RCAR_GP_PIN(4, 21)] = { PUPR3, 17 }, /* VI1_DATA12 */
[RCAR_GP_PIN(4, 22)] = { PUPR3, 18 }, /* VI1_DATA13 */
[RCAR_GP_PIN(4, 23)] = { PUPR3, 19 }, /* VI1_DATA14 */
[RCAR_GP_PIN(4, 24)] = { PUPR3, 20 }, /* VI1_DATA15 */
[RCAR_GP_PIN(4, 9)] = { PUPR3, 21 }, /* ETH_REF_CLK */
[RCAR_GP_PIN(4, 10)] = { PUPR3, 22 }, /* ETH_TXD0 */
[RCAR_GP_PIN(4, 11)] = { PUPR3, 23 }, /* ETH_TXD1 */
[RCAR_GP_PIN(4, 12)] = { PUPR3, 24 }, /* ETH_CRS_DV */
[RCAR_GP_PIN(4, 13)] = { PUPR3, 25 }, /* ETH_TX_EN */
[RCAR_GP_PIN(4, 14)] = { PUPR3, 26 }, /* ETH_RX_ER */
[RCAR_GP_PIN(4, 15)] = { PUPR3, 27 }, /* ETH_RXD0 */
[RCAR_GP_PIN(4, 16)] = { PUPR3, 28 }, /* ETH_RXD1 */
[RCAR_GP_PIN(4, 17)] = { PUPR3, 29 }, /* ETH_MDC */
[RCAR_GP_PIN(4, 18)] = { PUPR3, 30 }, /* ETH_MDIO */
[RCAR_GP_PIN(4, 19)] = { PUPR3, 31 }, /* ETH_LINK */
[RCAR_GP_PIN(3, 6)] = { PUPR4, 0 }, /* SSI_SCK012 */
[RCAR_GP_PIN(3, 7)] = { PUPR4, 1 }, /* SSI_WS012 */
[RCAR_GP_PIN(3, 10)] = { PUPR4, 2 }, /* SSI_SDATA0 */
[RCAR_GP_PIN(3, 9)] = { PUPR4, 3 }, /* SSI_SDATA1 */
[RCAR_GP_PIN(3, 8)] = { PUPR4, 4 }, /* SSI_SDATA2 */
[RCAR_GP_PIN(3, 2)] = { PUPR4, 5 }, /* SSI_SCK34 */
[RCAR_GP_PIN(3, 3)] = { PUPR4, 6 }, /* SSI_WS34 */
[RCAR_GP_PIN(3, 5)] = { PUPR4, 7 }, /* SSI_SDATA3 */
[RCAR_GP_PIN(3, 4)] = { PUPR4, 8 }, /* SSI_SDATA4 */
[RCAR_GP_PIN(2, 31)] = { PUPR4, 9 }, /* SSI_SCK5 */
[RCAR_GP_PIN(3, 0)] = { PUPR4, 10 }, /* SSI_WS5 */
[RCAR_GP_PIN(3, 1)] = { PUPR4, 11 }, /* SSI_SDATA5 */
[RCAR_GP_PIN(2, 28)] = { PUPR4, 12 }, /* SSI_SCK6 */
[RCAR_GP_PIN(2, 29)] = { PUPR4, 13 }, /* SSI_WS6 */
[RCAR_GP_PIN(2, 30)] = { PUPR4, 14 }, /* SSI_SDATA6 */
[RCAR_GP_PIN(2, 24)] = { PUPR4, 15 }, /* SSI_SCK78 */
[RCAR_GP_PIN(2, 25)] = { PUPR4, 16 }, /* SSI_WS78 */
[RCAR_GP_PIN(2, 27)] = { PUPR4, 17 }, /* SSI_SDATA7 */
[RCAR_GP_PIN(2, 26)] = { PUPR4, 18 }, /* SSI_SDATA8 */
[RCAR_GP_PIN(3, 23)] = { PUPR4, 19 }, /* TCLK0 */
[RCAR_GP_PIN(3, 11)] = { PUPR4, 20 }, /* SD0_CLK */
[RCAR_GP_PIN(3, 12)] = { PUPR4, 21 }, /* SD0_CMD */
[RCAR_GP_PIN(3, 13)] = { PUPR4, 22 }, /* SD0_DAT0 */
[RCAR_GP_PIN(3, 14)] = { PUPR4, 23 }, /* SD0_DAT1 */
[RCAR_GP_PIN(3, 15)] = { PUPR4, 24 }, /* SD0_DAT2 */
[RCAR_GP_PIN(3, 16)] = { PUPR4, 25 }, /* SD0_DAT3 */
[RCAR_GP_PIN(3, 17)] = { PUPR4, 26 }, /* SD0_CD */
[RCAR_GP_PIN(3, 18)] = { PUPR4, 27 }, /* SD0_WP */
[RCAR_GP_PIN(2, 22)] = { PUPR4, 28 }, /* AUDIO_CLKA */
[RCAR_GP_PIN(2, 23)] = { PUPR4, 29 }, /* AUDIO_CLKB */
[RCAR_GP_PIN(1, 14)] = { PUPR4, 30 }, /* IRQ2 */
[RCAR_GP_PIN(1, 15)] = { PUPR4, 31 }, /* IRQ3 */
[RCAR_GP_PIN(0, 1)] = { PUPR5, 0 }, /* PENC0 */
[RCAR_GP_PIN(0, 2)] = { PUPR5, 1 }, /* PENC1 */
[RCAR_GP_PIN(0, 3)] = { PUPR5, 2 }, /* USB_OVC0 */
[RCAR_GP_PIN(0, 4)] = { PUPR5, 3 }, /* USB_OVC1 */
[RCAR_GP_PIN(1, 16)] = { PUPR5, 4 }, /* SCIF_CLK */
[RCAR_GP_PIN(1, 17)] = { PUPR5, 5 }, /* TX0 */
[RCAR_GP_PIN(1, 18)] = { PUPR5, 6 }, /* RX0 */
[RCAR_GP_PIN(1, 19)] = { PUPR5, 7 }, /* SCK0 */
[RCAR_GP_PIN(1, 20)] = { PUPR5, 8 }, /* /CTS0 */
[RCAR_GP_PIN(1, 21)] = { PUPR5, 9 }, /* /RTS0 */
[RCAR_GP_PIN(3, 19)] = { PUPR5, 10 }, /* HSPI_CLK0 */
[RCAR_GP_PIN(3, 20)] = { PUPR5, 11 }, /* /HSPI_CS0 */
[RCAR_GP_PIN(3, 21)] = { PUPR5, 12 }, /* HSPI_RX0 */
[RCAR_GP_PIN(3, 22)] = { PUPR5, 13 }, /* HSPI_TX0 */
[RCAR_GP_PIN(4, 20)] = { PUPR5, 14 }, /* ETH_MAGIC */
[RCAR_GP_PIN(4, 25)] = { PUPR5, 15 }, /* AVS1 */
[RCAR_GP_PIN(4, 26)] = { PUPR5, 16 }, /* AVS2 */
static const struct sh_pfc_bias_info bias_info[] = {
{ RCAR_GP_PIN(0, 6), PUPR0, 0 }, /* A0 */
{ RCAR_GP_PIN(0, 7), PUPR0, 1 }, /* A1 */
{ RCAR_GP_PIN(0, 8), PUPR0, 2 }, /* A2 */
{ RCAR_GP_PIN(0, 9), PUPR0, 3 }, /* A3 */
{ RCAR_GP_PIN(0, 10), PUPR0, 4 }, /* A4 */
{ RCAR_GP_PIN(0, 11), PUPR0, 5 }, /* A5 */
{ RCAR_GP_PIN(0, 12), PUPR0, 6 }, /* A6 */
{ RCAR_GP_PIN(0, 13), PUPR0, 7 }, /* A7 */
{ RCAR_GP_PIN(0, 14), PUPR0, 8 }, /* A8 */
{ RCAR_GP_PIN(0, 15), PUPR0, 9 }, /* A9 */
{ RCAR_GP_PIN(0, 16), PUPR0, 10 }, /* A10 */
{ RCAR_GP_PIN(0, 17), PUPR0, 11 }, /* A11 */
{ RCAR_GP_PIN(0, 18), PUPR0, 12 }, /* A12 */
{ RCAR_GP_PIN(0, 19), PUPR0, 13 }, /* A13 */
{ RCAR_GP_PIN(0, 20), PUPR0, 14 }, /* A14 */
{ RCAR_GP_PIN(0, 21), PUPR0, 15 }, /* A15 */
{ RCAR_GP_PIN(0, 22), PUPR0, 16 }, /* A16 */
{ RCAR_GP_PIN(0, 23), PUPR0, 17 }, /* A17 */
{ RCAR_GP_PIN(0, 24), PUPR0, 18 }, /* A18 */
{ RCAR_GP_PIN(0, 25), PUPR0, 19 }, /* A19 */
{ RCAR_GP_PIN(0, 26), PUPR0, 20 }, /* A20 */
{ RCAR_GP_PIN(0, 27), PUPR0, 21 }, /* A21 */
{ RCAR_GP_PIN(0, 28), PUPR0, 22 }, /* A22 */
{ RCAR_GP_PIN(0, 29), PUPR0, 23 }, /* A23 */
{ RCAR_GP_PIN(0, 30), PUPR0, 24 }, /* A24 */
{ RCAR_GP_PIN(0, 31), PUPR0, 25 }, /* A25 */
{ RCAR_GP_PIN(1, 3), PUPR0, 26 }, /* /EX_CS0 */
{ RCAR_GP_PIN(1, 4), PUPR0, 27 }, /* /EX_CS1 */
{ RCAR_GP_PIN(1, 5), PUPR0, 28 }, /* /EX_CS2 */
{ RCAR_GP_PIN(1, 6), PUPR0, 29 }, /* /EX_CS3 */
{ RCAR_GP_PIN(1, 7), PUPR0, 30 }, /* /EX_CS4 */
{ RCAR_GP_PIN(1, 8), PUPR0, 31 }, /* /EX_CS5 */
{ RCAR_GP_PIN(0, 0), PUPR1, 0 }, /* /PRESETOUT */
{ RCAR_GP_PIN(0, 5), PUPR1, 1 }, /* /BS */
{ RCAR_GP_PIN(1, 0), PUPR1, 2 }, /* RD//WR */
{ RCAR_GP_PIN(1, 1), PUPR1, 3 }, /* /WE0 */
{ RCAR_GP_PIN(1, 2), PUPR1, 4 }, /* /WE1 */
{ RCAR_GP_PIN(1, 11), PUPR1, 5 }, /* EX_WAIT0 */
{ RCAR_GP_PIN(1, 9), PUPR1, 6 }, /* DREQ0 */
{ RCAR_GP_PIN(1, 10), PUPR1, 7 }, /* DACK0 */
{ RCAR_GP_PIN(1, 12), PUPR1, 8 }, /* IRQ0 */
{ RCAR_GP_PIN(1, 13), PUPR1, 9 }, /* IRQ1 */
{ RCAR_GP_PIN(1, 22), PUPR2, 0 }, /* DU0_DR0 */
{ RCAR_GP_PIN(1, 23), PUPR2, 1 }, /* DU0_DR1 */
{ RCAR_GP_PIN(1, 24), PUPR2, 2 }, /* DU0_DR2 */
{ RCAR_GP_PIN(1, 25), PUPR2, 3 }, /* DU0_DR3 */
{ RCAR_GP_PIN(1, 26), PUPR2, 4 }, /* DU0_DR4 */
{ RCAR_GP_PIN(1, 27), PUPR2, 5 }, /* DU0_DR5 */
{ RCAR_GP_PIN(1, 28), PUPR2, 6 }, /* DU0_DR6 */
{ RCAR_GP_PIN(1, 29), PUPR2, 7 }, /* DU0_DR7 */
{ RCAR_GP_PIN(1, 30), PUPR2, 8 }, /* DU0_DG0 */
{ RCAR_GP_PIN(1, 31), PUPR2, 9 }, /* DU0_DG1 */
{ RCAR_GP_PIN(2, 0), PUPR2, 10 }, /* DU0_DG2 */
{ RCAR_GP_PIN(2, 1), PUPR2, 11 }, /* DU0_DG3 */
{ RCAR_GP_PIN(2, 2), PUPR2, 12 }, /* DU0_DG4 */
{ RCAR_GP_PIN(2, 3), PUPR2, 13 }, /* DU0_DG5 */
{ RCAR_GP_PIN(2, 4), PUPR2, 14 }, /* DU0_DG6 */
{ RCAR_GP_PIN(2, 5), PUPR2, 15 }, /* DU0_DG7 */
{ RCAR_GP_PIN(2, 6), PUPR2, 16 }, /* DU0_DB0 */
{ RCAR_GP_PIN(2, 7), PUPR2, 17 }, /* DU0_DB1 */
{ RCAR_GP_PIN(2, 8), PUPR2, 18 }, /* DU0_DB2 */
{ RCAR_GP_PIN(2, 9), PUPR2, 19 }, /* DU0_DB3 */
{ RCAR_GP_PIN(2, 10), PUPR2, 20 }, /* DU0_DB4 */
{ RCAR_GP_PIN(2, 11), PUPR2, 21 }, /* DU0_DB5 */
{ RCAR_GP_PIN(2, 12), PUPR2, 22 }, /* DU0_DB6 */
{ RCAR_GP_PIN(2, 13), PUPR2, 23 }, /* DU0_DB7 */
{ RCAR_GP_PIN(2, 14), PUPR2, 24 }, /* DU0_DOTCLKIN */
{ RCAR_GP_PIN(2, 15), PUPR2, 25 }, /* DU0_DOTCLKOUT0 */
{ RCAR_GP_PIN(2, 17), PUPR2, 26 }, /* DU0_HSYNC */
{ RCAR_GP_PIN(2, 18), PUPR2, 27 }, /* DU0_VSYNC */
{ RCAR_GP_PIN(2, 19), PUPR2, 28 }, /* DU0_EXODDF */
{ RCAR_GP_PIN(2, 20), PUPR2, 29 }, /* DU0_DISP */
{ RCAR_GP_PIN(2, 21), PUPR2, 30 }, /* DU0_CDE */
{ RCAR_GP_PIN(2, 16), PUPR2, 31 }, /* DU0_DOTCLKOUT1 */
{ RCAR_GP_PIN(3, 24), PUPR3, 0 }, /* VI0_CLK */
{ RCAR_GP_PIN(3, 25), PUPR3, 1 }, /* VI0_CLKENB */
{ RCAR_GP_PIN(3, 26), PUPR3, 2 }, /* VI0_FIELD */
{ RCAR_GP_PIN(3, 27), PUPR3, 3 }, /* /VI0_HSYNC */
{ RCAR_GP_PIN(3, 28), PUPR3, 4 }, /* /VI0_VSYNC */
{ RCAR_GP_PIN(3, 29), PUPR3, 5 }, /* VI0_DATA0 */
{ RCAR_GP_PIN(3, 30), PUPR3, 6 }, /* VI0_DATA1 */
{ RCAR_GP_PIN(3, 31), PUPR3, 7 }, /* VI0_DATA2 */
{ RCAR_GP_PIN(4, 0), PUPR3, 8 }, /* VI0_DATA3 */
{ RCAR_GP_PIN(4, 1), PUPR3, 9 }, /* VI0_DATA4 */
{ RCAR_GP_PIN(4, 2), PUPR3, 10 }, /* VI0_DATA5 */
{ RCAR_GP_PIN(4, 3), PUPR3, 11 }, /* VI0_DATA6 */
{ RCAR_GP_PIN(4, 4), PUPR3, 12 }, /* VI0_DATA7 */
{ RCAR_GP_PIN(4, 5), PUPR3, 13 }, /* VI0_G2 */
{ RCAR_GP_PIN(4, 6), PUPR3, 14 }, /* VI0_G3 */
{ RCAR_GP_PIN(4, 7), PUPR3, 15 }, /* VI0_G4 */
{ RCAR_GP_PIN(4, 8), PUPR3, 16 }, /* VI0_G5 */
{ RCAR_GP_PIN(4, 21), PUPR3, 17 }, /* VI1_DATA12 */
{ RCAR_GP_PIN(4, 22), PUPR3, 18 }, /* VI1_DATA13 */
{ RCAR_GP_PIN(4, 23), PUPR3, 19 }, /* VI1_DATA14 */
{ RCAR_GP_PIN(4, 24), PUPR3, 20 }, /* VI1_DATA15 */
{ RCAR_GP_PIN(4, 9), PUPR3, 21 }, /* ETH_REF_CLK */
{ RCAR_GP_PIN(4, 10), PUPR3, 22 }, /* ETH_TXD0 */
{ RCAR_GP_PIN(4, 11), PUPR3, 23 }, /* ETH_TXD1 */
{ RCAR_GP_PIN(4, 12), PUPR3, 24 }, /* ETH_CRS_DV */
{ RCAR_GP_PIN(4, 13), PUPR3, 25 }, /* ETH_TX_EN */
{ RCAR_GP_PIN(4, 14), PUPR3, 26 }, /* ETH_RX_ER */
{ RCAR_GP_PIN(4, 15), PUPR3, 27 }, /* ETH_RXD0 */
{ RCAR_GP_PIN(4, 16), PUPR3, 28 }, /* ETH_RXD1 */
{ RCAR_GP_PIN(4, 17), PUPR3, 29 }, /* ETH_MDC */
{ RCAR_GP_PIN(4, 18), PUPR3, 30 }, /* ETH_MDIO */
{ RCAR_GP_PIN(4, 19), PUPR3, 31 }, /* ETH_LINK */
{ RCAR_GP_PIN(3, 6), PUPR4, 0 }, /* SSI_SCK012 */
{ RCAR_GP_PIN(3, 7), PUPR4, 1 }, /* SSI_WS012 */
{ RCAR_GP_PIN(3, 10), PUPR4, 2 }, /* SSI_SDATA0 */
{ RCAR_GP_PIN(3, 9), PUPR4, 3 }, /* SSI_SDATA1 */
{ RCAR_GP_PIN(3, 8), PUPR4, 4 }, /* SSI_SDATA2 */
{ RCAR_GP_PIN(3, 2), PUPR4, 5 }, /* SSI_SCK34 */
{ RCAR_GP_PIN(3, 3), PUPR4, 6 }, /* SSI_WS34 */
{ RCAR_GP_PIN(3, 5), PUPR4, 7 }, /* SSI_SDATA3 */
{ RCAR_GP_PIN(3, 4), PUPR4, 8 }, /* SSI_SDATA4 */
{ RCAR_GP_PIN(2, 31), PUPR4, 9 }, /* SSI_SCK5 */
{ RCAR_GP_PIN(3, 0), PUPR4, 10 }, /* SSI_WS5 */
{ RCAR_GP_PIN(3, 1), PUPR4, 11 }, /* SSI_SDATA5 */
{ RCAR_GP_PIN(2, 28), PUPR4, 12 }, /* SSI_SCK6 */
{ RCAR_GP_PIN(2, 29), PUPR4, 13 }, /* SSI_WS6 */
{ RCAR_GP_PIN(2, 30), PUPR4, 14 }, /* SSI_SDATA6 */
{ RCAR_GP_PIN(2, 24), PUPR4, 15 }, /* SSI_SCK78 */
{ RCAR_GP_PIN(2, 25), PUPR4, 16 }, /* SSI_WS78 */
{ RCAR_GP_PIN(2, 27), PUPR4, 17 }, /* SSI_SDATA7 */
{ RCAR_GP_PIN(2, 26), PUPR4, 18 }, /* SSI_SDATA8 */
{ RCAR_GP_PIN(3, 23), PUPR4, 19 }, /* TCLK0 */
{ RCAR_GP_PIN(3, 11), PUPR4, 20 }, /* SD0_CLK */
{ RCAR_GP_PIN(3, 12), PUPR4, 21 }, /* SD0_CMD */
{ RCAR_GP_PIN(3, 13), PUPR4, 22 }, /* SD0_DAT0 */
{ RCAR_GP_PIN(3, 14), PUPR4, 23 }, /* SD0_DAT1 */
{ RCAR_GP_PIN(3, 15), PUPR4, 24 }, /* SD0_DAT2 */
{ RCAR_GP_PIN(3, 16), PUPR4, 25 }, /* SD0_DAT3 */
{ RCAR_GP_PIN(3, 17), PUPR4, 26 }, /* SD0_CD */
{ RCAR_GP_PIN(3, 18), PUPR4, 27 }, /* SD0_WP */
{ RCAR_GP_PIN(2, 22), PUPR4, 28 }, /* AUDIO_CLKA */
{ RCAR_GP_PIN(2, 23), PUPR4, 29 }, /* AUDIO_CLKB */
{ RCAR_GP_PIN(1, 14), PUPR4, 30 }, /* IRQ2 */
{ RCAR_GP_PIN(1, 15), PUPR4, 31 }, /* IRQ3 */
{ RCAR_GP_PIN(0, 1), PUPR5, 0 }, /* PENC0 */
{ RCAR_GP_PIN(0, 2), PUPR5, 1 }, /* PENC1 */
{ RCAR_GP_PIN(0, 3), PUPR5, 2 }, /* USB_OVC0 */
{ RCAR_GP_PIN(0, 4), PUPR5, 3 }, /* USB_OVC1 */
{ RCAR_GP_PIN(1, 16), PUPR5, 4 }, /* SCIF_CLK */
{ RCAR_GP_PIN(1, 17), PUPR5, 5 }, /* TX0 */
{ RCAR_GP_PIN(1, 18), PUPR5, 6 }, /* RX0 */
{ RCAR_GP_PIN(1, 19), PUPR5, 7 }, /* SCK0 */
{ RCAR_GP_PIN(1, 20), PUPR5, 8 }, /* /CTS0 */
{ RCAR_GP_PIN(1, 21), PUPR5, 9 }, /* /RTS0 */
{ RCAR_GP_PIN(3, 19), PUPR5, 10 }, /* HSPI_CLK0 */
{ RCAR_GP_PIN(3, 20), PUPR5, 11 }, /* /HSPI_CS0 */
{ RCAR_GP_PIN(3, 21), PUPR5, 12 }, /* HSPI_RX0 */
{ RCAR_GP_PIN(3, 22), PUPR5, 13 }, /* HSPI_TX0 */
{ RCAR_GP_PIN(4, 20), PUPR5, 14 }, /* ETH_MAGIC */
{ RCAR_GP_PIN(4, 25), PUPR5, 15 }, /* AVS1 */
{ RCAR_GP_PIN(4, 26), PUPR5, 16 }, /* AVS2 */
};
static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc,
unsigned int pin)
{
const struct sh_pfc_bias_info *info;
void __iomem *addr;
if (WARN_ON_ONCE(!pullups[pin].reg))
info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
if (!info)
return PIN_CONFIG_BIAS_DISABLE;
addr = pfc->windows->virt + pullups[pin].reg;
addr = pfc->windows->virt + info->reg;
if (ioread32(addr) & BIT(pullups[pin].bit))
if (ioread32(addr) & BIT(info->bit))
return PIN_CONFIG_BIAS_PULL_UP;
else
return PIN_CONFIG_BIAS_DISABLE;
......@@ -3103,15 +3103,17 @@ static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc,
static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
unsigned int bias)
{
const struct sh_pfc_bias_info *info;
void __iomem *addr;
u32 value;
u32 bit;
if (WARN_ON_ONCE(!pullups[pin].reg))
info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
if (!info)
return;
addr = pfc->windows->virt + pullups[pin].reg;
bit = BIT(pullups[pin].bit);
addr = pfc->windows->virt + info->reg;
bit = BIT(info->bit);
value = ioread32(addr) & ~bit;
if (bias == PIN_CONFIG_BIAS_PULL_UP)
......
drivers/pinctrl/sh-pfc/pfc-r8a7795.c
View file @ d278dae8
......@@ -523,6 +523,22 @@ MOD_SEL0_2_1 MOD_SEL1_2 \
MOD_SEL1_1 \
MOD_SEL1_0 MOD_SEL2_0
/*
* These pins are not able to be muxed but have other properties
* that can be set, such as drive-strength or pull-up/pull-down enable.
*/
#define PINMUX_STATIC \
FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
FM(QSPI0_IO2) FM(QSPI0_IO3) \
FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
FM(QSPI1_IO2) FM(QSPI1_IO3) \
FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
FM(CLKOUT) FM(PRESETOUT) \
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF)
enum {
PINMUX_RESERVED = 0,
......@@ -548,6 +564,7 @@ enum {
PINMUX_GPSR
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_STATIC
PINMUX_MARK_END,
#undef F_
#undef FM
......@@ -1412,10 +1429,78 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3),
/*
* Static pins can not be muxed between different functions but
* still needs a mark entry in the pinmux list. Add each static
* pin to the list without an associated function. The sh-pfc
* core will do the right thing and skip trying to mux then pin
* while still applying configuration to it
*/
#define FM(x) PINMUX_DATA(x##_MARK, 0),
PINMUX_STATIC
#undef FM
};
/*
* R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs.
* Physical layout rows: A - AW, cols: 1 - 39.
*/
#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
/*
* Pins not associated with a GPIO port.
*
* The pin positions are different between different r8a7795
* packages, all that is needed for the pfc driver is a unique
* number for each pin. To this end use the pin layout from
* R-Car H3SiP to calculate a unique number for each pin.
*/
SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
};
/* - AUDIO CLOCK ------------------------------------------------------------ */
......@@ -1563,11 +1648,33 @@ static const unsigned int avb_phy_int_mux[] = {
AVB_PHY_INT_MARK,
};
static const unsigned int avb_mdc_pins[] = {
/* AVB_MDC */
RCAR_GP_PIN(2, 9),
/* AVB_MDC, AVB_MDIO */
RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
};
static const unsigned int avb_mdc_mux[] = {
AVB_MDC_MARK,
AVB_MDC_MARK, AVB_MDIO_MARK,
};
static const unsigned int avb_mii_pins[] = {
/*
* AVB_TX_CTL, AVB_TXC, AVB_TD0,
* AVB_TD1, AVB_TD2, AVB_TD3,
* AVB_RX_CTL, AVB_RXC, AVB_RD0,
* AVB_RD1, AVB_RD2, AVB_RD3,
* AVB_TXCREFCLK
*/
PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
PIN_NUMBER('A', 12),
};
static const unsigned int avb_mii_mux[] = {
AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
AVB_TXCREFCLK_MARK,
};
static const unsigned int avb_avtp_pps_pins[] = {
/* AVB_AVTP_PPS */
......@@ -3613,6 +3720,55 @@ static const unsigned int usb2_mux[] = {
USB2_PWEN_MARK, USB2_OVC_MARK,
};
/* - QSPI0 ------------------------------------------------------------------ */
static const unsigned int qspi0_ctrl_pins[] = {
/* QSPI0_SPCLK, QSPI0_SSL */
PIN_NUMBER('W', 3), PIN_NUMBER('Y', 3),
};
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data2_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4),
};
static const unsigned int qspi0_data2_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
};
static const unsigned int qspi0_data4_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4),
PIN_NUMBER('Y', 6), PIN_A_NUMBER('B', 6),
};
static const unsigned int qspi0_data4_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
};
/* - QSPI1 ------------------------------------------------------------------ */
static const unsigned int qspi1_ctrl_pins[] = {
/* QSPI1_SPCLK, QSPI1_SSL */
PIN_NUMBER('V', 3), PIN_NUMBER('V', 5),
};
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data2_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5),
};
static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
};
static const unsigned int qspi1_data4_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5),
PIN_A_NUMBER('E', 4), PIN_A_NUMBER('C', 3),
};
static const unsigned int qspi1_data4_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
SH_PFC_PIN_GROUP(audio_clk_a_b),
......@@ -3635,6 +3791,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb_magic),
SH_PFC_PIN_GROUP(avb_phy_int),
SH_PFC_PIN_GROUP(avb_mdc),
SH_PFC_PIN_GROUP(avb_mii),
SH_PFC_PIN_GROUP(avb_avtp_pps),
SH_PFC_PIN_GROUP(avb_avtp_match_a),
SH_PFC_PIN_GROUP(avb_avtp_capture_a),
......@@ -3912,6 +4069,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb2),
SH_PFC_PIN_GROUP(qspi0_ctrl),
SH_PFC_PIN_GROUP(qspi0_data2),
SH_PFC_PIN_GROUP(qspi0_data4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP(qspi1_data2),
SH_PFC_PIN_GROUP(qspi1_data4),
};
static const char * const audio_clk_groups[] = {
......@@ -3939,6 +4102,7 @@ static const char * const avb_groups[] = {
"avb_magic",
"avb_phy_int",
"avb_mdc",
"avb_mii",
"avb_avtp_pps",
"avb_avtp_match_a",
"avb_avtp_capture_a",
......@@ -4356,6 +4520,18 @@ static const char * const usb2_groups[] = {
"usb2",
};
static const char * const qspi0_groups[] = {
"qspi0_ctrl",
"qspi0_data2",
"qspi0_data4",
};
static const char * const qspi1_groups[] = {
"qspi1_ctrl",
"qspi1_data2",
"qspi1_data4",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb),
......@@ -4405,6 +4581,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb2),
SH_PFC_FUNCTION(qspi0),
SH_PFC_FUNCTION(qspi1),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
......@@ -4962,10 +5140,45 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
{ PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
{ PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
{ PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
{ PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
{ PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
{ PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
{ PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
{ PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
{ PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
{ PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
{ PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
{ PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
{ PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
{ PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
{ PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
{ PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
} },
{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
{ PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
{ PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
{ PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
{ PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
{ PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
{ PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
{ PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
{ PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
{ PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
{ PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
{ PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
{ PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
{ PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
} },
{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
{ RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
......@@ -5008,6 +5221,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
{ PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */
{ RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
{ RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
{ RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
......@@ -5018,6 +5232,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
} },
{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
{ RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
{ PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
{ RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
{ RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
{ RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
......@@ -5036,20 +5251,30 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
{ PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
{ PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
{ PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
{ PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
} },
{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
{ PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
{ PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
{ RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
......@@ -5118,6 +5343,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
{ RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
{ RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
{ PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
{ RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
......@@ -5188,206 +5414,206 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
#define PU5 0x14
#define PU6 0x18
static const struct {
u16 reg : 11;
u16 bit : 5;
} pullups[] = {
[RCAR_GP_PIN(2, 11)] = { PU0, 31 }, /* AVB_PHY_INT */
[RCAR_GP_PIN(2, 10)] = { PU0, 30 }, /* AVB_MAGIC */
[RCAR_GP_PIN(2, 9)] = { PU0, 29 }, /* AVB_MDC */
[RCAR_GP_PIN(1, 19)] = { PU1, 31 }, /* A19 */
[RCAR_GP_PIN(1, 18)] = { PU1, 30 }, /* A18 */
[RCAR_GP_PIN(1, 17)] = { PU1, 29 }, /* A17 */
[RCAR_GP_PIN(1, 16)] = { PU1, 28 }, /* A16 */
[RCAR_GP_PIN(1, 15)] = { PU1, 27 }, /* A15 */
[RCAR_GP_PIN(1, 14)] = { PU1, 26 }, /* A14 */
[RCAR_GP_PIN(1, 13)] = { PU1, 25 }, /* A13 */
[RCAR_GP_PIN(1, 12)] = { PU1, 24 }, /* A12 */
[RCAR_GP_PIN(1, 11)] = { PU1, 23 }, /* A11 */
[RCAR_GP_PIN(1, 10)] = { PU1, 22 }, /* A10 */
[RCAR_GP_PIN(1, 9)] = { PU1, 21 }, /* A9 */
[RCAR_GP_PIN(1, 8)] = { PU1, 20 }, /* A8 */
[RCAR_GP_PIN(1, 7)] = { PU1, 19 }, /* A7 */
[RCAR_GP_PIN(1, 6)] = { PU1, 18 }, /* A6 */
[RCAR_GP_PIN(1, 5)] = { PU1, 17 }, /* A5 */
[RCAR_GP_PIN(1, 4)] = { PU1, 16 }, /* A4 */
[RCAR_GP_PIN(1, 3)] = { PU1, 15 }, /* A3 */
[RCAR_GP_PIN(1, 2)] = { PU1, 14 }, /* A2 */
[RCAR_GP_PIN(1, 1)] = { PU1, 13 }, /* A1 */
[RCAR_GP_PIN(1, 0)] = { PU1, 12 }, /* A0 */
[RCAR_GP_PIN(2, 8)] = { PU1, 11 }, /* PWM2_A */
[RCAR_GP_PIN(2, 7)] = { PU1, 10 }, /* PWM1_A */
[RCAR_GP_PIN(2, 6)] = { PU1, 9 }, /* PWM0 */
[RCAR_GP_PIN(2, 5)] = { PU1, 8 }, /* IRQ5 */
[RCAR_GP_PIN(2, 4)] = { PU1, 7 }, /* IRQ4 */
[RCAR_GP_PIN(2, 3)] = { PU1, 6 }, /* IRQ3 */
[RCAR_GP_PIN(2, 2)] = { PU1, 5 }, /* IRQ2 */
[RCAR_GP_PIN(2, 1)] = { PU1, 4 }, /* IRQ1 */
[RCAR_GP_PIN(2, 0)] = { PU1, 3 }, /* IRQ0 */
[RCAR_GP_PIN(2, 14)] = { PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
[RCAR_GP_PIN(2, 13)] = { PU1, 1 }, /* AVB_AVTP_MATCH_A */
[RCAR_GP_PIN(2, 12)] = { PU1, 0 }, /* AVB_LINK */
[RCAR_GP_PIN(7, 3)] = { PU2, 29 }, /* HDMI1_CEC */
[RCAR_GP_PIN(7, 2)] = { PU2, 28 }, /* HDMI0_CEC */
[RCAR_GP_PIN(7, 1)] = { PU2, 27 }, /* AVS2 */
[RCAR_GP_PIN(7, 0)] = { PU2, 26 }, /* AVS1 */
[RCAR_GP_PIN(0, 15)] = { PU2, 25 }, /* D15 */
[RCAR_GP_PIN(0, 14)] = { PU2, 24 }, /* D14 */
[RCAR_GP_PIN(0, 13)] = { PU2, 23 }, /* D13 */
[RCAR_GP_PIN(0, 12)] = { PU2, 22 }, /* D12 */
[RCAR_GP_PIN(0, 11)] = { PU2, 21 }, /* D11 */
[RCAR_GP_PIN(0, 10)] = { PU2, 20 }, /* D10 */
[RCAR_GP_PIN(0, 9)] = { PU2, 19 }, /* D9 */
[RCAR_GP_PIN(0, 8)] = { PU2, 18 }, /* D8 */
[RCAR_GP_PIN(0, 7)] = { PU2, 17 }, /* D7 */
[RCAR_GP_PIN(0, 6)] = { PU2, 16 }, /* D6 */
[RCAR_GP_PIN(0, 5)] = { PU2, 15 }, /* D5 */
[RCAR_GP_PIN(0, 4)] = { PU2, 14 }, /* D4 */
[RCAR_GP_PIN(0, 3)] = { PU2, 13 }, /* D3 */
[RCAR_GP_PIN(0, 2)] = { PU2, 12 }, /* D2 */
[RCAR_GP_PIN(0, 1)] = { PU2, 11 }, /* D1 */
[RCAR_GP_PIN(0, 0)] = { PU2, 10 }, /* D0 */
[RCAR_GP_PIN(1, 27)] = { PU2, 8 }, /* EX_WAIT0_A */
[RCAR_GP_PIN(1, 26)] = { PU2, 7 }, /* WE1_N */
[RCAR_GP_PIN(1, 25)] = { PU2, 6 }, /* WE0_N */
[RCAR_GP_PIN(1, 24)] = { PU2, 5 }, /* RD_WR_N */
[RCAR_GP_PIN(1, 23)] = { PU2, 4 }, /* RD_N */
[RCAR_GP_PIN(1, 22)] = { PU2, 3 }, /* BS_N */
[RCAR_GP_PIN(1, 21)] = { PU2, 2 }, /* CS1_N_A26 */
[RCAR_GP_PIN(1, 20)] = { PU2, 1 }, /* CS0_N */
[RCAR_GP_PIN(4, 9)] = { PU3, 31 }, /* SD3_DAT0 */
[RCAR_GP_PIN(4, 8)] = { PU3, 30 }, /* SD3_CMD */
[RCAR_GP_PIN(4, 7)] = { PU3, 29 }, /* SD3_CLK */
[RCAR_GP_PIN(4, 6)] = { PU3, 28 }, /* SD2_DS */
[RCAR_GP_PIN(4, 5)] = { PU3, 27 }, /* SD2_DAT3 */
[RCAR_GP_PIN(4, 4)] = { PU3, 26 }, /* SD2_DAT2 */
[RCAR_GP_PIN(4, 3)] = { PU3, 25 }, /* SD2_DAT1 */
[RCAR_GP_PIN(4, 2)] = { PU3, 24 }, /* SD2_DAT0 */
[RCAR_GP_PIN(4, 1)] = { PU3, 23 }, /* SD2_CMD */
[RCAR_GP_PIN(4, 0)] = { PU3, 22 }, /* SD2_CLK */
[RCAR_GP_PIN(3, 11)] = { PU3, 21 }, /* SD1_DAT3 */
[RCAR_GP_PIN(3, 10)] = { PU3, 20 }, /* SD1_DAT2 */
[RCAR_GP_PIN(3, 9)] = { PU3, 19 }, /* SD1_DAT1 */
[RCAR_GP_PIN(3, 8)] = { PU3, 18 }, /* SD1_DAT0 */
[RCAR_GP_PIN(3, 7)] = { PU3, 17 }, /* SD1_CMD */
[RCAR_GP_PIN(3, 6)] = { PU3, 16 }, /* SD1_CLK */
[RCAR_GP_PIN(3, 5)] = { PU3, 15 }, /* SD0_DAT3 */
[RCAR_GP_PIN(3, 4)] = { PU3, 14 }, /* SD0_DAT2 */
[RCAR_GP_PIN(3, 3)] = { PU3, 13 }, /* SD0_DAT1 */
[RCAR_GP_PIN(3, 2)] = { PU3, 12 }, /* SD0_DAT0 */
[RCAR_GP_PIN(3, 1)] = { PU3, 11 }, /* SD0_CMD */
[RCAR_GP_PIN(3, 0)] = { PU3, 10 }, /* SD0_CLK */
[RCAR_GP_PIN(5, 19)] = { PU4, 31 }, /* MSIOF0_SS1 */
[RCAR_GP_PIN(5, 18)] = { PU4, 30 }, /* MSIOF0_SYNC */
[RCAR_GP_PIN(5, 17)] = { PU4, 29 }, /* MSIOF0_SCK */
[RCAR_GP_PIN(5, 16)] = { PU4, 28 }, /* HRTS0_N */
[RCAR_GP_PIN(5, 15)] = { PU4, 27 }, /* HCTS0_N */
[RCAR_GP_PIN(5, 14)] = { PU4, 26 }, /* HTX0 */
[RCAR_GP_PIN(5, 13)] = { PU4, 25 }, /* HRX0 */
[RCAR_GP_PIN(5, 12)] = { PU4, 24 }, /* HSCK0 */
[RCAR_GP_PIN(5, 11)] = { PU4, 23 }, /* RX2_A */
[RCAR_GP_PIN(5, 10)] = { PU4, 22 }, /* TX2_A */
[RCAR_GP_PIN(5, 9)] = { PU4, 21 }, /* SCK2 */
[RCAR_GP_PIN(5, 8)] = { PU4, 20 }, /* RTS1_N_TANS */
[RCAR_GP_PIN(5, 7)] = { PU4, 19 }, /* CTS1_N */
[RCAR_GP_PIN(5, 6)] = { PU4, 18 }, /* TX1_A */
[RCAR_GP_PIN(5, 5)] = { PU4, 17 }, /* RX1_A */
[RCAR_GP_PIN(5, 4)] = { PU4, 16 }, /* RTS0_N_TANS */
[RCAR_GP_PIN(5, 3)] = { PU4, 15 }, /* CTS0_N */
[RCAR_GP_PIN(5, 2)] = { PU4, 14 }, /* TX0 */
[RCAR_GP_PIN(5, 1)] = { PU4, 13 }, /* RX0 */
[RCAR_GP_PIN(5, 0)] = { PU4, 12 }, /* SCK0 */
[RCAR_GP_PIN(3, 15)] = { PU4, 11 }, /* SD1_WP */
[RCAR_GP_PIN(3, 14)] = { PU4, 10 }, /* SD1_CD */
[RCAR_GP_PIN(3, 13)] = { PU4, 9 }, /* SD0_WP */
[RCAR_GP_PIN(3, 12)] = { PU4, 8 }, /* SD0_CD */
[RCAR_GP_PIN(4, 17)] = { PU4, 7 }, /* SD3_DS */
[RCAR_GP_PIN(4, 16)] = { PU4, 6 }, /* SD3_DAT7 */
[RCAR_GP_PIN(4, 15)] = { PU4, 5 }, /* SD3_DAT6 */
[RCAR_GP_PIN(4, 14)] = { PU4, 4 }, /* SD3_DAT5 */
[RCAR_GP_PIN(4, 13)] = { PU4, 3 }, /* SD3_DAT4 */
[RCAR_GP_PIN(4, 12)] = { PU4, 2 }, /* SD3_DAT3 */
[RCAR_GP_PIN(4, 11)] = { PU4, 1 }, /* SD3_DAT2 */
[RCAR_GP_PIN(4, 10)] = { PU4, 0 }, /* SD3_DAT1 */
[RCAR_GP_PIN(6, 24)] = { PU5, 31 }, /* USB0_PWEN */
[RCAR_GP_PIN(6, 23)] = { PU5, 30 }, /* AUDIO_CLKB_B */
[RCAR_GP_PIN(6, 22)] = { PU5, 29 }, /* AUDIO_CLKA_A */
[RCAR_GP_PIN(6, 21)] = { PU5, 28 }, /* SSI_SDATA9_A */
[RCAR_GP_PIN(6, 20)] = { PU5, 27 }, /* SSI_SDATA8 */
[RCAR_GP_PIN(6, 19)] = { PU5, 26 }, /* SSI_SDATA7 */
[RCAR_GP_PIN(6, 18)] = { PU5, 25 }, /* SSI_WS78 */
[RCAR_GP_PIN(6, 17)] = { PU5, 24 }, /* SSI_SCK78 */
[RCAR_GP_PIN(6, 16)] = { PU5, 23 }, /* SSI_SDATA6 */
[RCAR_GP_PIN(6, 15)] = { PU5, 22 }, /* SSI_WS6 */
[RCAR_GP_PIN(6, 14)] = { PU5, 21 }, /* SSI_SCK6 */
[RCAR_GP_PIN(6, 13)] = { PU5, 20 }, /* SSI_SDATA5 */
[RCAR_GP_PIN(6, 12)] = { PU5, 19 }, /* SSI_WS5 */
[RCAR_GP_PIN(6, 11)] = { PU5, 18 }, /* SSI_SCK5 */
[RCAR_GP_PIN(6, 10)] = { PU5, 17 }, /* SSI_SDATA4 */
[RCAR_GP_PIN(6, 9)] = { PU5, 16 }, /* SSI_WS4 */
[RCAR_GP_PIN(6, 8)] = { PU5, 15 }, /* SSI_SCK4 */
[RCAR_GP_PIN(6, 7)] = { PU5, 14 }, /* SSI_SDATA3 */
[RCAR_GP_PIN(6, 6)] = { PU5, 13 }, /* SSI_WS34 */
[RCAR_GP_PIN(6, 5)] = { PU5, 12 }, /* SSI_SCK34 */
[RCAR_GP_PIN(6, 4)] = { PU5, 11 }, /* SSI_SDATA2_A */
[RCAR_GP_PIN(6, 3)] = { PU5, 10 }, /* SSI_SDATA1_A */
[RCAR_GP_PIN(6, 2)] = { PU5, 9 }, /* SSI_SDATA0 */
[RCAR_GP_PIN(6, 1)] = { PU5, 8 }, /* SSI_WS01239 */
[RCAR_GP_PIN(6, 0)] = { PU5, 7 }, /* SSI_SCK01239 */
[RCAR_GP_PIN(5, 25)] = { PU5, 5 }, /* MLB_DAT */
[RCAR_GP_PIN(5, 24)] = { PU5, 4 }, /* MLB_SIG */
[RCAR_GP_PIN(5, 23)] = { PU5, 3 }, /* MLB_CLK */
[RCAR_GP_PIN(5, 22)] = { PU5, 2 }, /* MSIOF0_RXD */
[RCAR_GP_PIN(5, 21)] = { PU5, 1 }, /* MSIOF0_SS2 */
[RCAR_GP_PIN(5, 20)] = { PU5, 0 }, /* MSIOF0_TXD */
[RCAR_GP_PIN(6, 31)] = { PU6, 6 }, /* USB31_OVC */
[RCAR_GP_PIN(6, 30)] = { PU6, 5 }, /* USB31_PWEN */
[RCAR_GP_PIN(6, 29)] = { PU6, 4 }, /* USB30_OVC */
[RCAR_GP_PIN(6, 28)] = { PU6, 3 }, /* USB30_PWEN */
[RCAR_GP_PIN(6, 27)] = { PU6, 2 }, /* USB1_OVC */
[RCAR_GP_PIN(6, 26)] = { PU6, 1 }, /* USB1_PWEN */
[RCAR_GP_PIN(6, 25)] = { PU6, 0 }, /* USB0_OVC */
static const struct sh_pfc_bias_info bias_info[] = {
{ RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
{ RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
{ RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
{ RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
{ RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
{ RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
{ RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
{ RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
{ RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
{ RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
{ RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
{ RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
{ RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
{ RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
{ RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
{ RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
{ RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
{ RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
{ RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
{ RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
{ RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
{ RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
{ RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
{ RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
{ RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
{ RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
{ RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
{ RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
{ RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
{ RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
{ RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
{ RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
{ RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
{ RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
{ RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
{ RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
{ RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
{ RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
{ RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
{ RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
{ RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
{ RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
{ RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
{ RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
{ RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
{ RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
{ RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
{ RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
{ RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
{ RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
{ RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
{ RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
{ RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
{ RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
{ RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
{ RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
{ RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
{ RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
{ RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
{ RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
{ RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
{ RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
{ RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
{ RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
{ RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
{ RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
{ RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
{ RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
{ RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
{ RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
{ RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
{ RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
{ RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
{ RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
{ RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
{ RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
{ RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
{ RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
{ RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
{ RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
{ RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
{ RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
{ RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
{ RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
{ RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
{ RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
{ RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
{ RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
{ RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
{ RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
{ RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
{ RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
{ RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
{ RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
{ RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
{ RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
{ RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
{ RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
{ RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
{ RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
{ RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
{ RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
{ RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
{ RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
{ RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
{ RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
{ RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
{ RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
{ RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
{ RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
{ RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
{ RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
{ RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
{ RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
{ RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
{ RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
{ RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
{ RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
{ RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
{ RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
{ RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
{ RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
{ RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
{ RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
{ RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
{ RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
{ RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
{ RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
{ RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
{ RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
{ RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
{ RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
{ RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
{ RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
{ RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
{ RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */
{ RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */
{ RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
{ RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
{ RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
{ RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
{ RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
{ RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
{ RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
{ RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
{ RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
{ RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
{ RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
{ RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */
{ RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */
{ RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
{ RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
{ RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
{ RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
{ RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
};
static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
unsigned int pin)
{
const struct sh_pfc_bias_info *info;
u32 reg;
u32 bit;
if (WARN_ON_ONCE(!pullups[pin].reg))
info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
if (!info)
return PIN_CONFIG_BIAS_DISABLE;
reg = pullups[pin].reg;
bit = BIT(pullups[pin].bit);
reg = info->reg;
bit = BIT(info->bit);
if (sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit) {
if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
return PIN_CONFIG_BIAS_PULL_UP;
else
return PIN_CONFIG_BIAS_PULL_DOWN;
} else
if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
return PIN_CONFIG_BIAS_DISABLE;
else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
return PIN_CONFIG_BIAS_PULL_UP;
else
return PIN_CONFIG_BIAS_PULL_DOWN;
}
static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
unsigned int bias)
{
const struct sh_pfc_bias_info *info;
u32 enable, updown;
u32 reg;
u32 bit;
if (WARN_ON_ONCE(!pullups[pin].reg))
info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
if (!info)
return;
reg = pullups[pin].reg;
bit = BIT(pullups[pin].bit);
reg = info->reg;
bit = BIT(info->bit);
enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
if (bias != PIN_CONFIG_BIAS_DISABLE)
......
drivers/pinctrl/sh-pfc/pfc-r8a7796.c
View file @ d278dae8
......@@ -1490,6 +1490,71 @@ static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
};
/* - EtherAVB --------------------------------------------------------------- */
static const unsigned int avb_link_pins[] = {
/* AVB_LINK */
RCAR_GP_PIN(2, 12),
};
static const unsigned int avb_link_mux[] = {
AVB_LINK_MARK,
};
static const unsigned int avb_magic_pins[] = {
/* AVB_MAGIC_ */
RCAR_GP_PIN(2, 10),
};
static const unsigned int avb_magic_mux[] = {
AVB_MAGIC_MARK,
};
static const unsigned int avb_phy_int_pins[] = {
/* AVB_PHY_INT */
RCAR_GP_PIN(2, 11),
};
static const unsigned int avb_phy_int_mux[] = {
AVB_PHY_INT_MARK,
};
static const unsigned int avb_mdc_pins[] = {
/* AVB_MDC */
RCAR_GP_PIN(2, 9),
};
static const unsigned int avb_mdc_mux[] = {
AVB_MDC_MARK,
};
static const unsigned int avb_avtp_pps_pins[] = {
/* AVB_AVTP_PPS */
RCAR_GP_PIN(2, 6),
};
static const unsigned int avb_avtp_pps_mux[] = {
AVB_AVTP_PPS_MARK,
};
static const unsigned int avb_avtp_match_a_pins[] = {
/* AVB_AVTP_MATCH_A */
RCAR_GP_PIN(2, 13),
};
static const unsigned int avb_avtp_match_a_mux[] = {
AVB_AVTP_MATCH_A_MARK,
};
static const unsigned int avb_avtp_capture_a_pins[] = {
/* AVB_AVTP_CAPTURE_A */
RCAR_GP_PIN(2, 14),
};
static const unsigned int avb_avtp_capture_a_mux[] = {
AVB_AVTP_CAPTURE_A_MARK,
};
static const unsigned int avb_avtp_match_b_pins[] = {
/* AVB_AVTP_MATCH_B */
RCAR_GP_PIN(1, 8),
};
static const unsigned int avb_avtp_match_b_mux[] = {
AVB_AVTP_MATCH_B_MARK,
};
static const unsigned int avb_avtp_capture_b_pins[] = {
/* AVB_AVTP_CAPTURE_B */
RCAR_GP_PIN(1, 11),
};
static const unsigned int avb_avtp_capture_b_mux[] = {
AVB_AVTP_CAPTURE_B_MARK,
};
/* - DRIF0 --------------------------------------------------------------- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
......@@ -1705,6 +1770,87 @@ static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
/* - DU --------------------------------------------------------------------- */
static const unsigned int du_rgb666_pins[] = {
/* R[7:2], G[7:2], B[7:2] */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
};
static const unsigned int du_rgb666_mux[] = {
DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
DU_DR3_MARK, DU_DR2_MARK,
DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
DU_DG3_MARK, DU_DG2_MARK,
DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
DU_DB3_MARK, DU_DB2_MARK,
};
static const unsigned int du_rgb888_pins[] = {
/* R[7:0], G[7:0], B[7:0] */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
};
static const unsigned int du_rgb888_mux[] = {
DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
};
static const unsigned int du_clk_out_0_pins[] = {
/* CLKOUT */
RCAR_GP_PIN(1, 27),
};
static const unsigned int du_clk_out_0_mux[] = {
DU_DOTCLKOUT0_MARK
};
static const unsigned int du_clk_out_1_pins[] = {
/* CLKOUT */
RCAR_GP_PIN(2, 3),
};
static const unsigned int du_clk_out_1_mux[] = {
DU_DOTCLKOUT1_MARK
};
static const unsigned int du_sync_pins[] = {
/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
};
static const unsigned int du_sync_mux[] = {
DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
};
static const unsigned int du_oddf_pins[] = {
/* EXDISP/EXODDF/EXCDE */
RCAR_GP_PIN(2, 2),
};
static const unsigned int du_oddf_mux[] = {
DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
};
static const unsigned int du_cde_pins[] = {
/* CDE */
RCAR_GP_PIN(2, 0),
};
static const unsigned int du_cde_mux[] = {
DU_CDE_MARK,
};
static const unsigned int du_disp_pins[] = {
/* DISP */
RCAR_GP_PIN(2, 1),
};
static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
};
/* - I2C -------------------------------------------------------------------- */
static const unsigned int i2c1_a_pins[] = {
/* SDA, SCL */
......@@ -2178,6 +2324,15 @@ static const unsigned int sdhi3_ds_mux[] = {
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb_link),
SH_PFC_PIN_GROUP(avb_magic),
SH_PFC_PIN_GROUP(avb_phy_int),
SH_PFC_PIN_GROUP(avb_mdc),
SH_PFC_PIN_GROUP(avb_avtp_pps),
SH_PFC_PIN_GROUP(avb_avtp_match_a),
SH_PFC_PIN_GROUP(avb_avtp_capture_a),
SH_PFC_PIN_GROUP(avb_avtp_match_b),
SH_PFC_PIN_GROUP(avb_avtp_capture_b),
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
SH_PFC_PIN_GROUP(drif0_data1_a),
......@@ -2208,6 +2363,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(drif3_ctrl_b),
SH_PFC_PIN_GROUP(drif3_data0_b),
SH_PFC_PIN_GROUP(drif3_data1_b),
SH_PFC_PIN_GROUP(du_rgb666),
SH_PFC_PIN_GROUP(du_rgb888),
SH_PFC_PIN_GROUP(du_clk_out_0),
SH_PFC_PIN_GROUP(du_clk_out_1),
SH_PFC_PIN_GROUP(du_sync),
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
SH_PFC_PIN_GROUP(i2c1_a),
SH_PFC_PIN_GROUP(i2c1_b),
SH_PFC_PIN_GROUP(i2c2_a),
......@@ -2272,6 +2435,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(sdhi3_ds),
};
static const char * const avb_groups[] = {
"avb_link",
"avb_magic",
"avb_phy_int",
"avb_mdc",
"avb_avtp_pps",
"avb_avtp_match_a",
"avb_avtp_capture_a",
"avb_avtp_match_b",
"avb_avtp_capture_b",
};
static const char * const drif0_groups[] = {
"drif0_ctrl_a",
"drif0_data0_a",
......@@ -2314,6 +2489,17 @@ static const char * const drif3_groups[] = {
"drif3_data1_b",
};
static const char * const du_groups[] = {
"du_rgb666",
"du_rgb888",
"du_clk_out_0",
"du_clk_out_1",
"du_sync",
"du_oddf",
"du_cde",
"du_disp",
};
static const char * const i2c1_groups[] = {
"i2c1_a",
"i2c1_b",
......@@ -2419,10 +2605,12 @@ static const char * const sdhi3_groups[] = {
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(avb),
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c6),
......
drivers/pinctrl/sh-pfc/pinctrl.c
View file @ d278dae8
......@@ -570,7 +570,8 @@ static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
return true;
return pin->configs &
(SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
case PIN_CONFIG_BIAS_PULL_UP:
return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
......
drivers/pinctrl/sh-pfc/sh_pfc.h
View file @ d278dae8
......@@ -189,6 +189,12 @@ struct sh_pfc_window {
unsigned long size;
};
struct sh_pfc_bias_info {
u16 pin;
u16 reg : 11;
u16 bit : 5;
};
struct sh_pfc_pin_range;
struct sh_pfc {
......@@ -540,6 +546,14 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
.configs = SH_PFC_PIN_CFG_NO_GPIO, \
}
/* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */
#define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \
{ \
.pin = PIN_NUMBER(row, col), \
.name = __stringify(PIN_##_name), \
.configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \
}
/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
* PORT_name_OUT, PORT_name_IN marks
*/
......
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