Skip to content

L
linux
Commit d2996831 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files
Options

drm/amdgpu: add SMUIO 11.0 register headers 

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3d220cc3
Hide whitespace changes
Inline Side-by-side
Showing with 1012 additions and 0 deletions
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h 0 → 100644
View file @ d2996831
/*
* Copyright (C) 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _smuio_11_0_0_OFFSET_HEADER
#define _smuio_11_0_0_OFFSET_HEADER
// addressBlock: smuio_smuio_SmuSmuioDec
// base address: 0x5a000
#define mmSMUSVI0_TEL_PLANE0 0x0004
#define mmSMUSVI0_TEL_PLANE0_BASE_IDX 0
#define mmSMUIO_MCM_CONFIG 0x0024
#define mmSMUIO_MCM_CONFIG_BASE_IDX 0
#define mmSMUIO_MP_RESET_INTR 0x00c1
#define mmSMUIO_MP_RESET_INTR_BASE_IDX 0
#define mmSMUIO_SOC_HALT 0x00c2
#define mmSMUIO_SOC_HALT_BASE_IDX 0
#define mmSMUIO_PWRMGT 0x00c8
#define mmSMUIO_PWRMGT_BASE_IDX 0
#define mmROM_CNTL 0x00e0
#define mmROM_CNTL_BASE_IDX 0
#define mmPAGE_MIRROR_CNTL 0x00e1
#define mmPAGE_MIRROR_CNTL_BASE_IDX 0
#define mmROM_STATUS 0x00e2
#define mmROM_STATUS_BASE_IDX 0
#define mmCGTT_ROM_CLK_CTRL0 0x00e3
#define mmCGTT_ROM_CLK_CTRL0_BASE_IDX 0
#define mmROM_INDEX 0x00e4
#define mmROM_INDEX_BASE_IDX 0
#define mmROM_DATA 0x00e5
#define mmROM_DATA_BASE_IDX 0
#define mmROM_START 0x00e6
#define mmROM_START_BASE_IDX 0
#define mmROM_SW_CNTL 0x00e7
#define mmROM_SW_CNTL_BASE_IDX 0
#define mmROM_SW_STATUS 0x00e8
#define mmROM_SW_STATUS_BASE_IDX 0
#define mmROM_SW_COMMAND 0x00e9
#define mmROM_SW_COMMAND_BASE_IDX 0
#define mmROM_SW_DATA_1 0x00ea
#define mmROM_SW_DATA_1_BASE_IDX 0
#define mmROM_SW_DATA_2 0x00eb
#define mmROM_SW_DATA_2_BASE_IDX 0
#define mmROM_SW_DATA_3 0x00ec
#define mmROM_SW_DATA_3_BASE_IDX 0
#define mmROM_SW_DATA_4 0x00ed
#define mmROM_SW_DATA_4_BASE_IDX 0
#define mmROM_SW_DATA_5 0x00ee
#define mmROM_SW_DATA_5_BASE_IDX 0
#define mmROM_SW_DATA_6 0x00ef
#define mmROM_SW_DATA_6_BASE_IDX 0
#define mmROM_SW_DATA_7 0x00f0
#define mmROM_SW_DATA_7_BASE_IDX 0
#define mmROM_SW_DATA_8 0x00f1
#define mmROM_SW_DATA_8_BASE_IDX 0
#define mmROM_SW_DATA_9 0x00f2
#define mmROM_SW_DATA_9_BASE_IDX 0
#define mmROM_SW_DATA_10 0x00f3
#define mmROM_SW_DATA_10_BASE_IDX 0
#define mmROM_SW_DATA_11 0x00f4
#define mmROM_SW_DATA_11_BASE_IDX 0
#define mmROM_SW_DATA_12 0x00f5
#define mmROM_SW_DATA_12_BASE_IDX 0
#define mmROM_SW_DATA_13 0x00f6
#define mmROM_SW_DATA_13_BASE_IDX 0
#define mmROM_SW_DATA_14 0x00f7
#define mmROM_SW_DATA_14_BASE_IDX 0
#define mmROM_SW_DATA_15 0x00f8
#define mmROM_SW_DATA_15_BASE_IDX 0
#define mmROM_SW_DATA_16 0x00f9
#define mmROM_SW_DATA_16_BASE_IDX 0
#define mmROM_SW_DATA_17 0x00fa
#define mmROM_SW_DATA_17_BASE_IDX 0
#define mmROM_SW_DATA_18 0x00fb
#define mmROM_SW_DATA_18_BASE_IDX 0
#define mmROM_SW_DATA_19 0x00fc
#define mmROM_SW_DATA_19_BASE_IDX 0
#define mmROM_SW_DATA_20 0x00fd
#define mmROM_SW_DATA_20_BASE_IDX 0
#define mmROM_SW_DATA_21 0x00fe
#define mmROM_SW_DATA_21_BASE_IDX 0
#define mmROM_SW_DATA_22 0x00ff
#define mmROM_SW_DATA_22_BASE_IDX 0
#define mmROM_SW_DATA_23 0x0100
#define mmROM_SW_DATA_23_BASE_IDX 0
#define mmROM_SW_DATA_24 0x0101
#define mmROM_SW_DATA_24_BASE_IDX 0
#define mmROM_SW_DATA_25 0x0102
#define mmROM_SW_DATA_25_BASE_IDX 0
#define mmROM_SW_DATA_26 0x0103
#define mmROM_SW_DATA_26_BASE_IDX 0
#define mmROM_SW_DATA_27 0x0104
#define mmROM_SW_DATA_27_BASE_IDX 0
#define mmROM_SW_DATA_28 0x0105
#define mmROM_SW_DATA_28_BASE_IDX 0
#define mmROM_SW_DATA_29 0x0106
#define mmROM_SW_DATA_29_BASE_IDX 0
#define mmROM_SW_DATA_30 0x0107
#define mmROM_SW_DATA_30_BASE_IDX 0
#define mmROM_SW_DATA_31 0x0108
#define mmROM_SW_DATA_31_BASE_IDX 0
#define mmROM_SW_DATA_32 0x0109
#define mmROM_SW_DATA_32_BASE_IDX 0
#define mmROM_SW_DATA_33 0x010a
#define mmROM_SW_DATA_33_BASE_IDX 0
#define mmROM_SW_DATA_34 0x010b
#define mmROM_SW_DATA_34_BASE_IDX 0
#define mmROM_SW_DATA_35 0x010c
#define mmROM_SW_DATA_35_BASE_IDX 0
#define mmROM_SW_DATA_36 0x010d
#define mmROM_SW_DATA_36_BASE_IDX 0
#define mmROM_SW_DATA_37 0x010e
#define mmROM_SW_DATA_37_BASE_IDX 0
#define mmROM_SW_DATA_38 0x010f
#define mmROM_SW_DATA_38_BASE_IDX 0
#define mmROM_SW_DATA_39 0x0110
#define mmROM_SW_DATA_39_BASE_IDX 0
#define mmROM_SW_DATA_40 0x0111
#define mmROM_SW_DATA_40_BASE_IDX 0
#define mmROM_SW_DATA_41 0x0112
#define mmROM_SW_DATA_41_BASE_IDX 0
#define mmROM_SW_DATA_42 0x0113
#define mmROM_SW_DATA_42_BASE_IDX 0
#define mmROM_SW_DATA_43 0x0114
#define mmROM_SW_DATA_43_BASE_IDX 0
#define mmROM_SW_DATA_44 0x0115
#define mmROM_SW_DATA_44_BASE_IDX 0
#define mmROM_SW_DATA_45 0x0116
#define mmROM_SW_DATA_45_BASE_IDX 0
#define mmROM_SW_DATA_46 0x0117
#define mmROM_SW_DATA_46_BASE_IDX 0
#define mmROM_SW_DATA_47 0x0118
#define mmROM_SW_DATA_47_BASE_IDX 0
#define mmROM_SW_DATA_48 0x0119
#define mmROM_SW_DATA_48_BASE_IDX 0
#define mmROM_SW_DATA_49 0x011a
#define mmROM_SW_DATA_49_BASE_IDX 0
#define mmROM_SW_DATA_50 0x011b
#define mmROM_SW_DATA_50_BASE_IDX 0
#define mmROM_SW_DATA_51 0x011c
#define mmROM_SW_DATA_51_BASE_IDX 0
#define mmROM_SW_DATA_52 0x011d
#define mmROM_SW_DATA_52_BASE_IDX 0
#define mmROM_SW_DATA_53 0x011e
#define mmROM_SW_DATA_53_BASE_IDX 0
#define mmROM_SW_DATA_54 0x011f
#define mmROM_SW_DATA_54_BASE_IDX 0
#define mmROM_SW_DATA_55 0x0120
#define mmROM_SW_DATA_55_BASE_IDX 0
#define mmROM_SW_DATA_56 0x0121
#define mmROM_SW_DATA_56_BASE_IDX 0
#define mmROM_SW_DATA_57 0x0122
#define mmROM_SW_DATA_57_BASE_IDX 0
#define mmROM_SW_DATA_58 0x0123
#define mmROM_SW_DATA_58_BASE_IDX 0
#define mmROM_SW_DATA_59 0x0124
#define mmROM_SW_DATA_59_BASE_IDX 0
#define mmROM_SW_DATA_60 0x0125
#define mmROM_SW_DATA_60_BASE_IDX 0
#define mmROM_SW_DATA_61 0x0126
#define mmROM_SW_DATA_61_BASE_IDX 0
#define mmROM_SW_DATA_62 0x0127
#define mmROM_SW_DATA_62_BASE_IDX 0
#define mmROM_SW_DATA_63 0x0128
#define mmROM_SW_DATA_63_BASE_IDX 0
#define mmROM_SW_DATA_64 0x0129
#define mmROM_SW_DATA_64_BASE_IDX 0
#define mmSMU_GPIOPAD_SW_INT_STAT 0x0140
#define mmSMU_GPIOPAD_SW_INT_STAT_BASE_IDX 0
#define mmSMU_GPIOPAD_MASK 0x0141
#define mmSMU_GPIOPAD_MASK_BASE_IDX 0
#define mmSMU_GPIOPAD_A 0x0142
#define mmSMU_GPIOPAD_A_BASE_IDX 0
#define mmSMU_GPIOPAD_TXIMPSEL 0x0143
#define mmSMU_GPIOPAD_TXIMPSEL_BASE_IDX 0
#define mmSMU_GPIOPAD_EN 0x0144
#define mmSMU_GPIOPAD_EN_BASE_IDX 0
#define mmSMU_GPIOPAD_Y 0x0145
#define mmSMU_GPIOPAD_Y_BASE_IDX 0
#define mmSMU_GPIOPAD_RXEN 0x0146
#define mmSMU_GPIOPAD_RXEN_BASE_IDX 0
#define mmSMU_GPIOPAD_RCVR_SEL0 0x0147
#define mmSMU_GPIOPAD_RCVR_SEL0_BASE_IDX 0
#define mmSMU_GPIOPAD_RCVR_SEL1 0x0148
#define mmSMU_GPIOPAD_RCVR_SEL1_BASE_IDX 0
#define mmSMU_GPIOPAD_PU_EN 0x0149
#define mmSMU_GPIOPAD_PU_EN_BASE_IDX 0
#define mmSMU_GPIOPAD_PD_EN 0x014a
#define mmSMU_GPIOPAD_PD_EN_BASE_IDX 0
#define mmSMU_GPIOPAD_PINSTRAPS 0x014b
#define mmSMU_GPIOPAD_PINSTRAPS_BASE_IDX 0
#define mmDFT_PINSTRAPS 0x014c
#define mmDFT_PINSTRAPS_BASE_IDX 0
#define mmSMU_GPIOPAD_INT_STAT_EN 0x014d
#define mmSMU_GPIOPAD_INT_STAT_EN_BASE_IDX 0
#define mmSMU_GPIOPAD_INT_STAT 0x014e
#define mmSMU_GPIOPAD_INT_STAT_BASE_IDX 0
#define mmSMU_GPIOPAD_INT_STAT_AK 0x014f
#define mmSMU_GPIOPAD_INT_STAT_AK_BASE_IDX 0
#define mmSMU_GPIOPAD_INT_EN 0x0150
#define mmSMU_GPIOPAD_INT_EN_BASE_IDX 0
#define mmSMU_GPIOPAD_INT_TYPE 0x0151
#define mmSMU_GPIOPAD_INT_TYPE_BASE_IDX 0
#define mmSMU_GPIOPAD_INT_POLARITY 0x0152
#define mmSMU_GPIOPAD_INT_POLARITY_BASE_IDX 0
#define mmROM_CC_BIF_PINSTRAP 0x0153
#define mmROM_CC_BIF_PINSTRAP_BASE_IDX 0
#define mmIO_SMUIO_PINSTRAP 0x0154
#define mmIO_SMUIO_PINSTRAP_BASE_IDX 0
#define mmSMUIO_PCC_CONTROL 0x0155
#define mmSMUIO_PCC_CONTROL_BASE_IDX 0
#define mmSMUIO_PCC_GPIO_SELECT 0x0156
#define mmSMUIO_PCC_GPIO_SELECT_BASE_IDX 0
#define mmSMUIO_GPIO_INT0_SELECT 0x0157
#define mmSMUIO_GPIO_INT0_SELECT_BASE_IDX 0
#define mmSMUIO_GPIO_INT1_SELECT 0x0158
#define mmSMUIO_GPIO_INT1_SELECT_BASE_IDX 0
#define mmSMUIO_GPIO_INT2_SELECT 0x0159
#define mmSMUIO_GPIO_INT2_SELECT_BASE_IDX 0
#define mmSMUIO_GPIO_INT3_SELECT 0x015a
#define mmSMUIO_GPIO_INT3_SELECT_BASE_IDX 0
#define mmSMU_GPIOPAD_MP_INT0_STAT 0x015b
#define mmSMU_GPIOPAD_MP_INT0_STAT_BASE_IDX 0
#define mmSMU_GPIOPAD_MP_INT1_STAT 0x015c
#define mmSMU_GPIOPAD_MP_INT1_STAT_BASE_IDX 0
#define mmSMU_GPIOPAD_MP_INT2_STAT 0x015d
#define mmSMU_GPIOPAD_MP_INT2_STAT_BASE_IDX 0
#define mmSMU_GPIOPAD_MP_INT3_STAT 0x015e
#define mmSMU_GPIOPAD_MP_INT3_STAT_BASE_IDX 0
#define mmSMIO_INDEX 0x015f
#define mmSMIO_INDEX_BASE_IDX 0
#define mmS0_VID_SMIO_CNTL 0x0160
#define mmS0_VID_SMIO_CNTL_BASE_IDX 0
#define mmS1_VID_SMIO_CNTL 0x0161
#define mmS1_VID_SMIO_CNTL_BASE_IDX 0
#define mmOPEN_DRAIN_SELECT 0x0162
#define mmOPEN_DRAIN_SELECT_BASE_IDX 0
#define mmSMIO_ENABLE 0x0163
#define mmSMIO_ENABLE_BASE_IDX 0
#define mmSMU_GPIOPAD_S0 0x0166
#define mmSMU_GPIOPAD_S0_BASE_IDX 0
#define mmSMU_GPIOPAD_S1 0x0167
#define mmSMU_GPIOPAD_S1_BASE_IDX 0
#define mmSMU_GPIOPAD_SCL_EN 0x0168
#define mmSMU_GPIOPAD_SCL_EN_BASE_IDX 0
#define mmSMU_GPIOPAD_SDA_EN 0x0169
#define mmSMU_GPIOPAD_SDA_EN_BASE_IDX 0
#define mmSMU_GPIOPAD_SCHMEN 0x016a
#define mmSMU_GPIOPAD_SCHMEN_BASE_IDX 0
// addressBlock: smuio_smuio_pwr_SmuSmuioDec
// base address: 0x5a800
#define mmIP_DISCOVERY_VERSION 0x0000
#define mmIP_DISCOVERY_VERSION_BASE_IDX 1
#define mmSOC_GAP_PWROK 0x00f8
#define mmSOC_GAP_PWROK_BASE_IDX 1
#define mmGFX_GAP_PWROK 0x00f9
#define mmGFX_GAP_PWROK_BASE_IDX 1
#define mmPWROK_REFCLK_GAP_CYCLES 0x00fa
#define mmPWROK_REFCLK_GAP_CYCLES_BASE_IDX 1
#define mmGOLDEN_TSC_INCREMENT_UPPER 0x0100
#define mmGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX 1
#define mmGOLDEN_TSC_INCREMENT_LOWER 0x0101
#define mmGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX 1
#define mmGOLDEN_TSC_COUNT_UPPER 0x0102
#define mmGOLDEN_TSC_COUNT_UPPER_BASE_IDX 1
#define mmGOLDEN_TSC_COUNT_LOWER 0x0103
#define mmGOLDEN_TSC_COUNT_LOWER_BASE_IDX 1
#define mmSOC_GOLDEN_TSC_SHADOW_UPPER 0x0104
#define mmSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1
#define mmSOC_GOLDEN_TSC_SHADOW_LOWER 0x0105
#define mmSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1
#define mmGFX_GOLDEN_TSC_SHADOW_UPPER 0x0106
#define mmGFX_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1
#define mmGFX_GOLDEN_TSC_SHADOW_LOWER 0x0107
#define mmGFX_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1
#define mmPWR_VIRT_RESET_REQ 0x0108
#define mmPWR_VIRT_RESET_REQ_BASE_IDX 1
#define mmSCRATCH_REGISTER0 0x0110
#define mmSCRATCH_REGISTER0_BASE_IDX 1
#define mmSCRATCH_REGISTER1 0x0111
#define mmSCRATCH_REGISTER1_BASE_IDX 1
#define mmSCRATCH_REGISTER2 0x0112
#define mmSCRATCH_REGISTER2_BASE_IDX 1
#define mmSCRATCH_REGISTER3 0x0113
#define mmSCRATCH_REGISTER3_BASE_IDX 1
#define mmSCRATCH_REGISTER4 0x0114
#define mmSCRATCH_REGISTER4_BASE_IDX 1
#define mmSCRATCH_REGISTER5 0x0115
#define mmSCRATCH_REGISTER5_BASE_IDX 1
#define mmSCRATCH_REGISTER6 0x0116
#define mmSCRATCH_REGISTER6_BASE_IDX 1
#define mmSCRATCH_REGISTER7 0x0117
#define mmSCRATCH_REGISTER7_BASE_IDX 1
#define mmPWR_DISP_TIMER_CONTROL 0x012c
#define mmPWR_DISP_TIMER_CONTROL_BASE_IDX 1
#define mmPWR_DISP_TIMER2_CONTROL 0x012e
#define mmPWR_DISP_TIMER2_CONTROL_BASE_IDX 1
#define mmPWR_DISP_TIMER_GLOBAL_CONTROL 0x0130
#define mmPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX 1
#define mmPWR_IH_CONTROL 0x0131
#define mmPWR_IH_CONTROL_BASE_IDX 1
#endif
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h 0 → 100644
View file @ d2996831
/*
* Copyright (C) 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _smuio_11_0_0_SH_MASK_HEADER
#define _smuio_11_0_0_SH_MASK_HEADER
// addressBlock: smuio_smuio_SmuSmuioDec
//SMUSVI0_TEL_PLANE0
#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR__SHIFT 0x0
#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT 0x10
#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR_MASK 0x000000FFL
#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK 0x01FF0000L
//SMUIO_MCM_CONFIG
#define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x0
#define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x2
#define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x5
#define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT 0x6
#define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000003L
#define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000001CL
#define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x00000020L
#define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x000000C0L
//SMUIO_MP_RESET_INTR
#define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT 0x0
#define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK 0x00000001L
//SMUIO_SOC_HALT
#define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN__SHIFT 0x2
#define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN__SHIFT 0x3
#define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN_MASK 0x00000004L
#define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN_MASK 0x00000008L
//SMUIO_PWRMGT
#define SMUIO_PWRMGT__i2c_clk_gate_en__SHIFT 0x0
#define SMUIO_PWRMGT__i2c1_clk_gate_en__SHIFT 0x4
#define SMUIO_PWRMGT__i2c_clk_gate_en_MASK 0x00000001L
#define SMUIO_PWRMGT__i2c1_clk_gate_en_MASK 0x00000010L
//ROM_CNTL
#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x0
#define ROM_CNTL__SPI_TIMING_RELAX__SHIFT 0x14
#define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE__SHIFT 0x15
#define ROM_CNTL__SPI_FAST_MODE__SHIFT 0x16
#define ROM_CNTL__SPI_FAST_MODE_OVERRIDE__SHIFT 0x17
#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18
#define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE__SHIFT 0x1c
#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x00000001L
#define ROM_CNTL__SPI_TIMING_RELAX_MASK 0x00100000L
#define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE_MASK 0x00200000L
#define ROM_CNTL__SPI_FAST_MODE_MASK 0x00400000L
#define ROM_CNTL__SPI_FAST_MODE_OVERRIDE_MASK 0x00800000L
#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0x0F000000L
#define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE_MASK 0x10000000L
//PAGE_MIRROR_CNTL
#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0
#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18
#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19
#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a
#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0x00FFFFFFL
#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x01000000L
#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x02000000L
#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0x0C000000L
//ROM_STATUS
#define ROM_STATUS__ROM_BUSY__SHIFT 0x0
#define ROM_STATUS__ROM_BUSY_MASK 0x00000001L
//CGTT_ROM_CLK_CTRL0
#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
//ROM_INDEX
#define ROM_INDEX__ROM_INDEX__SHIFT 0x0
#define ROM_INDEX__ROM_INDEX_MASK 0x00FFFFFFL
//ROM_DATA
#define ROM_DATA__ROM_DATA__SHIFT 0x0
#define ROM_DATA__ROM_DATA_MASK 0xFFFFFFFFL
//ROM_START
#define ROM_START__ROM_START__SHIFT 0x0
#define ROM_START__ROM_START_MASK 0x00FFFFFFL
//ROM_SW_CNTL
#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0
#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10
#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12
#define ROM_SW_CNTL__DATA_SIZE_MASK 0x0000FFFFL
#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x00030000L
#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x00040000L
//ROM_SW_STATUS
#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0
#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x00000001L
//ROM_SW_COMMAND
#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0
#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8
#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0x000000FFL
#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xFFFFFF00L
//ROM_SW_DATA_1
#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_2
#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_3
#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_4
#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_5
#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_6
#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_7
#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_8
#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_9
#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_10
#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_11
#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_12
#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_13
#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_14
#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_15
#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_16
#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_17
#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_18
#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_19
#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_20
#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_21
#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_22
#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_23
#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_24
#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_25
#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_26
#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_27
#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_28
#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_29
#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_30
#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_31
#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_32
#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_33
#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_34
#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_35
#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_36
#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_37
#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_38
#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_39
#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_40
#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_41
#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_42
#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_43
#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_44
#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_45
#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_46
#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_47
#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_48
#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_49
#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_50
#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_51
#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_52
#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_53
#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_54
#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_55
#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_56
#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_57
#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_58
#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_59
#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_60
#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_61
#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_62
#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_63
#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_64
#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xFFFFFFFFL
//SMU_GPIOPAD_SW_INT_STAT
#define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0
#define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L
//SMU_GPIOPAD_MASK
#define SMU_GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0
#define SMU_GPIOPAD_MASK__GPIO_MASK_MASK 0x7FFFFFFFL
//SMU_GPIOPAD_A
#define SMU_GPIOPAD_A__GPIO_A__SHIFT 0x0
#define SMU_GPIOPAD_A__GPIO_A_MASK 0x7FFFFFFFL
//SMU_GPIOPAD_TXIMPSEL
#define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL__SHIFT 0x0
#define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL_MASK 0x7FFFFFFFL
//SMU_GPIOPAD_EN
#define SMU_GPIOPAD_EN__GPIO_EN__SHIFT 0x0
#define SMU_GPIOPAD_EN__GPIO_EN_MASK 0x7FFFFFFFL
//SMU_GPIOPAD_Y
#define SMU_GPIOPAD_Y__GPIO_Y__SHIFT 0x0
#define SMU_GPIOPAD_Y__GPIO_Y_MASK 0x7FFFFFFFL
//SMU_GPIOPAD_RXEN
#define SMU_GPIOPAD_RXEN__GPIO_RXEN__SHIFT 0x0
#define SMU_GPIOPAD_RXEN__GPIO_RXEN_MASK 0x7FFFFFFFL
//SMU_GPIOPAD_RCVR_SEL0
#define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0__SHIFT 0x0
#define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0_MASK 0x7FFFFFFFL
//SMU_GPIOPAD_RCVR_SEL1
#define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1__SHIFT 0x0
#define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1_MASK 0x7FFFFFFFL
//SMU_GPIOPAD_PU_EN
#define SMU_GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0
#define SMU_GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7FFFFFFFL
//SMU_GPIOPAD_PD_EN
#define SMU_GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0
#define SMU_GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7FFFFFFFL
//SMU_GPIOPAD_PINSTRAPS
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L
#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L
//DFT_PINSTRAPS
#define DFT_PINSTRAPS__DFT_PINSTRAPS__SHIFT 0x0
#define DFT_PINSTRAPS__DFT_PINSTRAPS_MASK 0x000000FFL
//SMU_GPIOPAD_INT_STAT_EN
#define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0
#define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f
#define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1FFFFFFFL
#define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L
//SMU_GPIOPAD_INT_STAT
#define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0
#define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f
#define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1FFFFFFFL
#define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L
//SMU_GPIOPAD_INT_STAT_AK
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c
#define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L
#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L
#define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L
//SMU_GPIOPAD_INT_EN
#define SMU_GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0
#define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f
#define SMU_GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1FFFFFFFL
#define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L
//SMU_GPIOPAD_INT_TYPE
#define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0
#define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f
#define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1FFFFFFFL
#define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L
//SMU_GPIOPAD_INT_POLARITY
#define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0
#define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f
#define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1FFFFFFFL
#define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L
//ROM_CC_BIF_PINSTRAP
#define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN__SHIFT 0x0
#define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE__SHIFT 0x1
#define ROM_CC_BIF_PINSTRAP__ROM_CONFIG__SHIFT 0x4
#define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A__SHIFT 0x7
#define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN__SHIFT 0x8
#define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS__SHIFT 0x9
#define ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING__SHIFT 0xa
#define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN_MASK 0x00000001L
#define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE_MASK 0x0000000EL
#define ROM_CC_BIF_PINSTRAP__ROM_CONFIG_MASK 0x00000070L
#define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A_MASK 0x00000080L
#define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN_MASK 0x00000100L
#define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS_MASK 0x00000200L
#define ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING_MASK 0x00000400L
//IO_SMUIO_PINSTRAP
#define IO_SMUIO_PINSTRAP__AUD_PORT_CONN__SHIFT 0x0
#define IO_SMUIO_PINSTRAP__AUD__SHIFT 0x3
#define IO_SMUIO_PINSTRAP__BOARD_CONFIG__SHIFT 0x5
#define IO_SMUIO_PINSTRAP__SMBUS_ADDR__SHIFT 0x8
#define IO_SMUIO_PINSTRAP__AUD_PORT_CONN_MASK 0x00000007L
#define IO_SMUIO_PINSTRAP__AUD_MASK 0x00000018L
#define IO_SMUIO_PINSTRAP__BOARD_CONFIG_MASK 0x000000E0L
#define IO_SMUIO_PINSTRAP__SMBUS_ADDR_MASK 0x00000100L
//SMUIO_PCC_CONTROL
#define SMUIO_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0
#define SMUIO_PCC_CONTROL__PCC_POLARITY_MASK 0x00000001L
//SMUIO_PCC_GPIO_SELECT
#define SMUIO_PCC_GPIO_SELECT__GPIO__SHIFT 0x0
#define SMUIO_PCC_GPIO_SELECT__GPIO_MASK 0xFFFFFFFFL
//SMUIO_GPIO_INT0_SELECT
#define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT__SHIFT 0x0
#define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT_MASK 0xFFFFFFFFL
//SMUIO_GPIO_INT1_SELECT
#define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT__SHIFT 0x0
#define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT_MASK 0xFFFFFFFFL
//SMUIO_GPIO_INT2_SELECT
#define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT__SHIFT 0x0
#define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT_MASK 0xFFFFFFFFL
//SMUIO_GPIO_INT3_SELECT
#define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT__SHIFT 0x0
#define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT_MASK 0xFFFFFFFFL
//SMU_GPIOPAD_MP_INT0_STAT
#define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT__SHIFT 0x0
#define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT_MASK 0x1FFFFFFFL
//SMU_GPIOPAD_MP_INT1_STAT
#define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT__SHIFT 0x0
#define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT_MASK 0x1FFFFFFFL
//SMU_GPIOPAD_MP_INT2_STAT
#define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT__SHIFT 0x0
#define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT_MASK 0x1FFFFFFFL
//SMU_GPIOPAD_MP_INT3_STAT
#define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT__SHIFT 0x0
#define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT_MASK 0x1FFFFFFFL
//SMIO_INDEX
#define SMIO_INDEX__SW_SMIO_INDEX__SHIFT 0x0
#define SMIO_INDEX__SW_SMIO_INDEX_MASK 0x00000001L
//S0_VID_SMIO_CNTL
#define S0_VID_SMIO_CNTL__S0_SMIO_VALUES__SHIFT 0x0
#define S0_VID_SMIO_CNTL__S0_SMIO_VALUES_MASK 0xFFFFFFFFL
//S1_VID_SMIO_CNTL
#define S1_VID_SMIO_CNTL__S1_SMIO_VALUES__SHIFT 0x0
#define S1_VID_SMIO_CNTL__S1_SMIO_VALUES_MASK 0xFFFFFFFFL
//OPEN_DRAIN_SELECT
#define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT 0x0
#define OPEN_DRAIN_SELECT__RESERVED__SHIFT 0x1f
#define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK 0x7FFFFFFFL
#define OPEN_DRAIN_SELECT__RESERVED_MASK 0x80000000L
//SMIO_ENABLE
#define SMIO_ENABLE__SMIO_ENABLE__SHIFT 0x0
#define SMIO_ENABLE__SMIO_ENABLE_MASK 0xFFFFFFFFL
//SMU_GPIOPAD_S0
#define SMU_GPIOPAD_S0__GPIO_S0__SHIFT 0x0
#define SMU_GPIOPAD_S0__GPIO_S0_MASK 0x7FFFFFFFL
//SMU_GPIOPAD_S1
#define SMU_GPIOPAD_S1__GPIO_S1__SHIFT 0x0
#define SMU_GPIOPAD_S1__GPIO_S1_MASK 0x7FFFFFFFL
//SMU_GPIOPAD_SCL_EN
#define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN__SHIFT 0x0
#define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN_MASK 0x7FFFFFFFL
//SMU_GPIOPAD_SDA_EN
#define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN__SHIFT 0x0
#define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN_MASK 0x7FFFFFFFL
//SMU_GPIOPAD_SCHMEN
#define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN__SHIFT 0x0
#define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN_MASK 0x7FFFFFFFL
// addressBlock: smuio_smuio_pwr_SmuSmuioDec
//IP_DISCOVERY_VERSION
#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT 0x0
#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK 0xFFFFFFFFL
//SOC_GAP_PWROK
#define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT 0x0
#define SOC_GAP_PWROK__soc_gap_pwrok_MASK 0x00000001L
//GFX_GAP_PWROK
#define GFX_GAP_PWROK__gfx_gap_pwrok__SHIFT 0x0
#define GFX_GAP_PWROK__gfx_gap_pwrok_MASK 0x00000001L
//PWROK_REFCLK_GAP_CYCLES
#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT 0x0
#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT 0x8
#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK 0x000000FFL
#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK 0x0000FF00L
//GOLDEN_TSC_INCREMENT_UPPER
#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT 0x0
#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK 0x00FFFFFFL
//GOLDEN_TSC_INCREMENT_LOWER
#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT 0x0
#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK 0xFFFFFFFFL
//GOLDEN_TSC_COUNT_UPPER
#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT 0x0
#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK 0x00FFFFFFL
//GOLDEN_TSC_COUNT_LOWER
#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT 0x0
#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK 0xFFFFFFFFL
//SOC_GOLDEN_TSC_SHADOW_UPPER
#define SOC_GOLDEN_TSC_SHADOW_UPPER__SOCGoldenTscShadowUpper__SHIFT 0x0
#define SOC_GOLDEN_TSC_SHADOW_UPPER__SOCGoldenTscShadowUpper_MASK 0x00FFFFFFL
//SOC_GOLDEN_TSC_SHADOW_LOWER
#define SOC_GOLDEN_TSC_SHADOW_LOWER__SOCGoldenTscShadowLower__SHIFT 0x0
#define SOC_GOLDEN_TSC_SHADOW_LOWER__SOCGoldenTscShadowLower_MASK 0xFFFFFFFFL
//GFX_GOLDEN_TSC_SHADOW_UPPER
#define GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper__SHIFT 0x0
#define GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper_MASK 0x00FFFFFFL
//GFX_GOLDEN_TSC_SHADOW_LOWER
#define GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower__SHIFT 0x0
#define GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower_MASK 0xFFFFFFFFL
//PWR_VIRT_RESET_REQ
#define PWR_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0
#define PWR_VIRT_RESET_REQ__PF_FLR__SHIFT 0x1f
#define PWR_VIRT_RESET_REQ__VF_FLR_MASK 0x7FFFFFFFL
#define PWR_VIRT_RESET_REQ__PF_FLR_MASK 0x80000000L
//SCRATCH_REGISTER0
#define SCRATCH_REGISTER0__ScratchPad0__SHIFT 0x0
#define SCRATCH_REGISTER0__ScratchPad0_MASK 0xFFFFFFFFL
//SCRATCH_REGISTER1
#define SCRATCH_REGISTER1__ScratchPad1__SHIFT 0x0
#define SCRATCH_REGISTER1__ScratchPad1_MASK 0xFFFFFFFFL
//SCRATCH_REGISTER2
#define SCRATCH_REGISTER2__ScratchPad2__SHIFT 0x0
#define SCRATCH_REGISTER2__ScratchPad2_MASK 0xFFFFFFFFL
//SCRATCH_REGISTER3
#define SCRATCH_REGISTER3__ScratchPad3__SHIFT 0x0
#define SCRATCH_REGISTER3__ScratchPad3_MASK 0xFFFFFFFFL
//SCRATCH_REGISTER4
#define SCRATCH_REGISTER4__ScratchPad4__SHIFT 0x0
#define SCRATCH_REGISTER4__ScratchPad4_MASK 0xFFFFFFFFL
//SCRATCH_REGISTER5
#define SCRATCH_REGISTER5__ScratchPad5__SHIFT 0x0
#define SCRATCH_REGISTER5__ScratchPad5_MASK 0xFFFFFFFFL
//SCRATCH_REGISTER6
#define SCRATCH_REGISTER6__ScratchPad6__SHIFT 0x0
#define SCRATCH_REGISTER6__ScratchPad6_MASK 0xFFFFFFFFL
//SCRATCH_REGISTER7
#define SCRATCH_REGISTER7__ScratchPad7__SHIFT 0x0
#define SCRATCH_REGISTER7__ScratchPad7_MASK 0xFFFFFFFFL
//PWR_DISP_TIMER_CONTROL
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L
#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L
//PWR_DISP_TIMER2_CONTROL
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L
#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L
//PWR_DISP_TIMER_GLOBAL_CONTROL
#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0
#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa
#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK 0x000003FFL
#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK 0x00000400L
//PWR_IH_CONTROL
#define PWR_IH_CONTROL__MAX_CREDIT__SHIFT 0x0
#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT 0x5
#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT 0x6
#define PWR_IH_CONTROL__MAX_CREDIT_MASK 0x0000001FL
#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK 0x00000020L
#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK 0x00000040L
#endif
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7