Commit d46f1c3f authored by Chris Wilson's avatar Chris Wilson Committed by Daniel Vetter

drm/i915: Allow the GPU to cache stolen memory

As a corollary to reviewing the interaction between LLC and our cache
domains, the GPU PTE bits are independent of the CPU PAT bits. As such
we can set the cache level on stolen memory based on how we wish the GPU
to cache accesses to it. So we are free to set the same default cache
levels as for normal bo, i.e. enable LLC cacheing by default where
appropriate.
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 2c22569b
...@@ -287,9 +287,8 @@ _i915_gem_object_create_stolen(struct drm_device *dev, ...@@ -287,9 +287,8 @@ _i915_gem_object_create_stolen(struct drm_device *dev,
i915_gem_object_pin_pages(obj); i915_gem_object_pin_pages(obj);
obj->stolen = stolen; obj->stolen = stolen;
obj->base.write_domain = I915_GEM_DOMAIN_GTT; obj->base.read_domains = I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT;
obj->base.read_domains = I915_GEM_DOMAIN_GTT; obj->cache_level = HAS_LLC(dev) ? I915_CACHE_LLC : I915_CACHE_NONE;
obj->cache_level = I915_CACHE_NONE;
return obj; return obj;
......
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